Re: [edk2-platforms][Patch 1/3] CoffeelakeSiliconPkg/BaseSmbusLib: Fix SmBusSendByte value

["Chiu, Chasel" <chasel.chiu@intel.com>]

Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>

> -----Original Message-----
> From: Kinney, Michael D <michael.d.kinney@intel.com>
> Sent: Friday, June 11, 2021 6:46 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Chaganty, Rangasai V
> <rangasai.v.chaganty@intel.com>
> Subject: [edk2-platforms][Patch 1/3] CoffeelakeSiliconPkg/BaseSmbusLib: Fix
> SmBusSendByte value
> 
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3450
> 
> Update SmBusSendByte() to write value to Command Register instead of Host
> Data registers.
> 
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
> ---
>  .../Pch/Library/BaseSmbusLib/BaseSmbusLib.c   | 24 +++++++++++++------
>  1 file changed, 17 insertions(+), 7 deletions(-)
> 
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseSmbusLib/BaseSmbusLib.c
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseSmbusLib/BaseSmbusLib.c
> index 3d6386d433..dacf9d03b2 100644
> ---
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseSmbusLib/BaseSmbusLib.c
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseSmbusLib/BaseSm
> +++ busLib.c
> @@ -203,14 +203,24 @@ InternalSmBusNonBlock (
>      AuxiliaryControl |= B_SMBUS_IO_AAC;
>    }
>    //
> -  // Set Host Commond Register.
> +  // We do not need Data Register for SendByte Command
>    //
> -  IoWrite8 (IoPortBaseAddress + R_SMBUS_IO_HCMD, (UINT8)
> SMBUS_LIB_COMMAND (SmBusAddress));
> -  //
> -  // Write value to Host Data 0 and Host Data 1 Registers.
> -  //
> -  IoWrite8 (IoPortBaseAddress + R_SMBUS_IO_HD0, (UINT8) Value);
> -  IoWrite8 (IoPortBaseAddress + R_SMBUS_IO_HD1, (UINT8) (Value >> 8));
> +  if ((HostControl == V_SMBUS_IO_SMB_CMD_BYTE) && ((SmBusAddress &
> BIT0) == B_SMBUS_IO_WRITE)) {
> +    //
> +    // Set Host Command Register.
> +    //
> +    IoWrite8 (IoPortBaseAddress + R_SMBUS_IO_HCMD, (UINT8)Value);  }
> + else {
> +    //
> +    // Set Host Command Register.
> +    //
> +    IoWrite8 (IoPortBaseAddress + R_SMBUS_IO_HCMD, (UINT8)
> SMBUS_LIB_COMMAND (SmBusAddress));
> +    //
> +    // Write value to Host Data 0 and Host Data 1 Registers.
> +    //
> +    IoWrite8 (IoPortBaseAddress + R_SMBUS_IO_HD0, (UINT8) Value);
> +    IoWrite8 (IoPortBaseAddress + R_SMBUS_IO_HD1, (UINT8) (Value >>
> + 8));  }
>    //
>    // Set Auxiliary Control Regiester.
>    //
> --
> 2.31.1.windows.1