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* [PATCH v2] IntelFsp2Pkg: FSP should support input UPD as NULL.
@ 2022-11-02  5:46 Chiu, Chasel
  2022-11-03  0:18 ` Nate DeSimone
  2022-11-03  2:32 ` [edk2-devel] " Kuo, Ted
  0 siblings, 2 replies; 6+ messages in thread
From: Chiu, Chasel @ 2022-11-02  5:46 UTC (permalink / raw)
  To: devel; +Cc: Chasel Chiu, Nate DeSimone, Star Zeng

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4114

FSP specification supports input UPD as NULL cases which FSP will
use built-in UPD region instead.
FSP should not return INVALID_PARAMETER in such cases.

In FSP-T entry point case, the valid FSP-T UPD region pointer will be
passed to platform FSP code to consume.
In FSP-M and FSP-S cases, valid UPD pointer will be decided when
updating corresponding pointer field in FspGlobalData.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
 IntelFsp2Pkg/FspSecCore/SecFspApiChk.c         | 12 ++++++++++--
 IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 73 +++++++++++++++++++++++++++++++++++++++++++++++++++++++------------------
 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm  | 40 ++++++++++++++++++++++++++--------------
 3 files changed, 91 insertions(+), 34 deletions(-)

diff --git a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
index a44fbf2a50..5f59938518 100644
--- a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
+++ b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
@@ -44,6 +44,8 @@ FspApiCallingCheck (
     //
     if (((UINTN)FspData != MAX_ADDRESS) && ((UINTN)FspData != MAX_UINT32)) {
       Status = EFI_UNSUPPORTED;
+    } else if (ApiParam == NULL) {
+      Status = EFI_SUCCESS;
     } else if (EFI_ERROR (FspUpdSignatureCheck (ApiIdx, ApiParam))) {
       Status = EFI_INVALID_PARAMETER;
     }
@@ -67,9 +69,13 @@ FspApiCallingCheck (
     } else {
       if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE) {
         Status = EFI_UNSUPPORTED;
-      } else if (EFI_ERROR (FspUpdSignatureCheck (FspSiliconInitApiIndex, ApiParam))) {
-        Status = EFI_INVALID_PARAMETER;
       } else if (ApiIdx == FspSiliconInitApiIndex) {
+        if (ApiParam == NULL) {
+          Status = EFI_SUCCESS;
+        } else if (EFI_ERROR (FspUpdSignatureCheck (FspSiliconInitApiIndex, ApiParam))) {
+          Status = EFI_INVALID_PARAMETER;
+        }
+
         //
         // Reset MultiPhase NumberOfPhases to zero
         //
@@ -89,6 +95,8 @@ FspApiCallingCheck (
     } else {
       if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE) {
         Status = EFI_UNSUPPORTED;
+      } else if (ApiParam == NULL) {
+        Status = EFI_SUCCESS;
       } else if (EFI_ERROR (FspUpdSignatureCheck (FspSmmInitApiIndex, ApiParam))) {
         Status = EFI_INVALID_PARAMETER;
       }
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
index 61030a843b..73821ad22a 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
@@ -21,7 +21,7 @@ extern   ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))
 ; Following functions will be provided in PlatformSecLib
 ;
 extern ASM_PFX(AsmGetFspBaseAddress)
-extern ASM_PFX(AsmGetFspInfoHeader)
+extern ASM_PFX(AsmGetFspInfoHeaderNoStack)
 ;extern ASM_PFX(LoadMicrocode)    ; @todo: needs a weak implementation
 extern ASM_PFX(SecPlatformInit)   ; @todo: needs a weak implementation
 extern ASM_PFX(SecCarInit)
@@ -160,6 +160,47 @@ endstruc
          RET_ESI_EXT   mm7
 %endmacro
 
+%macro CALL_EDI  1
+
+  mov     edi,  %%ReturnAddress
+  jmp     %1
+%%ReturnAddress:
+
+%endmacro
+
+%macro CALL_EBP 1
+  mov     ebp, %%ReturnAddress
+  jmp     %1
+%%ReturnAddress:
+%endmacro
+
+%macro RET_EBP 0
+  jmp     ebp                           ; restore EIP from EBP
+%endmacro
+
+;
+; Load UPD region pointer in ECX
+;
+global ASM_PFX(LoadUpdPointerToECX)
+ASM_PFX(LoadUpdPointerToECX):
+  ;
+  ; esp + 4 is input UPD parameter
+  ; If esp + 4 is NULL the default UPD should be used
+  ; ecx will be the UPD region that should be used
+  ;
+  mov       ecx, dword [esp + 4]
+  cmp       ecx, 0
+  jnz       ParamValid
+
+  ;
+  ; Fall back to default UPD region
+  ;
+  CALL_EDI  ASM_PFX(AsmGetFspInfoHeaderNoStack)
+  mov       ecx, DWORD [eax + 01Ch]      ; Read FsptImageBaseAddress
+  add       ecx, DWORD [eax + 024h]      ; Get Cfg Region base address = FsptImageBaseAddress + CfgRegionOffset
+ParamValid:
+  RET_EBP
+
 ;
 ; @todo: The strong/weak implementation does not work.
 ;        This needs to be reviewed later.
@@ -187,10 +228,9 @@ endstruc
 global ASM_PFX(LoadMicrocodeDefault)
 ASM_PFX(LoadMicrocodeDefault):
    ; Inputs:
-   ;   esp -> LoadMicrocodeParams pointer
+   ;   ecx -> UPD region contains LoadMicrocodeParams pointer
    ; Register Usage:
-   ;   esp  Preserved
-   ;   All others destroyed
+   ;   All are destroyed
    ; Assumptions:
    ;   No memory available, stack is hard-coded and used for return address
    ;   Executed by SBSP and NBSP
@@ -201,12 +241,9 @@ ASM_PFX(LoadMicrocodeDefault):
    ;
    movd   ebp, mm7
 
+   mov    esp, ecx  ; ECX has been assigned to UPD region
    cmp    esp, 0
    jz     ParamError
-   mov    eax, dword [esp + 4]    ; Parameter pointer
-   cmp    eax, 0
-   jz     ParamError
-   mov    esp, eax
 
    ; skip loading Microcode if the MicrocodeCodeSize is zero
    ; and report error if size is less than 2k
@@ -444,13 +481,15 @@ Done:
 Exit2:
    jmp   ebp
 
-
+;
+; EstablishStackFsp: EDI should be preserved cross this function
+;
 global ASM_PFX(EstablishStackFsp)
 ASM_PFX(EstablishStackFsp):
   ;
   ; Save parameter pointer in edx
   ;
-  mov       edx, dword [esp + 4]
+  mov       edx, ecx   ; ECX has been assigned to UPD region
 
   ;
   ; Enable FSP STACK
@@ -555,39 +594,37 @@ ASM_PFX(TempRamInitApi):
   SAVE_EAX
   SAVE_EDX
 
-  ;
-  ; Check Parameter
-  ;
-  mov       eax, dword [esp + 4]
-  cmp       eax, 0
-  mov       eax, 80000002h
-  jz        TempRamInitExit
-
   ;
   ; Sec Platform Init
   ;
+  CALL_EBP  ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param
   CALL_MMX  ASM_PFX(SecPlatformInit)
   cmp       eax, 0
   jnz       TempRamInitExit
 
   ; Load microcode
   LOAD_ESP
+  CALL_EBP  ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param
   CALL_MMX  ASM_PFX(LoadMicrocodeDefault)
   SXMMN     xmm6, 3, eax            ;Save microcode return status in ECX-SLOT 3 in xmm6.
   ;@note If return value eax is not 0, microcode did not load, but continue and attempt to boot.
 
   ; Call Sec CAR Init
   LOAD_ESP
+  CALL_EBP  ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param
   CALL_MMX  ASM_PFX(SecCarInit)
   cmp       eax, 0
   jnz       TempRamInitExit
 
   LOAD_ESP
+  CALL_EBP  ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param
+  mov       edi, ecx                     ; Save UPD param to EDI for later code use
   CALL_MMX  ASM_PFX(EstablishStackFsp)
   cmp       eax, 0
   jnz       TempRamInitExit
 
   LXMMN     xmm6, eax, 3  ;Restore microcode status if no CAR init error from ECX-SLOT 3 in xmm6.
+  SXMMN     xmm6, 3, edi  ;Save FSP-T UPD parameter pointer in ECX-SLOT 3 in xmm6.
 
 TempRamInitExit:
   mov       bl, al                  ; save al data in bl
diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
index 7dd89c531a..cdebe90fab 100644
--- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
@@ -21,7 +21,7 @@ extern   ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))
 ; Following functions will be provided in PlatformSecLib
 ;
 extern ASM_PFX(AsmGetFspBaseAddress)
-extern ASM_PFX(AsmGetFspInfoHeader)
+extern ASM_PFX(AsmGetFspInfoHeaderNoStack)
 ;extern ASM_PFX(LoadMicrocode)    ; @todo: needs a weak implementation
 extern ASM_PFX(SecPlatformInit)   ; @todo: needs a weak implementation
 extern ASM_PFX(SecCarInit)
@@ -87,6 +87,14 @@ struc LoadMicrocodeParamsFsp24
     .size:
 endstruc
 
+%macro CALL_RDI  1
+
+  mov     rdi,  %%ReturnAddress
+  jmp     %1
+%%ReturnAddress:
+
+%endmacro
+
 ;
 ; @todo: The strong/weak implementation does not work.
 ;        This needs to be reviewed later.
@@ -116,8 +124,7 @@ ASM_PFX(LoadMicrocodeDefault):
    ; Inputs:
    ;   rcx -> LoadMicrocodeParams pointer
    ; Register Usage:
-   ;   rsp  Preserved
-   ;   All others destroyed
+   ;   All are destroyed
    ; Assumptions:
    ;   No memory available, stack is hard-coded and used for return address
    ;   Executed by SBSP and NBSP
@@ -420,10 +427,6 @@ ASM_PFX(TempRamInitApi):
   ENABLE_SSE
   ENABLE_AVX
   ;
-  ; Save Input Parameter in YMM10
-  ;
-  SAVE_RCX
-  ;
   ; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and YMM6
   ;
   SAVE_REGS
@@ -433,6 +436,22 @@ ASM_PFX(TempRamInitApi):
   ;
   SAVE_BFV  rbp
 
+  ;
+  ; Save Input Parameter in YMM10
+  ;
+  cmp       rcx, 0
+  jnz       ParamValid
+
+  ;
+  ; Fall back to default UPD
+  ;
+  CALL_RDI  ASM_PFX(AsmGetFspInfoHeaderNoStack)
+  xor       rcx, rcx
+  mov       ecx,  DWORD [rax + 01Ch]      ; Read FsptImageBaseAddress
+  add       ecx,  DWORD [rax + 024h]      ; Get Cfg Region base address = FsptImageBaseAddress + CfgRegionOffset
+ParamValid:
+  SAVE_RCX
+
   ;
   ; Save timestamp into YMM6
   ;
@@ -441,13 +460,6 @@ ASM_PFX(TempRamInitApi):
   or        rax, rdx
   SAVE_TS   rax
 
-  ;
-  ; Check Parameter
-  ;
-  cmp       rcx, 0
-  mov       rcx, 08000000000000002h
-  jz        TempRamInitExit
-
   ;
   ; Sec Platform Init
   ;
-- 
2.35.0.windows.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* Re: [PATCH v2] IntelFsp2Pkg: FSP should support input UPD as NULL.
  2022-11-02  5:46 [PATCH v2] IntelFsp2Pkg: FSP should support input UPD as NULL Chiu, Chasel
@ 2022-11-03  0:18 ` Nate DeSimone
  2022-11-03  2:32 ` [edk2-devel] " Kuo, Ted
  1 sibling, 0 replies; 6+ messages in thread
From: Nate DeSimone @ 2022-11-03  0:18 UTC (permalink / raw)
  To: Chiu, Chasel, devel@edk2.groups.io; +Cc: Zeng, Star

Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

-----Original Message-----
From: Chiu, Chasel <chasel.chiu@intel.com> 
Sent: Tuesday, November 1, 2022 10:46 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel <chasel.chiu@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Zeng, Star <star.zeng@intel.com>
Subject: [PATCH v2] IntelFsp2Pkg: FSP should support input UPD as NULL.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4114

FSP specification supports input UPD as NULL cases which FSP will use built-in UPD region instead.
FSP should not return INVALID_PARAMETER in such cases.

In FSP-T entry point case, the valid FSP-T UPD region pointer will be passed to platform FSP code to consume.
In FSP-M and FSP-S cases, valid UPD pointer will be decided when updating corresponding pointer field in FspGlobalData.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
 IntelFsp2Pkg/FspSecCore/SecFspApiChk.c         | 12 ++++++++++--
 IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 73 +++++++++++++++++++++++++++++++++++++++++++++++++++++++------------------
 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm  | 40 ++++++++++++++++++++++++++--------------
 3 files changed, 91 insertions(+), 34 deletions(-)

diff --git a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
index a44fbf2a50..5f59938518 100644
--- a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
+++ b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
@@ -44,6 +44,8 @@ FspApiCallingCheck (
     //     if (((UINTN)FspData != MAX_ADDRESS) && ((UINTN)FspData != MAX_UINT32)) {       Status = EFI_UNSUPPORTED;+    } else if (ApiParam == NULL) {+      Status = EFI_SUCCESS;     } else if (EFI_ERROR (FspUpdSignatureCheck (ApiIdx, ApiParam))) {       Status = EFI_INVALID_PARAMETER;     }@@ -67,9 +69,13 @@ FspApiCallingCheck (
     } else {       if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE) {         Status = EFI_UNSUPPORTED;-      } else if (EFI_ERROR (FspUpdSignatureCheck (FspSiliconInitApiIndex, ApiParam))) {-        Status = EFI_INVALID_PARAMETER;       } else if (ApiIdx == FspSiliconInitApiIndex) {+        if (ApiParam == NULL) {+          Status = EFI_SUCCESS;+        } else if (EFI_ERROR (FspUpdSignatureCheck (FspSiliconInitApiIndex, ApiParam))) {+          Status = EFI_INVALID_PARAMETER;+        }+         //         // Reset MultiPhase NumberOfPhases to zero         //@@ -89,6 +95,8 @@ FspApiCallingCheck (
     } else {       if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE) {         Status = EFI_UNSUPPORTED;+      } else if (ApiParam == NULL) {+        Status = EFI_SUCCESS;       } else if (EFI_ERROR (FspUpdSignatureCheck (FspSmmInitApiIndex, ApiParam))) {         Status = EFI_INVALID_PARAMETER;       }diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
index 61030a843b..73821ad22a 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
@@ -21,7 +21,7 @@ extern   ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))
 ; Following functions will be provided in PlatformSecLib ; extern ASM_PFX(AsmGetFspBaseAddress)-extern ASM_PFX(AsmGetFspInfoHeader)+extern ASM_PFX(AsmGetFspInfoHeaderNoStack) ;extern ASM_PFX(LoadMicrocode)    ; @todo: needs a weak implementation extern ASM_PFX(SecPlatformInit)   ; @todo: needs a weak implementation extern ASM_PFX(SecCarInit)@@ -160,6 +160,47 @@ endstruc
          RET_ESI_EXT   mm7 %endmacro +%macro CALL_EDI  1++  mov     edi,  %%ReturnAddress+  jmp     %1+%%ReturnAddress:++%endmacro++%macro CALL_EBP 1+  mov     ebp, %%ReturnAddress+  jmp     %1+%%ReturnAddress:+%endmacro++%macro RET_EBP 0+  jmp     ebp                           ; restore EIP from EBP+%endmacro++;+; Load UPD region pointer in ECX+;+global ASM_PFX(LoadUpdPointerToECX)+ASM_PFX(LoadUpdPointerToECX):+  ;+  ; esp + 4 is input UPD parameter+  ; If esp + 4 is NULL the default UPD should be used+  ; ecx will be the UPD region that should be used+  ;+  mov       ecx, dword [esp + 4]+  cmp       ecx, 0+  jnz       ParamValid++  ;+  ; Fall back to default UPD region+  ;+  CALL_EDI  ASM_PFX(AsmGetFspInfoHeaderNoStack)+  mov       ecx, DWORD [eax + 01Ch]      ; Read FsptImageBaseAddress+  add       ecx, DWORD [eax + 024h]      ; Get Cfg Region base address = FsptImageBaseAddress + CfgRegionOffset+ParamValid:+  RET_EBP+ ; ; @todo: The strong/weak implementation does not work. ;        This needs to be reviewed later.@@ -187,10 +228,9 @@ endstruc
 global ASM_PFX(LoadMicrocodeDefault) ASM_PFX(LoadMicrocodeDefault):    ; Inputs:-   ;   esp -> LoadMicrocodeParams pointer+   ;   ecx -> UPD region contains LoadMicrocodeParams pointer    ; Register Usage:-   ;   esp  Preserved-   ;   All others destroyed+   ;   All are destroyed    ; Assumptions:    ;   No memory available, stack is hard-coded and used for return address    ;   Executed by SBSP and NBSP@@ -201,12 +241,9 @@ ASM_PFX(LoadMicrocodeDefault):
    ;    movd   ebp, mm7 +   mov    esp, ecx  ; ECX has been assigned to UPD region    cmp    esp, 0    jz     ParamError-   mov    eax, dword [esp + 4]    ; Parameter pointer-   cmp    eax, 0-   jz     ParamError-   mov    esp, eax     ; skip loading Microcode if the MicrocodeCodeSize is zero    ; and report error if size is less than 2k@@ -444,13 +481,15 @@ Done:
 Exit2:    jmp   ebp -+;+; EstablishStackFsp: EDI should be preserved cross this function+; global ASM_PFX(EstablishStackFsp) ASM_PFX(EstablishStackFsp):   ;   ; Save parameter pointer in edx   ;-  mov       edx, dword [esp + 4]+  mov       edx, ecx   ; ECX has been assigned to UPD region    ;   ; Enable FSP STACK@@ -555,39 +594,37 @@ ASM_PFX(TempRamInitApi):
   SAVE_EAX   SAVE_EDX -  ;-  ; Check Parameter-  ;-  mov       eax, dword [esp + 4]-  cmp       eax, 0-  mov       eax, 80000002h-  jz        TempRamInitExit-   ;   ; Sec Platform Init   ;+  CALL_EBP  ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param   CALL_MMX  ASM_PFX(SecPlatformInit)   cmp       eax, 0   jnz       TempRamInitExit    ; Load microcode   LOAD_ESP+  CALL_EBP  ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param   CALL_MMX  ASM_PFX(LoadMicrocodeDefault)   SXMMN     xmm6, 3, eax            ;Save microcode return status in ECX-SLOT 3 in xmm6.   ;@note If return value eax is not 0, microcode did not load, but continue and attempt to boot.    ; Call Sec CAR Init   LOAD_ESP+  CALL_EBP  ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param   CALL_MMX  ASM_PFX(SecCarInit)   cmp       eax, 0   jnz       TempRamInitExit    LOAD_ESP+  CALL_EBP  ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param+  mov       edi, ecx                     ; Save UPD param to EDI for later code use   CALL_MMX  ASM_PFX(EstablishStackFsp)   cmp       eax, 0   jnz       TempRamInitExit    LXMMN     xmm6, eax, 3  ;Restore microcode status if no CAR init error from ECX-SLOT 3 in xmm6.+  SXMMN     xmm6, 3, edi  ;Save FSP-T UPD parameter pointer in ECX-SLOT 3 in xmm6.  TempRamInitExit:   mov       bl, al                  ; save al data in bldiff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
index 7dd89c531a..cdebe90fab 100644
--- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
@@ -21,7 +21,7 @@ extern   ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))
 ; Following functions will be provided in PlatformSecLib ; extern ASM_PFX(AsmGetFspBaseAddress)-extern ASM_PFX(AsmGetFspInfoHeader)+extern ASM_PFX(AsmGetFspInfoHeaderNoStack) ;extern ASM_PFX(LoadMicrocode)    ; @todo: needs a weak implementation extern ASM_PFX(SecPlatformInit)   ; @todo: needs a weak implementation extern ASM_PFX(SecCarInit)@@ -87,6 +87,14 @@ struc LoadMicrocodeParamsFsp24
     .size: endstruc +%macro CALL_RDI  1++  mov     rdi,  %%ReturnAddress+  jmp     %1+%%ReturnAddress:++%endmacro+ ; ; @todo: The strong/weak implementation does not work. ;        This needs to be reviewed later.@@ -116,8 +124,7 @@ ASM_PFX(LoadMicrocodeDefault):
    ; Inputs:    ;   rcx -> LoadMicrocodeParams pointer    ; Register Usage:-   ;   rsp  Preserved-   ;   All others destroyed+   ;   All are destroyed    ; Assumptions:    ;   No memory available, stack is hard-coded and used for return address    ;   Executed by SBSP and NBSP@@ -420,10 +427,6 @@ ASM_PFX(TempRamInitApi):
   ENABLE_SSE   ENABLE_AVX   ;-  ; Save Input Parameter in YMM10-  ;-  SAVE_RCX-  ;   ; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and YMM6   ;   SAVE_REGS@@ -433,6 +436,22 @@ ASM_PFX(TempRamInitApi):
   ;   SAVE_BFV  rbp +  ;+  ; Save Input Parameter in YMM10+  ;+  cmp       rcx, 0+  jnz       ParamValid++  ;+  ; Fall back to default UPD+  ;+  CALL_RDI  ASM_PFX(AsmGetFspInfoHeaderNoStack)+  xor       rcx, rcx+  mov       ecx,  DWORD [rax + 01Ch]      ; Read FsptImageBaseAddress+  add       ecx,  DWORD [rax + 024h]      ; Get Cfg Region base address = FsptImageBaseAddress + CfgRegionOffset+ParamValid:+  SAVE_RCX+   ;   ; Save timestamp into YMM6   ;@@ -441,13 +460,6 @@ ASM_PFX(TempRamInitApi):
   or        rax, rdx   SAVE_TS   rax -  ;-  ; Check Parameter-  ;-  cmp       rcx, 0-  mov       rcx, 08000000000000002h-  jz        TempRamInitExit-   ;   ; Sec Platform Init   ;-- 
2.35.0.windows.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* Re: [edk2-devel] [PATCH v2] IntelFsp2Pkg: FSP should support input UPD as NULL.
  2022-11-02  5:46 [PATCH v2] IntelFsp2Pkg: FSP should support input UPD as NULL Chiu, Chasel
  2022-11-03  0:18 ` Nate DeSimone
@ 2022-11-03  2:32 ` Kuo, Ted
  2022-11-03 17:01   ` Chiu, Chasel
  1 sibling, 1 reply; 6+ messages in thread
From: Kuo, Ted @ 2022-11-03  2:32 UTC (permalink / raw)
  To: devel@edk2.groups.io, Chiu, Chasel; +Cc: Desimone, Nathaniel L, Zeng, Star

Hi Chasel,

I have few comments. Please find [Ted] inline.

Thanks,
Ted

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Chiu, Chasel
Sent: Wednesday, November 2, 2022 1:46 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel <chasel.chiu@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Zeng, Star <star.zeng@intel.com>
Subject: [edk2-devel] [PATCH v2] IntelFsp2Pkg: FSP should support input UPD as NULL.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4114

FSP specification supports input UPD as NULL cases which FSP will
use built-in UPD region instead.
FSP should not return INVALID_PARAMETER in such cases.

In FSP-T entry point case, the valid FSP-T UPD region pointer will be
passed to platform FSP code to consume.
In FSP-M and FSP-S cases, valid UPD pointer will be decided when
updating corresponding pointer field in FspGlobalData.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
 IntelFsp2Pkg/FspSecCore/SecFspApiChk.c         | 12 ++++++++++--
 IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 73 +++++++++++++++++++++++++++++++++++++++++++++++++++++++------------------
 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm  | 40 ++++++++++++++++++++++++++--------------
 3 files changed, 91 insertions(+), 34 deletions(-)

diff --git a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
index a44fbf2a50..5f59938518 100644
--- a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
+++ b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
@@ -44,6 +44,8 @@ FspApiCallingCheck (
     //
     if (((UINTN)FspData != MAX_ADDRESS) && ((UINTN)FspData != MAX_UINT32)) {
       Status = EFI_UNSUPPORTED;
+    } else if (ApiParam == NULL) {
+      Status = EFI_SUCCESS;
     } else if (EFI_ERROR (FspUpdSignatureCheck (ApiIdx, ApiParam))) {
       Status = EFI_INVALID_PARAMETER;
     }
@@ -67,9 +69,13 @@ FspApiCallingCheck (
     } else {
       if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE) {
         Status = EFI_UNSUPPORTED;
-      } else if (EFI_ERROR (FspUpdSignatureCheck (FspSiliconInitApiIndex, ApiParam))) {
-        Status = EFI_INVALID_PARAMETER;
       } else if (ApiIdx == FspSiliconInitApiIndex) {
+        if (ApiParam == NULL) {
+          Status = EFI_SUCCESS;
+        } else if (EFI_ERROR (FspUpdSignatureCheck (FspSiliconInitApiIndex, ApiParam))) {
+          Status = EFI_INVALID_PARAMETER;
+        }
+
         //
         // Reset MultiPhase NumberOfPhases to zero
         //
@@ -89,6 +95,8 @@ FspApiCallingCheck (
     } else {
       if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE) {
         Status = EFI_UNSUPPORTED;
+      } else if (ApiParam == NULL) {
+        Status = EFI_SUCCESS;
       } else if (EFI_ERROR (FspUpdSignatureCheck (FspSmmInitApiIndex, ApiParam))) {
         Status = EFI_INVALID_PARAMETER;
       }
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
index 61030a843b..73821ad22a 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
@@ -21,7 +21,7 @@ extern   ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))
 ; Following functions will be provided in PlatformSecLib
 ;
 extern ASM_PFX(AsmGetFspBaseAddress)
-extern ASM_PFX(AsmGetFspInfoHeader)
+extern ASM_PFX(AsmGetFspInfoHeaderNoStack)
 ;extern ASM_PFX(LoadMicrocode)    ; @todo: needs a weak implementation
 extern ASM_PFX(SecPlatformInit)   ; @todo: needs a weak implementation
 extern ASM_PFX(SecCarInit)
@@ -160,6 +160,47 @@ endstruc
          RET_ESI_EXT   mm7
 %endmacro
 
+%macro CALL_EDI  1
+
+  mov     edi,  %%ReturnAddress
+  jmp     %1
+%%ReturnAddress:
+
+%endmacro
+
+%macro CALL_EBP 1
+  mov     ebp, %%ReturnAddress
+  jmp     %1
+%%ReturnAddress:
+%endmacro
+
+%macro RET_EBP 0
+  jmp     ebp                           ; restore EIP from EBP
+%endmacro
+
+;
+; Load UPD region pointer in ECX
+;
+global ASM_PFX(LoadUpdPointerToECX)
+ASM_PFX(LoadUpdPointerToECX):
+  ;
+  ; esp + 4 is input UPD parameter
+  ; If esp + 4 is NULL the default UPD should be used
+  ; ecx will be the UPD region that should be used
+  ;
+  mov       ecx, dword [esp + 4]
+  cmp       ecx, 0
+  jnz       ParamValid
+
+  ;
+  ; Fall back to default UPD region
+  ;
+  CALL_EDI  ASM_PFX(AsmGetFspInfoHeaderNoStack)
+  mov       ecx, DWORD [eax + 01Ch]      ; Read FsptImageBaseAddress
+  add       ecx, DWORD [eax + 024h]      ; Get Cfg Region base address = FsptImageBaseAddress + CfgRegionOffset
+ParamValid:
+  RET_EBP
+
 ;
 ; @todo: The strong/weak implementation does not work.
 ;        This needs to be reviewed later.
@@ -187,10 +228,9 @@ endstruc
 global ASM_PFX(LoadMicrocodeDefault)
 ASM_PFX(LoadMicrocodeDefault):
    ; Inputs:
-   ;   esp -> LoadMicrocodeParams pointer
+   ;   ecx -> UPD region contains LoadMicrocodeParams pointer
    ; Register Usage:
-   ;   esp  Preserved
-   ;   All others destroyed
+   ;   All are destroyed
    ; Assumptions:
    ;   No memory available, stack is hard-coded and used for return address
    ;   Executed by SBSP and NBSP
@@ -201,12 +241,9 @@ ASM_PFX(LoadMicrocodeDefault):
    ;
    movd   ebp, mm7
 
+   mov    esp, ecx  ; ECX has been assigned to UPD region
    cmp    esp, 0
[Ted]: do we still need to check esp here?
    jz     ParamError
-   mov    eax, dword [esp + 4]    ; Parameter pointer
-   cmp    eax, 0
-   jz     ParamError
-   mov    esp, eax
 
    ; skip loading Microcode if the MicrocodeCodeSize is zero
    ; and report error if size is less than 2k
@@ -444,13 +481,15 @@ Done:
 Exit2:
    jmp   ebp
 
-
+;
+; EstablishStackFsp: EDI should be preserved cross this function
+;
 global ASM_PFX(EstablishStackFsp)
 ASM_PFX(EstablishStackFsp):
   ;
   ; Save parameter pointer in edx
   ;
-  mov       edx, dword [esp + 4]
+  mov       edx, ecx   ; ECX has been assigned to UPD region
 
   ;
   ; Enable FSP STACK
@@ -555,39 +594,37 @@ ASM_PFX(TempRamInitApi):
   SAVE_EAX
   SAVE_EDX
 
-  ;
-  ; Check Parameter
-  ;
-  mov       eax, dword [esp + 4]
-  cmp       eax, 0
-  mov       eax, 80000002h
-  jz        TempRamInitExit
-
   ;
   ; Sec Platform Init
   ;
+  CALL_EBP  ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param
   CALL_MMX  ASM_PFX(SecPlatformInit)
   cmp       eax, 0
   jnz       TempRamInitExit
 
   ; Load microcode
   LOAD_ESP
[Ted]: Do we still need to restore ESP before calling function since we're using ecx to pass parameter?
+  CALL_EBP  ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param
   CALL_MMX  ASM_PFX(LoadMicrocodeDefault)
   SXMMN     xmm6, 3, eax            ;Save microcode return status in ECX-SLOT 3 in xmm6.
   ;@note If return value eax is not 0, microcode did not load, but continue and attempt to boot.
 
   ; Call Sec CAR Init
   LOAD_ESP
[Ted]: Do we still need to restore ESP before calling function since we're using ecx to pass parameter?
+  CALL_EBP  ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param
   CALL_MMX  ASM_PFX(SecCarInit)
   cmp       eax, 0
   jnz       TempRamInitExit
 
   LOAD_ESP
[Ted]: Do we still need to restore ESP before calling function since we're using ecx to pass parameter?
+  CALL_EBP  ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param
+  mov       edi, ecx                     ; Save UPD param to EDI for later code use
   CALL_MMX  ASM_PFX(EstablishStackFsp)
   cmp       eax, 0
   jnz       TempRamInitExit
 
   LXMMN     xmm6, eax, 3  ;Restore microcode status if no CAR init error from ECX-SLOT 3 in xmm6.
+  SXMMN     xmm6, 3, edi  ;Save FSP-T UPD parameter pointer in ECX-SLOT 3 in xmm6.
 
 TempRamInitExit:
   mov       bl, al                  ; save al data in bl
diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
index 7dd89c531a..cdebe90fab 100644
--- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
@@ -21,7 +21,7 @@ extern   ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))
 ; Following functions will be provided in PlatformSecLib
 ;
 extern ASM_PFX(AsmGetFspBaseAddress)
-extern ASM_PFX(AsmGetFspInfoHeader)
+extern ASM_PFX(AsmGetFspInfoHeaderNoStack)
 ;extern ASM_PFX(LoadMicrocode)    ; @todo: needs a weak implementation
 extern ASM_PFX(SecPlatformInit)   ; @todo: needs a weak implementation
 extern ASM_PFX(SecCarInit)
@@ -87,6 +87,14 @@ struc LoadMicrocodeParamsFsp24
     .size:
 endstruc
 
+%macro CALL_RDI  1
+
+  mov     rdi,  %%ReturnAddress
+  jmp     %1
+%%ReturnAddress:
+
+%endmacro
+
 ;
 ; @todo: The strong/weak implementation does not work.
 ;        This needs to be reviewed later.
@@ -116,8 +124,7 @@ ASM_PFX(LoadMicrocodeDefault):
    ; Inputs:
    ;   rcx -> LoadMicrocodeParams pointer
    ; Register Usage:
-   ;   rsp  Preserved
-   ;   All others destroyed
+   ;   All are destroyed
    ; Assumptions:
    ;   No memory available, stack is hard-coded and used for return address
    ;   Executed by SBSP and NBSP
@@ -420,10 +427,6 @@ ASM_PFX(TempRamInitApi):
   ENABLE_SSE
   ENABLE_AVX
   ;
-  ; Save Input Parameter in YMM10
-  ;
-  SAVE_RCX
-  ;
   ; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and YMM6
   ;
   SAVE_REGS
@@ -433,6 +436,22 @@ ASM_PFX(TempRamInitApi):
   ;
   SAVE_BFV  rbp
 
+  ;
+  ; Save Input Parameter in YMM10
+  ;
+  cmp       rcx, 0
+  jnz       ParamValid
+
+  ;
+  ; Fall back to default UPD
+  ;
+  CALL_RDI  ASM_PFX(AsmGetFspInfoHeaderNoStack)
+  xor       rcx, rcx
+  mov       ecx,  DWORD [rax + 01Ch]      ; Read FsptImageBaseAddress
+  add       ecx,  DWORD [rax + 024h]      ; Get Cfg Region base address = FsptImageBaseAddress + CfgRegionOffset
+ParamValid:
+  SAVE_RCX
+
   ;
   ; Save timestamp into YMM6
   ;
@@ -441,13 +460,6 @@ ASM_PFX(TempRamInitApi):
   or        rax, rdx
   SAVE_TS   rax
 
-  ;
-  ; Check Parameter
-  ;
-  cmp       rcx, 0
-  mov       rcx, 08000000000000002h
-  jz        TempRamInitExit
-
   ;
   ; Sec Platform Init
   ;
-- 
2.35.0.windows.1


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^ permalink raw reply related	[flat|nested] 6+ messages in thread

* Re: [edk2-devel] [PATCH v2] IntelFsp2Pkg: FSP should support input UPD as NULL.
  2022-11-03  2:32 ` [edk2-devel] " Kuo, Ted
@ 2022-11-03 17:01   ` Chiu, Chasel
  2022-11-04  1:56     ` Kuo, Ted
  0 siblings, 1 reply; 6+ messages in thread
From: Chiu, Chasel @ 2022-11-03 17:01 UTC (permalink / raw)
  To: Kuo, Ted, devel@edk2.groups.io; +Cc: Desimone, Nathaniel L, Zeng, Star


Hi Ted,

Please see my reply below inline.

Thanks,
Chasel


> -----Original Message-----
> From: Kuo, Ted <ted.kuo@intel.com>
> Sent: Wednesday, November 2, 2022 7:32 PM
> To: devel@edk2.groups.io; Chiu, Chasel <chasel.chiu@intel.com>
> Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Zeng, Star
> <star.zeng@intel.com>
> Subject: RE: [edk2-devel] [PATCH v2] IntelFsp2Pkg: FSP should support
> input UPD as NULL.
> 
> Hi Chasel,
> 
> I have few comments. Please find [Ted] inline.
> 
> Thanks,
> Ted
> 
> -----Original Message-----
> From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Chiu,
> Chasel
> Sent: Wednesday, November 2, 2022 1:46 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desimone@intel.com>; Zeng, Star <star.zeng@intel.com>
> Subject: [edk2-devel] [PATCH v2] IntelFsp2Pkg: FSP should support input
> UPD as NULL.
> 
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4114
> 
> FSP specification supports input UPD as NULL cases which FSP will use built-
> in UPD region instead.
> FSP should not return INVALID_PARAMETER in such cases.
> 
> In FSP-T entry point case, the valid FSP-T UPD region pointer will be passed
> to platform FSP code to consume.
> In FSP-M and FSP-S cases, valid UPD pointer will be decided when updating
> corresponding pointer field in FspGlobalData.
> 
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Star Zeng <star.zeng@intel.com>
> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
> ---
>  IntelFsp2Pkg/FspSecCore/SecFspApiChk.c         | 12 ++++++++++--
>  IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 73
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++------
> ------------
>  IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm  | 40
> ++++++++++++++++++++++++++--------------
>  3 files changed, 91 insertions(+), 34 deletions(-)
> 
> diff --git a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
> b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
> index a44fbf2a50..5f59938518 100644
> --- a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
> +++ b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
> @@ -44,6 +44,8 @@ FspApiCallingCheck (
>      //
>      if (((UINTN)FspData != MAX_ADDRESS) && ((UINTN)FspData !=
> MAX_UINT32)) {
>        Status = EFI_UNSUPPORTED;
> +    } else if (ApiParam == NULL) {
> +      Status = EFI_SUCCESS;
>      } else if (EFI_ERROR (FspUpdSignatureCheck (ApiIdx, ApiParam))) {
>        Status = EFI_INVALID_PARAMETER;
>      }
> @@ -67,9 +69,13 @@ FspApiCallingCheck (
>      } else {
>        if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE) {
>          Status = EFI_UNSUPPORTED;
> -      } else if (EFI_ERROR (FspUpdSignatureCheck (FspSiliconInitApiIndex,
> ApiParam))) {
> -        Status = EFI_INVALID_PARAMETER;
>        } else if (ApiIdx == FspSiliconInitApiIndex) {
> +        if (ApiParam == NULL) {
> +          Status = EFI_SUCCESS;
> +        } else if (EFI_ERROR (FspUpdSignatureCheck (FspSiliconInitApiIndex,
> ApiParam))) {
> +          Status = EFI_INVALID_PARAMETER;
> +        }
> +
>          //
>          // Reset MultiPhase NumberOfPhases to zero
>          //
> @@ -89,6 +95,8 @@ FspApiCallingCheck (
>      } else {
>        if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE) {
>          Status = EFI_UNSUPPORTED;
> +      } else if (ApiParam == NULL) {
> +        Status = EFI_SUCCESS;
>        } else if (EFI_ERROR (FspUpdSignatureCheck (FspSmmInitApiIndex,
> ApiParam))) {
>          Status = EFI_INVALID_PARAMETER;
>        }
> diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
> b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
> index 61030a843b..73821ad22a 100644
> --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
> +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
> @@ -21,7 +21,7 @@ extern   ASM_PFX(PcdGet32
> (PcdFspReservedBufferSize))
>  ; Following functions will be provided in PlatformSecLib  ;  extern
> ASM_PFX(AsmGetFspBaseAddress) -extern
> ASM_PFX(AsmGetFspInfoHeader)
> +extern ASM_PFX(AsmGetFspInfoHeaderNoStack)
>  ;extern ASM_PFX(LoadMicrocode)    ; @todo: needs a weak
> implementation
>  extern ASM_PFX(SecPlatformInit)   ; @todo: needs a weak implementation
>  extern ASM_PFX(SecCarInit)
> @@ -160,6 +160,47 @@ endstruc
>           RET_ESI_EXT   mm7
>  %endmacro
> 
> +%macro CALL_EDI  1
> +
> +  mov     edi,  %%ReturnAddress
> +  jmp     %1
> +%%ReturnAddress:
> +
> +%endmacro
> +
> +%macro CALL_EBP 1
> +  mov     ebp, %%ReturnAddress
> +  jmp     %1
> +%%ReturnAddress:
> +%endmacro
> +
> +%macro RET_EBP 0
> +  jmp     ebp                           ; restore EIP from EBP
> +%endmacro
> +
> +;
> +; Load UPD region pointer in ECX
> +;
> +global ASM_PFX(LoadUpdPointerToECX)
> +ASM_PFX(LoadUpdPointerToECX):
> +  ;
> +  ; esp + 4 is input UPD parameter
> +  ; If esp + 4 is NULL the default UPD should be used
> +  ; ecx will be the UPD region that should be used
> +  ;
> +  mov       ecx, dword [esp + 4]
> +  cmp       ecx, 0
> +  jnz       ParamValid
> +
> +  ;
> +  ; Fall back to default UPD region
> +  ;
> +  CALL_EDI  ASM_PFX(AsmGetFspInfoHeaderNoStack)
> +  mov       ecx, DWORD [eax + 01Ch]      ; Read FsptImageBaseAddress
> +  add       ecx, DWORD [eax + 024h]      ; Get Cfg Region base address =
> FsptImageBaseAddress + CfgRegionOffset
> +ParamValid:
> +  RET_EBP
> +
>  ;
>  ; @todo: The strong/weak implementation does not work.
>  ;        This needs to be reviewed later.
> @@ -187,10 +228,9 @@ endstruc
>  global ASM_PFX(LoadMicrocodeDefault)
>  ASM_PFX(LoadMicrocodeDefault):
>     ; Inputs:
> -   ;   esp -> LoadMicrocodeParams pointer
> +   ;   ecx -> UPD region contains LoadMicrocodeParams pointer
>     ; Register Usage:
> -   ;   esp  Preserved
> -   ;   All others destroyed
> +   ;   All are destroyed
>     ; Assumptions:
>     ;   No memory available, stack is hard-coded and used for return address
>     ;   Executed by SBSP and NBSP
> @@ -201,12 +241,9 @@ ASM_PFX(LoadMicrocodeDefault):
>     ;
>     movd   ebp, mm7
> 
> +   mov    esp, ecx  ; ECX has been assigned to UPD region
>     cmp    esp, 0
> [Ted]: do we still need to check esp here?

Yes, typically ESP now should never be zero, but I keep it there because original code having this check and this check is nice to have in case unexpected things happening (like FSP with wrong header info).




>     jz     ParamError
> -   mov    eax, dword [esp + 4]    ; Parameter pointer
> -   cmp    eax, 0
> -   jz     ParamError
> -   mov    esp, eax
> 
>     ; skip loading Microcode if the MicrocodeCodeSize is zero
>     ; and report error if size is less than 2k @@ -444,13 +481,15 @@ Done:
>  Exit2:
>     jmp   ebp
> 
> -
> +;
> +; EstablishStackFsp: EDI should be preserved cross this function ;
>  global ASM_PFX(EstablishStackFsp)
>  ASM_PFX(EstablishStackFsp):
>    ;
>    ; Save parameter pointer in edx
>    ;
> -  mov       edx, dword [esp + 4]
> +  mov       edx, ecx   ; ECX has been assigned to UPD region
> 
>    ;
>    ; Enable FSP STACK
> @@ -555,39 +594,37 @@ ASM_PFX(TempRamInitApi):
>    SAVE_EAX
>    SAVE_EDX
> 
> -  ;
> -  ; Check Parameter
> -  ;
> -  mov       eax, dword [esp + 4]
> -  cmp       eax, 0
> -  mov       eax, 80000002h
> -  jz        TempRamInitExit
> -
>    ;
>    ; Sec Platform Init
>    ;
> +  CALL_EBP  ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param
>    CALL_MMX  ASM_PFX(SecPlatformInit)
>    cmp       eax, 0
>    jnz       TempRamInitExit
> 
>    ; Load microcode
>    LOAD_ESP
> [Ted]: Do we still need to restore ESP before calling function since we're
> using ecx to pass parameter?

ECX and ESP may be corrupted by any sub-function so here we need to restore both of them.




> +  CALL_EBP  ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param
>    CALL_MMX  ASM_PFX(LoadMicrocodeDefault)
>    SXMMN     xmm6, 3, eax            ;Save microcode return status in ECX-SLOT
> 3 in xmm6.
>    ;@note If return value eax is not 0, microcode did not load, but continue
> and attempt to boot.
> 
>    ; Call Sec CAR Init
>    LOAD_ESP
> [Ted]: Do we still need to restore ESP before calling function since we're

ECX and ESP may be corrupted by any sub-function so here we need to restore both of them.




> using ecx to pass parameter?
> +  CALL_EBP  ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param
>    CALL_MMX  ASM_PFX(SecCarInit)
>    cmp       eax, 0
>    jnz       TempRamInitExit
> 
>    LOAD_ESP
> [Ted]: Do we still need to restore ESP before calling function since we're


ECX and ESP may be corrupted by any sub-function so here we need to restore both of them.




> using ecx to pass parameter?
> +  CALL_EBP  ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param
> +  mov       edi, ecx                     ; Save UPD param to EDI for later code use
>    CALL_MMX  ASM_PFX(EstablishStackFsp)
>    cmp       eax, 0
>    jnz       TempRamInitExit
> 
>    LXMMN     xmm6, eax, 3  ;Restore microcode status if no CAR init error
> from ECX-SLOT 3 in xmm6.
> +  SXMMN     xmm6, 3, edi  ;Save FSP-T UPD parameter pointer in ECX-SLOT
> 3 in xmm6.
> 
>  TempRamInitExit:
>    mov       bl, al                  ; save al data in bl
> diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
> b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
> index 7dd89c531a..cdebe90fab 100644
> --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
> +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
> @@ -21,7 +21,7 @@ extern   ASM_PFX(PcdGet32
> (PcdFspReservedBufferSize))
>  ; Following functions will be provided in PlatformSecLib  ;  extern
> ASM_PFX(AsmGetFspBaseAddress) -extern
> ASM_PFX(AsmGetFspInfoHeader)
> +extern ASM_PFX(AsmGetFspInfoHeaderNoStack)
>  ;extern ASM_PFX(LoadMicrocode)    ; @todo: needs a weak
> implementation
>  extern ASM_PFX(SecPlatformInit)   ; @todo: needs a weak implementation
>  extern ASM_PFX(SecCarInit)
> @@ -87,6 +87,14 @@ struc LoadMicrocodeParamsFsp24
>      .size:
>  endstruc
> 
> +%macro CALL_RDI  1
> +
> +  mov     rdi,  %%ReturnAddress
> +  jmp     %1
> +%%ReturnAddress:
> +
> +%endmacro
> +
>  ;
>  ; @todo: The strong/weak implementation does not work.
>  ;        This needs to be reviewed later.
> @@ -116,8 +124,7 @@ ASM_PFX(LoadMicrocodeDefault):
>     ; Inputs:
>     ;   rcx -> LoadMicrocodeParams pointer
>     ; Register Usage:
> -   ;   rsp  Preserved
> -   ;   All others destroyed
> +   ;   All are destroyed
>     ; Assumptions:
>     ;   No memory available, stack is hard-coded and used for return address
>     ;   Executed by SBSP and NBSP
> @@ -420,10 +427,6 @@ ASM_PFX(TempRamInitApi):
>    ENABLE_SSE
>    ENABLE_AVX
>    ;
> -  ; Save Input Parameter in YMM10
> -  ;
> -  SAVE_RCX
> -  ;
>    ; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and YMM6
>    ;
>    SAVE_REGS
> @@ -433,6 +436,22 @@ ASM_PFX(TempRamInitApi):
>    ;
>    SAVE_BFV  rbp
> 
> +  ;
> +  ; Save Input Parameter in YMM10
> +  ;
> +  cmp       rcx, 0
> +  jnz       ParamValid
> +
> +  ;
> +  ; Fall back to default UPD
> +  ;
> +  CALL_RDI  ASM_PFX(AsmGetFspInfoHeaderNoStack)
> +  xor       rcx, rcx
> +  mov       ecx,  DWORD [rax + 01Ch]      ; Read FsptImageBaseAddress
> +  add       ecx,  DWORD [rax + 024h]      ; Get Cfg Region base address =
> FsptImageBaseAddress + CfgRegionOffset
> +ParamValid:
> +  SAVE_RCX
> +
>    ;
>    ; Save timestamp into YMM6
>    ;
> @@ -441,13 +460,6 @@ ASM_PFX(TempRamInitApi):
>    or        rax, rdx
>    SAVE_TS   rax
> 
> -  ;
> -  ; Check Parameter
> -  ;
> -  cmp       rcx, 0
> -  mov       rcx, 08000000000000002h
> -  jz        TempRamInitExit
> -
>    ;
>    ; Sec Platform Init
>    ;
> --
> 2.35.0.windows.1
> 
> 
> -=-=-=-=-=-=
> Groups.io Links: You receive all messages sent to this group.
> View/Reply Online (#95854):
> https://edk2.groups.io/g/devel/message/95854
> Mute This Topic: https://groups.io/mt/94728678/1862468
> Group Owner: devel+owner@edk2.groups.io
> Unsubscribe: https://edk2.groups.io/g/devel/unsub [ted.kuo@intel.com] -
> =-=-=-=-=-=
> 


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [edk2-devel] [PATCH v2] IntelFsp2Pkg: FSP should support input UPD as NULL.
  2022-11-03 17:01   ` Chiu, Chasel
@ 2022-11-04  1:56     ` Kuo, Ted
  0 siblings, 0 replies; 6+ messages in thread
From: Kuo, Ted @ 2022-11-04  1:56 UTC (permalink / raw)
  To: Chiu, Chasel, devel@edk2.groups.io; +Cc: Desimone, Nathaniel L, Zeng, Star

Reviewed-by: Ted Kuo <ted.kuo@intel.com>

-----Original Message-----
From: Chiu, Chasel <chasel.chiu@intel.com> 
Sent: Friday, November 4, 2022 1:02 AM
To: Kuo, Ted <ted.kuo@intel.com>; devel@edk2.groups.io
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Zeng, Star <star.zeng@intel.com>
Subject: RE: [edk2-devel] [PATCH v2] IntelFsp2Pkg: FSP should support input UPD as NULL.


Hi Ted,

Please see my reply below inline.

Thanks,
Chasel


> -----Original Message-----
> From: Kuo, Ted <ted.kuo@intel.com>
> Sent: Wednesday, November 2, 2022 7:32 PM
> To: devel@edk2.groups.io; Chiu, Chasel <chasel.chiu@intel.com>
> Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Zeng, Star 
> <star.zeng@intel.com>
> Subject: RE: [edk2-devel] [PATCH v2] IntelFsp2Pkg: FSP should support 
> input UPD as NULL.
> 
> Hi Chasel,
> 
> I have few comments. Please find [Ted] inline.
> 
> Thanks,
> Ted
> 
> -----Original Message-----
> From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Chiu, 
> Chasel
> Sent: Wednesday, November 2, 2022 1:46 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Desimone, Nathaniel L 
> <nathaniel.l.desimone@intel.com>; Zeng, Star <star.zeng@intel.com>
> Subject: [edk2-devel] [PATCH v2] IntelFsp2Pkg: FSP should support 
> input UPD as NULL.
> 
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4114
> 
> FSP specification supports input UPD as NULL cases which FSP will use 
> built- in UPD region instead.
> FSP should not return INVALID_PARAMETER in such cases.
> 
> In FSP-T entry point case, the valid FSP-T UPD region pointer will be 
> passed to platform FSP code to consume.
> In FSP-M and FSP-S cases, valid UPD pointer will be decided when 
> updating corresponding pointer field in FspGlobalData.
> 
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Star Zeng <star.zeng@intel.com>
> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
> ---
>  IntelFsp2Pkg/FspSecCore/SecFspApiChk.c         | 12 ++++++++++--
>  IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 73
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++------
> ------------
>  IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm  | 40
> ++++++++++++++++++++++++++--------------
>  3 files changed, 91 insertions(+), 34 deletions(-)
> 
> diff --git a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
> b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
> index a44fbf2a50..5f59938518 100644
> --- a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
> +++ b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
> @@ -44,6 +44,8 @@ FspApiCallingCheck (
>      //
>      if (((UINTN)FspData != MAX_ADDRESS) && ((UINTN)FspData !=
> MAX_UINT32)) {
>        Status = EFI_UNSUPPORTED;
> +    } else if (ApiParam == NULL) {
> +      Status = EFI_SUCCESS;
>      } else if (EFI_ERROR (FspUpdSignatureCheck (ApiIdx, ApiParam))) {
>        Status = EFI_INVALID_PARAMETER;
>      }
> @@ -67,9 +69,13 @@ FspApiCallingCheck (
>      } else {
>        if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE) {
>          Status = EFI_UNSUPPORTED;
> -      } else if (EFI_ERROR (FspUpdSignatureCheck (FspSiliconInitApiIndex,
> ApiParam))) {
> -        Status = EFI_INVALID_PARAMETER;
>        } else if (ApiIdx == FspSiliconInitApiIndex) {
> +        if (ApiParam == NULL) {
> +          Status = EFI_SUCCESS;
> +        } else if (EFI_ERROR (FspUpdSignatureCheck 
> + (FspSiliconInitApiIndex,
> ApiParam))) {
> +          Status = EFI_INVALID_PARAMETER;
> +        }
> +
>          //
>          // Reset MultiPhase NumberOfPhases to zero
>          //
> @@ -89,6 +95,8 @@ FspApiCallingCheck (
>      } else {
>        if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE) {
>          Status = EFI_UNSUPPORTED;
> +      } else if (ApiParam == NULL) {
> +        Status = EFI_SUCCESS;
>        } else if (EFI_ERROR (FspUpdSignatureCheck (FspSmmInitApiIndex,
> ApiParam))) {
>          Status = EFI_INVALID_PARAMETER;
>        }
> diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
> b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
> index 61030a843b..73821ad22a 100644
> --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
> +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
> @@ -21,7 +21,7 @@ extern   ASM_PFX(PcdGet32
> (PcdFspReservedBufferSize))
>  ; Following functions will be provided in PlatformSecLib  ;  extern
> ASM_PFX(AsmGetFspBaseAddress) -extern
> ASM_PFX(AsmGetFspInfoHeader)
> +extern ASM_PFX(AsmGetFspInfoHeaderNoStack)
>  ;extern ASM_PFX(LoadMicrocode)    ; @todo: needs a weak
> implementation
>  extern ASM_PFX(SecPlatformInit)   ; @todo: needs a weak implementation
>  extern ASM_PFX(SecCarInit)
> @@ -160,6 +160,47 @@ endstruc
>           RET_ESI_EXT   mm7
>  %endmacro
> 
> +%macro CALL_EDI  1
> +
> +  mov     edi,  %%ReturnAddress
> +  jmp     %1
> +%%ReturnAddress:
> +
> +%endmacro
> +
> +%macro CALL_EBP 1
> +  mov     ebp, %%ReturnAddress
> +  jmp     %1
> +%%ReturnAddress:
> +%endmacro
> +
> +%macro RET_EBP 0
> +  jmp     ebp                           ; restore EIP from EBP
> +%endmacro
> +
> +;
> +; Load UPD region pointer in ECX
> +;
> +global ASM_PFX(LoadUpdPointerToECX)
> +ASM_PFX(LoadUpdPointerToECX):
> +  ;
> +  ; esp + 4 is input UPD parameter
> +  ; If esp + 4 is NULL the default UPD should be used
> +  ; ecx will be the UPD region that should be used
> +  ;
> +  mov       ecx, dword [esp + 4]
> +  cmp       ecx, 0
> +  jnz       ParamValid
> +
> +  ;
> +  ; Fall back to default UPD region
> +  ;
> +  CALL_EDI  ASM_PFX(AsmGetFspInfoHeaderNoStack)
> +  mov       ecx, DWORD [eax + 01Ch]      ; Read FsptImageBaseAddress
> +  add       ecx, DWORD [eax + 024h]      ; Get Cfg Region base address =
> FsptImageBaseAddress + CfgRegionOffset
> +ParamValid:
> +  RET_EBP
> +
>  ;
>  ; @todo: The strong/weak implementation does not work.
>  ;        This needs to be reviewed later.
> @@ -187,10 +228,9 @@ endstruc
>  global ASM_PFX(LoadMicrocodeDefault)
>  ASM_PFX(LoadMicrocodeDefault):
>     ; Inputs:
> -   ;   esp -> LoadMicrocodeParams pointer
> +   ;   ecx -> UPD region contains LoadMicrocodeParams pointer
>     ; Register Usage:
> -   ;   esp  Preserved
> -   ;   All others destroyed
> +   ;   All are destroyed
>     ; Assumptions:
>     ;   No memory available, stack is hard-coded and used for return address
>     ;   Executed by SBSP and NBSP
> @@ -201,12 +241,9 @@ ASM_PFX(LoadMicrocodeDefault):
>     ;
>     movd   ebp, mm7
> 
> +   mov    esp, ecx  ; ECX has been assigned to UPD region
>     cmp    esp, 0
> [Ted]: do we still need to check esp here?

Yes, typically ESP now should never be zero, but I keep it there because original code having this check and this check is nice to have in case unexpected things happening (like FSP with wrong header info).




>     jz     ParamError
> -   mov    eax, dword [esp + 4]    ; Parameter pointer
> -   cmp    eax, 0
> -   jz     ParamError
> -   mov    esp, eax
> 
>     ; skip loading Microcode if the MicrocodeCodeSize is zero
>     ; and report error if size is less than 2k @@ -444,13 +481,15 @@ Done:
>  Exit2:
>     jmp   ebp
> 
> -
> +;
> +; EstablishStackFsp: EDI should be preserved cross this function ;
>  global ASM_PFX(EstablishStackFsp)
>  ASM_PFX(EstablishStackFsp):
>    ;
>    ; Save parameter pointer in edx
>    ;
> -  mov       edx, dword [esp + 4]
> +  mov       edx, ecx   ; ECX has been assigned to UPD region
> 
>    ;
>    ; Enable FSP STACK
> @@ -555,39 +594,37 @@ ASM_PFX(TempRamInitApi):
>    SAVE_EAX
>    SAVE_EDX
> 
> -  ;
> -  ; Check Parameter
> -  ;
> -  mov       eax, dword [esp + 4]
> -  cmp       eax, 0
> -  mov       eax, 80000002h
> -  jz        TempRamInitExit
> -
>    ;
>    ; Sec Platform Init
>    ;
> +  CALL_EBP  ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param
>    CALL_MMX  ASM_PFX(SecPlatformInit)
>    cmp       eax, 0
>    jnz       TempRamInitExit
> 
>    ; Load microcode
>    LOAD_ESP
> [Ted]: Do we still need to restore ESP before calling function since 
> we're using ecx to pass parameter?

ECX and ESP may be corrupted by any sub-function so here we need to restore both of them.




> +  CALL_EBP  ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param
>    CALL_MMX  ASM_PFX(LoadMicrocodeDefault)
>    SXMMN     xmm6, 3, eax            ;Save microcode return status in ECX-SLOT
> 3 in xmm6.
>    ;@note If return value eax is not 0, microcode did not load, but 
> continue and attempt to boot.
> 
>    ; Call Sec CAR Init
>    LOAD_ESP
> [Ted]: Do we still need to restore ESP before calling function since 
> we're

ECX and ESP may be corrupted by any sub-function so here we need to restore both of them.




> using ecx to pass parameter?
> +  CALL_EBP  ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param
>    CALL_MMX  ASM_PFX(SecCarInit)
>    cmp       eax, 0
>    jnz       TempRamInitExit
> 
>    LOAD_ESP
> [Ted]: Do we still need to restore ESP before calling function since 
> we're


ECX and ESP may be corrupted by any sub-function so here we need to restore both of them.




> using ecx to pass parameter?
> +  CALL_EBP  ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param
> +  mov       edi, ecx                     ; Save UPD param to EDI for later code use
>    CALL_MMX  ASM_PFX(EstablishStackFsp)
>    cmp       eax, 0
>    jnz       TempRamInitExit
> 
>    LXMMN     xmm6, eax, 3  ;Restore microcode status if no CAR init error
> from ECX-SLOT 3 in xmm6.
> +  SXMMN     xmm6, 3, edi  ;Save FSP-T UPD parameter pointer in ECX-SLOT
> 3 in xmm6.
> 
>  TempRamInitExit:
>    mov       bl, al                  ; save al data in bl
> diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
> b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
> index 7dd89c531a..cdebe90fab 100644
> --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
> +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
> @@ -21,7 +21,7 @@ extern   ASM_PFX(PcdGet32
> (PcdFspReservedBufferSize))
>  ; Following functions will be provided in PlatformSecLib  ;  extern
> ASM_PFX(AsmGetFspBaseAddress) -extern
> ASM_PFX(AsmGetFspInfoHeader)
> +extern ASM_PFX(AsmGetFspInfoHeaderNoStack)
>  ;extern ASM_PFX(LoadMicrocode)    ; @todo: needs a weak
> implementation
>  extern ASM_PFX(SecPlatformInit)   ; @todo: needs a weak implementation
>  extern ASM_PFX(SecCarInit)
> @@ -87,6 +87,14 @@ struc LoadMicrocodeParamsFsp24
>      .size:
>  endstruc
> 
> +%macro CALL_RDI  1
> +
> +  mov     rdi,  %%ReturnAddress
> +  jmp     %1
> +%%ReturnAddress:
> +
> +%endmacro
> +
>  ;
>  ; @todo: The strong/weak implementation does not work.
>  ;        This needs to be reviewed later.
> @@ -116,8 +124,7 @@ ASM_PFX(LoadMicrocodeDefault):
>     ; Inputs:
>     ;   rcx -> LoadMicrocodeParams pointer
>     ; Register Usage:
> -   ;   rsp  Preserved
> -   ;   All others destroyed
> +   ;   All are destroyed
>     ; Assumptions:
>     ;   No memory available, stack is hard-coded and used for return address
>     ;   Executed by SBSP and NBSP
> @@ -420,10 +427,6 @@ ASM_PFX(TempRamInitApi):
>    ENABLE_SSE
>    ENABLE_AVX
>    ;
> -  ; Save Input Parameter in YMM10
> -  ;
> -  SAVE_RCX
> -  ;
>    ; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and YMM6
>    ;
>    SAVE_REGS
> @@ -433,6 +436,22 @@ ASM_PFX(TempRamInitApi):
>    ;
>    SAVE_BFV  rbp
> 
> +  ;
> +  ; Save Input Parameter in YMM10
> +  ;
> +  cmp       rcx, 0
> +  jnz       ParamValid
> +
> +  ;
> +  ; Fall back to default UPD
> +  ;
> +  CALL_RDI  ASM_PFX(AsmGetFspInfoHeaderNoStack)
> +  xor       rcx, rcx
> +  mov       ecx,  DWORD [rax + 01Ch]      ; Read FsptImageBaseAddress
> +  add       ecx,  DWORD [rax + 024h]      ; Get Cfg Region base address =
> FsptImageBaseAddress + CfgRegionOffset
> +ParamValid:
> +  SAVE_RCX
> +
>    ;
>    ; Save timestamp into YMM6
>    ;
> @@ -441,13 +460,6 @@ ASM_PFX(TempRamInitApi):
>    or        rax, rdx
>    SAVE_TS   rax
> 
> -  ;
> -  ; Check Parameter
> -  ;
> -  cmp       rcx, 0
> -  mov       rcx, 08000000000000002h
> -  jz        TempRamInitExit
> -
>    ;
>    ; Sec Platform Init
>    ;
> --
> 2.35.0.windows.1
> 
> 
> -=-=-=-=-=-=
> Groups.io Links: You receive all messages sent to this group.
> View/Reply Online (#95854):
> https://edk2.groups.io/g/devel/message/95854
> Mute This Topic: https://groups.io/mt/94728678/1862468
> Group Owner: devel+owner@edk2.groups.io
> Unsubscribe: https://edk2.groups.io/g/devel/unsub [ted.kuo@intel.com] 
> - =-=-=-=-=-=
> 


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [edk2-devel] [PATCH v2] IntelFsp2Pkg: FSP should support input UPD as NULL.
       [not found] <1723AE652BEE57BF.15522@groups.io>
@ 2022-11-04  4:50 ` Chiu, Chasel
  0 siblings, 0 replies; 6+ messages in thread
From: Chiu, Chasel @ 2022-11-04  4:50 UTC (permalink / raw)
  To: devel@edk2.groups.io, Chiu, Chasel; +Cc: Desimone, Nathaniel L, Zeng, Star


Patch merged: https://github.com/tianocore/edk2/commit/b84f32ae5b475ce657ea1c9db29d4e4ec7711948

Thanks,
Chasel


> -----Original Message-----
> From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Chiu,
> Chasel
> Sent: Tuesday, November 1, 2022 10:46 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desimone@intel.com>; Zeng, Star <star.zeng@intel.com>
> Subject: [edk2-devel] [PATCH v2] IntelFsp2Pkg: FSP should support input
> UPD as NULL.
> 
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4114
> 
> FSP specification supports input UPD as NULL cases which FSP will use built-
> in UPD region instead.
> FSP should not return INVALID_PARAMETER in such cases.
> 
> In FSP-T entry point case, the valid FSP-T UPD region pointer will be passed
> to platform FSP code to consume.
> In FSP-M and FSP-S cases, valid UPD pointer will be decided when updating
> corresponding pointer field in FspGlobalData.
> 
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Star Zeng <star.zeng@intel.com>
> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
> ---
>  IntelFsp2Pkg/FspSecCore/SecFspApiChk.c         | 12 ++++++++++--
>  IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 73
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++------
> ------------
>  IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm  | 40
> ++++++++++++++++++++++++++--------------
>  3 files changed, 91 insertions(+), 34 deletions(-)
> 
> diff --git a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
> b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
> index a44fbf2a50..5f59938518 100644
> --- a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
> +++ b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
> @@ -44,6 +44,8 @@ FspApiCallingCheck (
>      //     if (((UINTN)FspData != MAX_ADDRESS) && ((UINTN)FspData !=
> MAX_UINT32)) {       Status = EFI_UNSUPPORTED;+    } else if (ApiParam ==
> NULL) {+      Status = EFI_SUCCESS;     } else if (EFI_ERROR
> (FspUpdSignatureCheck (ApiIdx, ApiParam))) {       Status =
> EFI_INVALID_PARAMETER;     }@@ -67,9 +69,13 @@ FspApiCallingCheck (
>      } else {       if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE)
> {         Status = EFI_UNSUPPORTED;-      } else if (EFI_ERROR
> (FspUpdSignatureCheck (FspSiliconInitApiIndex, ApiParam))) {-        Status =
> EFI_INVALID_PARAMETER;       } else if (ApiIdx == FspSiliconInitApiIndex) {+
> if (ApiParam == NULL) {+          Status = EFI_SUCCESS;+        } else if
> (EFI_ERROR (FspUpdSignatureCheck (FspSiliconInitApiIndex, ApiParam))) {+
> Status = EFI_INVALID_PARAMETER;+        }+         //         // Reset MultiPhase
> NumberOfPhases to zero         //@@ -89,6 +95,8 @@ FspApiCallingCheck (
>      } else {       if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE)
> {         Status = EFI_UNSUPPORTED;+      } else if (ApiParam == NULL) {+
> Status = EFI_SUCCESS;       } else if (EFI_ERROR (FspUpdSignatureCheck
> (FspSmmInitApiIndex, ApiParam))) {         Status =
> EFI_INVALID_PARAMETER;       }diff --git
> a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
> b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
> index 61030a843b..73821ad22a 100644
> --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
> +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
> @@ -21,7 +21,7 @@ extern   ASM_PFX(PcdGet32
> (PcdFspReservedBufferSize))
>  ; Following functions will be provided in PlatformSecLib ; extern
> ASM_PFX(AsmGetFspBaseAddress)-extern
> ASM_PFX(AsmGetFspInfoHeader)+extern
> ASM_PFX(AsmGetFspInfoHeaderNoStack) ;extern
> ASM_PFX(LoadMicrocode)    ; @todo: needs a weak implementation extern
> ASM_PFX(SecPlatformInit)   ; @todo: needs a weak implementation extern
> ASM_PFX(SecCarInit)@@ -160,6 +160,47 @@ endstruc
>           RET_ESI_EXT   mm7 %endmacro +%macro CALL_EDI  1++  mov     edi,
> %%ReturnAddress+  jmp     %1+%%ReturnAddress:++%endmacro++%macro
> CALL_EBP 1+  mov     ebp, %%ReturnAddress+  jmp
> %1+%%ReturnAddress:+%endmacro++%macro RET_EBP 0+  jmp
> ebp                           ; restore EIP from EBP+%endmacro++;+; Load UPD
> region pointer in ECX+;+global
> ASM_PFX(LoadUpdPointerToECX)+ASM_PFX(LoadUpdPointerToECX):+  ;+  ;
> esp + 4 is input UPD parameter+  ; If esp + 4 is NULL the default UPD should
> be used+  ; ecx will be the UPD region that should be used+  ;+  mov       ecx,
> dword [esp + 4]+  cmp       ecx, 0+  jnz       ParamValid++  ;+  ; Fall back to
> default UPD region+  ;+  CALL_EDI
> ASM_PFX(AsmGetFspInfoHeaderNoStack)+  mov       ecx, DWORD [eax +
> 01Ch]      ; Read FsptImageBaseAddress+  add       ecx, DWORD [eax +
> 024h]      ; Get Cfg Region base address = FsptImageBaseAddress +
> CfgRegionOffset+ParamValid:+  RET_EBP+ ; ; @todo: The strong/weak
> implementation does not work. ;        This needs to be reviewed later.@@ -
> 187,10 +228,9 @@ endstruc
>  global ASM_PFX(LoadMicrocodeDefault)
> ASM_PFX(LoadMicrocodeDefault):    ; Inputs:-   ;   esp ->
> LoadMicrocodeParams pointer+   ;   ecx -> UPD region contains
> LoadMicrocodeParams pointer    ; Register Usage:-   ;   esp  Preserved-   ;
> All others destroyed+   ;   All are destroyed    ; Assumptions:    ;   No
> memory available, stack is hard-coded and used for return address    ;
> Executed by SBSP and NBSP@@ -201,12 +241,9 @@
> ASM_PFX(LoadMicrocodeDefault):
>     ;    movd   ebp, mm7 +   mov    esp, ecx  ; ECX has been assigned to UPD
> region    cmp    esp, 0    jz     ParamError-   mov    eax, dword [esp + 4]    ;
> Parameter pointer-   cmp    eax, 0-   jz     ParamError-   mov    esp, eax     ;
> skip loading Microcode if the MicrocodeCodeSize is zero    ; and report error
> if size is less than 2k@@ -444,13 +481,15 @@ Done:
>  Exit2:    jmp   ebp -+;+; EstablishStackFsp: EDI should be preserved cross
> this function+; global ASM_PFX(EstablishStackFsp)
> ASM_PFX(EstablishStackFsp):   ;   ; Save parameter pointer in edx   ;-  mov
> edx, dword [esp + 4]+  mov       edx, ecx   ; ECX has been assigned to UPD
> region    ;   ; Enable FSP STACK@@ -555,39 +594,37 @@
> ASM_PFX(TempRamInitApi):
>    SAVE_EAX   SAVE_EDX -  ;-  ; Check Parameter-  ;-  mov       eax, dword [esp
> + 4]-  cmp       eax, 0-  mov       eax, 80000002h-  jz        TempRamInitExit-
>    ;   ; Sec Platform Init   ;+  CALL_EBP  ASM_PFX(LoadUpdPointerToECX) ;
> ECX for UPD param   CALL_MMX  ASM_PFX(SecPlatformInit)   cmp       eax, 0
> jnz       TempRamInitExit    ; Load microcode   LOAD_ESP+  CALL_EBP
> ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param   CALL_MMX
> ASM_PFX(LoadMicrocodeDefault)   SXMMN     xmm6, 3, eax            ;Save
> microcode return status in ECX-SLOT 3 in xmm6.   ;@note If return value eax
> is not 0, microcode did not load, but continue and attempt to boot.    ; Call
> Sec CAR Init   LOAD_ESP+  CALL_EBP  ASM_PFX(LoadUpdPointerToECX) ;
> ECX for UPD param   CALL_MMX  ASM_PFX(SecCarInit)   cmp       eax, 0   jnz
> TempRamInitExit    LOAD_ESP+  CALL_EBP
> ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param+  mov       edi,
> ecx                     ; Save UPD param to EDI for later code use   CALL_MMX
> ASM_PFX(EstablishStackFsp)   cmp       eax, 0   jnz       TempRamInitExit
> LXMMN     xmm6, eax, 3  ;Restore microcode status if no CAR init error
> from ECX-SLOT 3 in xmm6.+  SXMMN     xmm6, 3, edi  ;Save FSP-T UPD
> parameter pointer in ECX-SLOT 3 in xmm6.  TempRamInitExit:   mov       bl,
> al                  ; save al data in bldiff --git
> a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
> b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
> index 7dd89c531a..cdebe90fab 100644
> --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
> +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
> @@ -21,7 +21,7 @@ extern   ASM_PFX(PcdGet32
> (PcdFspReservedBufferSize))
>  ; Following functions will be provided in PlatformSecLib ; extern
> ASM_PFX(AsmGetFspBaseAddress)-extern
> ASM_PFX(AsmGetFspInfoHeader)+extern
> ASM_PFX(AsmGetFspInfoHeaderNoStack) ;extern
> ASM_PFX(LoadMicrocode)    ; @todo: needs a weak implementation extern
> ASM_PFX(SecPlatformInit)   ; @todo: needs a weak implementation extern
> ASM_PFX(SecCarInit)@@ -87,6 +87,14 @@ struc
> LoadMicrocodeParamsFsp24
>      .size: endstruc +%macro CALL_RDI  1++  mov     rdi,  %%ReturnAddress+
> jmp     %1+%%ReturnAddress:++%endmacro+ ; ; @todo: The strong/weak
> implementation does not work. ;        This needs to be reviewed later.@@ -
> 116,8 +124,7 @@ ASM_PFX(LoadMicrocodeDefault):
>     ; Inputs:    ;   rcx -> LoadMicrocodeParams pointer    ; Register Usage:-   ;
> rsp  Preserved-   ;   All others destroyed+   ;   All are destroyed    ;
> Assumptions:    ;   No memory available, stack is hard-coded and used for
> return address    ;   Executed by SBSP and NBSP@@ -420,10 +427,6 @@
> ASM_PFX(TempRamInitApi):
>    ENABLE_SSE   ENABLE_AVX   ;-  ; Save Input Parameter in YMM10-  ;-
> SAVE_RCX-  ;   ; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and
> YMM6   ;   SAVE_REGS@@ -433,6 +436,22 @@
> ASM_PFX(TempRamInitApi):
>    ;   SAVE_BFV  rbp +  ;+  ; Save Input Parameter in YMM10+  ;+  cmp       rcx,
> 0+  jnz       ParamValid++  ;+  ; Fall back to default UPD+  ;+  CALL_RDI
> ASM_PFX(AsmGetFspInfoHeaderNoStack)+  xor       rcx, rcx+  mov       ecx,
> DWORD [rax + 01Ch]      ; Read FsptImageBaseAddress+  add       ecx,
> DWORD [rax + 024h]      ; Get Cfg Region base address =
> FsptImageBaseAddress + CfgRegionOffset+ParamValid:+  SAVE_RCX+   ;   ;
> Save timestamp into YMM6   ;@@ -441,13 +460,6 @@
> ASM_PFX(TempRamInitApi):
>    or        rax, rdx   SAVE_TS   rax -  ;-  ; Check Parameter-  ;-  cmp       rcx, 0-
> mov       rcx, 08000000000000002h-  jz        TempRamInitExit-   ;   ; Sec
> Platform Init   ;--
> 2.35.0.windows.1
> 
> 
> 
> -=-=-=-=-=-=
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^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2022-11-04  4:50 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-11-02  5:46 [PATCH v2] IntelFsp2Pkg: FSP should support input UPD as NULL Chiu, Chasel
2022-11-03  0:18 ` Nate DeSimone
2022-11-03  2:32 ` [edk2-devel] " Kuo, Ted
2022-11-03 17:01   ` Chiu, Chasel
2022-11-04  1:56     ` Kuo, Ted
     [not found] <1723AE652BEE57BF.15522@groups.io>
2022-11-04  4:50 ` Chiu, Chasel

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