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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Patch pushed: https://github.com/tianocore/edk2/commit/de9e5b7dc721d4ca319c0455cf83577347= e0abef Thanks, Chasel > -----Original Message----- > From: S, Ashraf Ali > Sent: Thursday, December 16, 2021 4:10 PM > To: devel@edk2.groups.io > Cc: S, Ashraf Ali ; Chiu, Chasel ; > Desimone, Nathaniel L ; Zeng, Star > ; Kuo, Ted ; Duggapu, Chinni B > ; Chaganty, Rangasai V > ; Solanki, Digant H > ; V, Sangeetha ; Ni, R= ay > > Subject: [PATCH v8] IntelFsp2WrapperPkg : FSPM/S UPD data address based o= n > Build Type >=20 > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3642 > when the module is not building in IA32 mode which will lead to building = error. > when a module built-in X64 function pointer will be the size of 64bit wid= th which > cannot be fit in 32bit address which will lead to error. to overcome this= issue > introducing the 2 new PCD's for the 64bit modules can consume it. based o= n the > which pcd platform set, use that. >=20 > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Star Zeng > Cc: Kuo Ted > Cc: Duggapu Chinni B > Cc: Rangasai V Chaganty > Cc: Digant H Solanki > Cc: Sangeetha V > Cc: Ray Ni > Signed-off-by: Ashraf Ali S > --- > .../FspmWrapperPeim/FspmWrapperPeim.c | 25 ++++++++++++++++--- > .../FspmWrapperPeim/FspmWrapperPeim.inf | 3 ++- > .../FspsWrapperPeim/FspsWrapperPeim.c | 25 ++++++++++++++++--- > .../FspsWrapperPeim/FspsWrapperPeim.inf | 3 ++- > IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec | 2 ++ > 5 files changed, 50 insertions(+), 8 deletions(-) >=20 > diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c > b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c > index 287e7f9159..49fbb27eca 100644 > --- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c > +++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c > @@ -3,7 +3,7 @@ > register TemporaryRamDonePpi to call TempRamExit API, and register > MemoryDiscoveredPpi > notify to call FspSiliconInit API. >=20 > - Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
> + Copyright (c) 2014 - 2021, Intel Corporation. All rights > + reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > **/ > @@ -38,6 +38,25 @@ >=20 > extern EFI_GUID gFspHobGuid; >=20 > +/** > + Get the FSP M UPD Data address > + > + @return FSP-M UPD Data Address > +**/ > + > +UINTN > +EFIAPI > +GetFspmUpdDataAddress ( > + VOID > + ) > +{ > + if (PcdGet64 (PcdFspmUpdDataAddress64) !=3D 0) { > + return (UINTN) PcdGet64 (PcdFspmUpdDataAddress64); > + } else { > + return (UINTN) PcdGet32 (PcdFspmUpdDataAddress); > + } > +} > + > /** > Call FspMemoryInit API. >=20 > @@ -67,7 +86,7 @@ PeiFspMemoryInit ( > return EFI_DEVICE_ERROR; > } >=20 > - if ((PcdGet32 (PcdFspmUpdDataAddress) =3D=3D 0) && (FspmHeaderPtr- > >CfgRegionSize !=3D 0) && (FspmHeaderPtr->CfgRegionOffset !=3D 0)) { > + if ((GetFspmUpdDataAddress () =3D=3D 0) && (FspmHeaderPtr->CfgRegionSi= ze > + !=3D 0) && (FspmHeaderPtr->CfgRegionOffset !=3D 0)) { > // > // Copy default FSP-M UPD data from Flash > // > @@ -79,7 +98,7 @@ PeiFspMemoryInit ( > // > // External UPD is ready, get the buffer from PCD pointer. > // > - FspmUpdDataPtr =3D (FSPM_UPD_COMMON *)PcdGet32 > (PcdFspmUpdDataAddress); > + FspmUpdDataPtr =3D (FSPM_UPD_COMMON *) GetFspmUpdDataAddress(); > ASSERT (FspmUpdDataPtr !=3D NULL); > } >=20 > diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > index 00166e56a0..5d0e021401 100644 > --- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > +++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > @@ -6,7 +6,7 @@ > # register TemporaryRamDonePpi to call TempRamExit API, and register > MemoryDiscoveredPpi # notify to call FspSiliconInit API. > # > -# Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved. > +# Copyright (c) 2014 - 2021, Intel Corporation. All rights > +reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -60,6 +60,7 @@ > gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CONSUMES > gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress ## CONSUMES > gIntelFsp2WrapperTokenSpaceGuid.PcdFspMeasurementConfig ## > CONSUMES > + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress64 ## > CONSUMES >=20 > [Sources] > FspmWrapperPeim.c > diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c > b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c > index f7459a90b5..ddee9cd029 100644 > --- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c > +++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c > @@ -3,7 +3,7 @@ > register TemporaryRamDonePpi to call TempRamExit API, and register > MemoryDiscoveredPpi > notify to call FspSiliconInit API. >=20 > - Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
> + Copyright (c) 2014 - 2021, Intel Corporation. All rights > + reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > **/ > @@ -181,6 +181,25 @@ FspSiliconInitDoneGetFspHobList ( > } > } >=20 > +/** > + Get the FSP S UPD Data address > + > + @return FSP-S UPD Data Address > +**/ > + > +UINTN > +EFIAPI > +GetFspsUpdDataAddress ( > + VOID > + ) > +{ > + if (PcdGet64 (PcdFspsUpdDataAddress64) !=3D 0) { > + return (UINTN) PcdGet64 (PcdFspsUpdDataAddress64); > + } else { > + return (UINTN) PcdGet32 (PcdFspsUpdDataAddress); > + } > +} > + > /** > This function is for FSP dispatch mode to perform post FSP-S process. >=20 > @@ -283,7 +302,7 @@ PeiMemoryDiscoveredNotify ( > return EFI_DEVICE_ERROR; > } >=20 > - if ((PcdGet32 (PcdFspsUpdDataAddress) =3D=3D 0) && (FspsHeaderPtr- > >CfgRegionSize !=3D 0) && (FspsHeaderPtr->CfgRegionOffset !=3D 0)) { > + if ((GetFspsUpdDataAddress () =3D=3D 0) && (FspsHeaderPtr->CfgRegionSi= ze > + !=3D 0) && (FspsHeaderPtr->CfgRegionOffset !=3D 0)) { > // > // Copy default FSP-S UPD data from Flash > // > @@ -292,7 +311,7 @@ PeiMemoryDiscoveredNotify ( > SourceData =3D (UINTN *)((UINTN)FspsHeaderPtr->ImageBase + > (UINTN)FspsHeaderPtr->CfgRegionOffset); > CopyMem (FspsUpdDataPtr, SourceData, (UINTN)FspsHeaderPtr- > >CfgRegionSize); > } else { > - FspsUpdDataPtr =3D (FSPS_UPD_COMMON *)PcdGet32 > (PcdFspsUpdDataAddress); > + FspsUpdDataPtr =3D (FSPS_UPD_COMMON *) GetFspsUpdDataAddress(); > ASSERT (FspsUpdDataPtr !=3D NULL); > } >=20 > diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > index aeeca58d6d..da0049a654 100644 > --- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > +++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > @@ -6,7 +6,7 @@ > # register TemporaryRamDonePpi to call TempRamExit API, and register > MemoryDiscoveredPpi # notify to call FspSiliconInit API. > # > -# Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved. > +# Copyright (c) 2014 - 2021, Intel Corporation. All rights > +reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -68,6 +68,7 @@ > gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress ## CONSUMES > gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CONSUMES > gIntelFsp2WrapperTokenSpaceGuid.PcdFspMeasurementConfig ## > CONSUMES > + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress64 ## > CONSUMES >=20 > [Guids] > gFspHobGuid ## CONSUMES ## HOB > diff --git a/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec > b/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec > index b8dac1b574..a5a8b8a19e 100644 > --- a/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec > +++ b/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec > @@ -121,3 +121,5 @@ > # >=20 > gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x00000000|UIN > T32|0x50000000 >=20 > gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0x00000000|UINT > 32|0x50000001 > + > + > gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress64|0x00000000|U > IN > + T64|0x50000002 > + > + > gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress64|0x00000000|UI > N > + T64|0x50000003 > -- > 2.30.2.windows.1