Re: [edk2-platforms] [PATCH V2 2/4] WhiskeylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

["Chiu, Chasel" <chasel.chiu@intel.com>]

Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>

Thanks,
Chasel


> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Tuesday, June 7, 2022 7:17 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael
> <michael.kubacki@microsoft.com>
> Subject: [edk2-platforms] [PATCH V2 2/4] WhiskeylakeOpenBoardPkg: Indicate
> width of CLK duty cycle in FADT
> 
> Set the location of the DUTY_CYCLE field in the P_CNT register and indicate the
> width of the clock duty cycle to OS power management
> 
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Michael Kubacki <michael.kubacki@microsoft.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
>  .../WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc | 9 ++++++++-
>  .../WhiskeylakeURvp/OpenBoardPkgPcd.dsc                  | 9 ++++++++-
>  2 files changed, 16 insertions(+), 2 deletions(-)
> 
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc
> index 84d4ec1331..8f3cc6ba28 100644
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.ds
> +++ c
> @@ -1,7 +1,7 @@
>  ## @file
>  #  PCD configuration build description file for the UpXtreme board.
>  #
> -# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2020 - 2022, Intel Corporation. All rights
> +reserved.<BR>
>  #
>  # SPDX-License-Identifier: BSD-2-Clause-Patent  # @@ -259,6 +259,13 @@
>    gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber|2
> 
> gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpa
> ceGuid.PcdPciExpressRegionLength
> 
> +  #
> +  # Set the location of the DUTY_CYCLE field in the P_CNT register  #
> + and indicate the width of the clock duty cycle to OS power management
> + #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
> +
>    ######################################
>    # Platform Configuration
>    ######################################
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg
> Pcd.dsc
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg
> Pcd.dsc
> index 4a7ba4d5f0..4a5d5ef03b 100644
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg
> Pcd.dsc
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPk
> +++ gPcd.dsc
> @@ -1,7 +1,7 @@
>  ## @file
>  #  PCD configuration build description file for the WhiskeylakeURvp board.
>  #
> -# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2019 - 2022, Intel Corporation. All rights
> +reserved.<BR>
>  #
>  # SPDX-License-Identifier: BSD-2-Clause-Patent  # @@ -242,6 +242,13 @@
>    ######################################
> 
> gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpa
> ceGuid.PcdPciExpressRegionLength
> 
> +  #
> +  # Set the location of the DUTY_CYCLE field in the P_CNT register  #
> + and indicate the width of the clock duty cycle to OS power management
> + #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
> +
>    ######################################
>    # Platform Configuration
>    ######################################
> --
> 2.27.0.windows.1