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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Chasel Chiu Thanks, Chasel > -----Original Message----- > From: Desimone, Nathaniel L > Sent: Tuesday, June 7, 2022 7:17 AM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Kubacki, Michael > > Subject: [edk2-platforms] [PATCH V2 2/4] WhiskeylakeOpenBoardPkg: Indicat= e > width of CLK duty cycle in FADT >=20 > Set the location of the DUTY_CYCLE field in the P_CNT register and indica= te the > width of the clock duty cycle to OS power management >=20 > Cc: Chasel Chiu > Cc: Michael Kubacki > Signed-off-by: Nate DeSimone > --- > .../WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc | 9 ++++++++- > .../WhiskeylakeURvp/OpenBoardPkgPcd.dsc | 9 ++++++++- > 2 files changed, 16 insertions(+), 2 deletions(-) >=20 > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc > b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc > index 84d4ec1331..8f3cc6ba28 100644 > --- > a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.ds > +++ c > @@ -1,7 +1,7 @@ > ## @file > # PCD configuration build description file for the UpXtreme board. > # > -# Copyright (c) 2020, Intel Corporation. All rights reserved.
> +# Copyright (c) 2020 - 2022, Intel Corporation. All rights > +reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -259,6 +259,13 @@ > gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber|2 >=20 > gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpa > ceGuid.PcdPciExpressRegionLength >=20 > + # > + # Set the location of the DUTY_CYCLE field in the P_CNT register # > + and indicate the width of the clock duty cycle to OS power management > + # > + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1 > + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3 > + > ###################################### > # Platform Configuration > ###################################### > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg > Pcd.dsc > b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg > Pcd.dsc > index 4a7ba4d5f0..4a5d5ef03b 100644 > --- > a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg > Pcd.dsc > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPk > +++ gPcd.dsc > @@ -1,7 +1,7 @@ > ## @file > # PCD configuration build description file for the WhiskeylakeURvp boar= d. > # > -# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
> +# Copyright (c) 2019 - 2022, Intel Corporation. All rights > +reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -242,6 +242,13 @@ > ###################################### >=20 > gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpa > ceGuid.PcdPciExpressRegionLength >=20 > + # > + # Set the location of the DUTY_CYCLE field in the P_CNT register # > + and indicate the width of the clock duty cycle to OS power management > + # > + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1 > + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3 > + > ###################################### > # Platform Configuration > ###################################### > -- > 2.27.0.windows.1