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List-Unsubscribe: X-Gm-Message-State: 63VrtgLaH3xzqGqOANGcWoitx7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=Cat06e1q; arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}"); dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Hi Wei, Could you please split the patch to into separate patches? Different patch for different issue may looks clearer. Thanks, Dun -----Original Message----- From: Sheng, W =20 Sent: Friday, November 3, 2023 1:35 PM To: devel@edk2.groups.io Cc: Dong, Eric ; Ni, Ray ; Laszlo Er= sek ; Wu, Jiaxin ; Tan, Dun Subject: [PATCH] UefiCpuPkg/PiSmmCpuDxeSmm: Clear CR4.CET before restoring = MSR IA32_S_CET Clear CR4.CET bit before restoring MSR IA32_S_CET. Backup/restore MSR IA32_U_CET in SMI. Use current CR4 value when changing CR4.CET. Initial mSmmInterruptSspTables to 0. Signed-off-by: Sheng Wei Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Cc: Wu Jiaxin Cc: Tan Dun --- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 62 +++++++++++++---- UefiC= puPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 72 ++++++++++++++++---- UefiCpuP= kg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c | 2 +- 3 files changed, 107 insertions(+), 29 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSm= mCpuDxeSmm/Ia32/SmiEntry.nasm index 19de5f614e..a087576a54 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm @@ -16,18 +16,19 @@ %include "StuffRsbNasm.inc" %include "Nasm.inc" +%define MSR_IA32_U_CET = 0x6A0 %define MSR_IA32_S_CET 0x6A2-%d= efine MSR_IA32_CET_SH_STK_EN 0x1-%define MSR_IA32_CET_WR_SH= STK_EN 0x2-%define MSR_IA32_CET_ENDBR_EN 0x4-%defi= ne MSR_IA32_CET_LEG_IW_EN 0x8-%define MSR_IA32_CET_NO_TRACK= _EN 0x10-%define MSR_IA32_CET_SUPPRESS_DIS 0x20-%defin= e MSR_IA32_CET_SUPPRESS 0x400-%define MSR_IA32_CET_TRACKER= 0x800+%define MSR_IA32_CET_SH_STK_EN 0x1+%define= MSR_IA32_CET_WR_SHSTK_EN 0x2+%define MSR_IA32_CET_ENDBR_EN = 0x4+%define MSR_IA32_CET_LEG_IW_EN 0x8+%define MSR_IA32= _CET_NO_TRACK_EN 0x10+%define MSR_IA32_CET_SUPPRESS_DIS = 0x20+%define MSR_IA32_CET_SUPPRESS 0x400+%define MSR_IA32_CET_= TRACKER 0x800 %define MSR_IA32_PL0_SSP 0x6A= 4 -%define CR4_CET 0x800000+%define CR4_CET_BIT = 23 %define MSR_IA32_MISC_ENABLE 0x1A0 %define MSR_E= FER 0xc0000080@@ -214,11 +215,21 @@ ASM_PFX(mPatchCetSupported): push edx push eax + mov ecx, MSR_IA32_U_CET+ rdmsr= + push edx+ push eax+ mov ecx, MSR_IA32_PL0_SSP rdm= sr push edx push eax + mov ecx, MSR_IA32_U_CET+ xor= eax, eax+ xor edx, edx+ wrmsr+ mov ecx, MSR_IA32_S_C= ET mov eax, MSR_IA32_CET_SH_STK_EN xor edx, edx@@ -249,7 +2= 60,8 @@ CetInterruptDone: bts ecx, 16 ; set WP mov cr0, ecx - = mov eax, 0x668 | CR4_CET+ mov eax, cr4+ bts eax, CR4_CET= _BIT mov cr4, eax setssbsy@@ -276,18 +288,30 @@ CetDone: cmp al, 0 jz CetDone2 - mov eax, 0x668- mov = cr4, eax ; disable CET+ mov ecx, MSR_IA32_S_CET+ xor e= ax, eax+ xor edx, edx+ wrmsr++ ; clear CR4.CET bit+ mov = eax, cr4+ btr eax, CR4_CET_BIT+ mov cr4, eax mov ec= x, MSR_IA32_PL0_SSP pop eax pop edx wrmsr - mov = ecx, MSR_IA32_S_CET+ mov ecx, MSR_IA32_U_CET pop eax pop= edx wrmsr++ mov ecx, MSR_IA32_S_CET+ pop eax+ pop= edx+ mov ebx, eax CetDone2: mov eax, ASM_PFX(mXdSuppor= ted)@@ -305,6 +329,18 @@ CetDone2: .7: StuffRsb32++ mov eax, ASM_PFX(mCetSupported)+ mov a= l, [eax]+ cmp al, 0+ jz CetDone3++ mov ecx, MSR_IA32_= S_CET+ mov eax, ebx+ xor edx, edx+ wrmsr+CetDone3:+ rs= m ASM_PFX(gcSmiHandlerSize): DW $ - _SmiEntryPointdiff --git a/UefiCpuPkg/= PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.n= asm index d302ca8d01..7aed7c8dda 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm @@ -20,19 +20,20 @@ ; Variables referenced by C code ; +%define MSR_IA32_U_CET = 0x6A0 %define MSR_IA32_S_CET 0x6A2-%define MSR_I= A32_CET_SH_STK_EN 0x1-%define MSR_IA32_CET_WR_SHSTK_EN = 0x2-%define MSR_IA32_CET_ENDBR_EN 0x4-%define MSR_IA32= _CET_LEG_IW_EN 0x8-%define MSR_IA32_CET_NO_TRACK_EN = 0x10-%define MSR_IA32_CET_SUPPRESS_DIS 0x20-%define MSR_IA32_= CET_SUPPRESS 0x400-%define MSR_IA32_CET_TRACKER = 0x800+%define MSR_IA32_CET_SH_STK_EN 0x1+%define MSR_IA32_CET= _WR_SHSTK_EN 0x2+%define MSR_IA32_CET_ENDBR_EN 0x4+%= define MSR_IA32_CET_LEG_IW_EN 0x8+%define MSR_IA32_CET_NO_TRACK= _EN 0x10+%define MSR_IA32_CET_SUPPRESS_DIS 0x20+%define = MSR_IA32_CET_SUPPRESS 0x400+%define MSR_IA32_CET_TRACKER = 0x800 %define MSR_IA32_PL0_SSP 0x6A4 %define MSR= _IA32_INTERRUPT_SSP_TABLE_ADDR 0x6A8 -%define CR4_CET = 0x800000+%define CR4_CET_BIT 23 %define MSR_= IA32_MISC_ENABLE 0x1A0 %define MSR_EFER 0xc0000080@@ -230,6 +231,11 @@= ASM_PFX(mPatchCetSupported): push rdx push rax + mov ecx, MSR_IA32_U_CET+ rdmsr= + push rdx+ push rax+ mov ecx, MSR_IA32_PL0_SSP rdm= sr push rdx@@ -240,6 +246,11 @@ ASM_PFX(mPatchCetSupported): push rdx push rax + mov ecx, MSR_IA32_U_CET+ xor = eax, eax+ xor edx, edx+ wrmsr+ mov ecx, MSR_IA32_S_CET= mov eax, MSR_IA32_CET_SH_STK_EN xor edx, edx@@ -276,7 +287= ,8 @@ CetInterruptDone: bts ecx, 16 ; set WP mov cr0, rcx - = mov eax, 0x668 | CR4_CET+ mov rax, cr4+ bts rax, CR4_CET= _BIT mov cr4, rax setssbsy@@ -316,13 +328,20 @@ CpuSmmDebugExi= tAbsAddr: add rsp, 0x200 mov rax, strict qword 0 ; mov = rax, ASM_PFX(mCetSupported)-mCetSupportedAbsAddr:+mCetSupportedAbsAddr1: = mov al, [rax] cmp al, 0 jz CetDone2 - mov e= ax, 0x668- mov cr4, rax ; disable CET+ mov ecx, MSR_IA3= 2_S_CET+ xor eax, eax+ xor edx, edx+ wrmsr++ ; clear CR= 4.CET bit+ mov rax, cr4+ btr rax, CR4_CET_BIT+ mov cr4= , rax mov ecx, MSR_IA32_INTERRUPT_SSP_TABLE_ADDR pop rax@@= -334,10 +353,15 @@ mCetSupportedAbsAddr: pop rdx wrmsr - mov ecx, MSR_IA32_S_CET+ mov ecx= , MSR_IA32_U_CET pop rax pop rdx wrmsr++ mov ecx= , MSR_IA32_S_CET+ pop rax+ pop rdx+ mov ebx, eax CetDo= ne2: mov rax, strict qword 0 ; lea rax, [ASM_PFX= (mXdSupported)]@@ -356,6 +380,19 @@ mXdSupportedAbsAddr: .1: StuffRsb64++ mov rax, strict qword 0 ; mov r= ax, ASM_PFX(mCetSupported)+mCetSupportedAbsAddr2:+ mov al, [rax]+ = cmp al, 0+ jz CetDone3++ mov ecx, MSR_IA32_S_CET+ mo= v eax, ebx+ xor edx, edx+ wrmsr+CetDone3:+ rsm ASM_PFX(g= cSmiHandlerSize) DW $ - _SmiEntryPoint@@ -391,6 +428,11 @@ ASM_PFX(= PiSmmCpuSmiEntryFixupAddress): mov qword [rcx - 8], rax lea rax, [ASM_PFX(mCetSupported)]-= lea rcx, [mCetSupportedAbsAddr]+ lea rcx, [mCetSupportedAbsAdd= r1] mov qword [rcx - 8], rax++ lea rax, [ASM_PFX(mCetSupported= )]+ lea rcx, [mCetSupportedAbsAddr2]+ mov qword [rcx - 8], rax+= retdiff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c b/UefiCpu= Pkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c index c4f21e2155..6c53213b0b 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c @@ -20,7 +20,7 @@ UINT32 mCetPl0Ssp; UINT32 mCetInterruptSsp; UINT32 mCet= InterruptSspTable; -UINTN mSmmInterruptSspTables;+UINTN mSmmInterruptSspT= ables =3D 0; /** Initialize IDT IST Field.--=20 2.26.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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