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X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BN9PR11MB5483.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: b51177c0-1de2-4b8b-46a5-08dc130b3770 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Jan 2024 01:10:07.4848 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: QGKNV6z9U8k7leoH4W8X5sIMD7BVX1po62fMWdBqpahSA6RrdhdnEFThmpK883rS0CdyHq83vtfNRbCiIqn3gg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR11MB7307 X-OriginatorOrg: intel.com Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: FdyAbH7spWfnLsYWssCEq10yx7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=L4Bg6WWX; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}") Hi Gerd, I explain the reason why 47 here is since virtual addresses are sign-extend= ed in the commit message. About the technical background, I also mentioned in the commit message " Wh= en 5-Level Paging is disabled and the PhysicalAddressBits retrived from CP= U HOB or CpuId is bigger than 47". Could you please provide more detailed s= uggestion about the commit message? Or can we merge the code firstly? Then I'll raise another PR to make the co= mments around the code more detailed as we want. Thanks, Dun -----Original Message----- From: Gerd Hoffmann =20 Sent: Thursday, January 11, 2024 6:21 PM To: Tan, Dun Cc: devel@edk2.groups.io; Ni, Ray ; Laszlo Ersek ; Kumar, Rahul R Subject: Re: [Patch V3] UefiCpuPkg:Limit PhysicalAddressBits in special cas= e On Thu, Jan 11, 2024 at 04:59:47PM +0800, Dun Tan wrote: > When creating smm page table, limit maximum supported physical address=20 > bits returned by > CalculateMaximumSupportAddress() to 47 if 5-Level Paging is disabled. > When 5-Level Paging is disabled and the PhysicalAddressBits retrived=20 > from CPU HOB or CpuId is bigger than 47, and since virtual addresses=20 > are sign-extended, only [0, 2^47-1] range in 52-bit physical address=20 > is mapped in page table. > + // > + // Only [0, 2^47 -1] in 52-bit physical addresses is mapped in page=20 > + table // when 5-Level Paging is disabled. > + // > + ASSERT (PhysicalAddressBits <=3D 52); if (!Is5LevelPagingNeeded &&=20 > + (PhysicalAddressBits > 47)) { > + PhysicalAddressBits =3D 47; > + } The code change is fine but the comment should be more verbose and explain = the why 47 not 48 is used here. The discussion on the patch clearly showed= that the technical background is not obvious ... take care, Gerd -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113636): https://edk2.groups.io/g/devel/message/113636 Mute This Topic: https://groups.io/mt/103658816/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-