From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mx.groups.io with SMTP id smtpd.web12.5665.1624844098026264521 for ; Sun, 27 Jun 2021 18:34:58 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@intel.onmicrosoft.com header.s=selector2-intel-onmicrosoft-com header.b=jLuL1VMS; spf=pass (domain: intel.com, ip: 192.55.52.136, mailfrom: chasel.chiu@intel.com) X-IronPort-AV: E=McAfee;i="6200,9189,10028"; a="187560683" X-IronPort-AV: E=Sophos;i="5.83,304,1616482800"; d="scan'208";a="187560683" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2021 18:34:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.83,304,1616482800"; d="scan'208";a="456119924" Received: from orsmsx606.amr.corp.intel.com ([10.22.229.19]) by fmsmga008.fm.intel.com with ESMTP; 27 Jun 2021 18:34:57 -0700 Received: from orsmsx610.amr.corp.intel.com (10.22.229.23) by ORSMSX606.amr.corp.intel.com (10.22.229.19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.4; Sun, 27 Jun 2021 18:34:56 -0700 Received: from orsmsx602.amr.corp.intel.com (10.22.229.15) by ORSMSX610.amr.corp.intel.com (10.22.229.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.4; Sun, 27 Jun 2021 18:34:56 -0700 Received: from ORSEDG602.ED.cps.intel.com (10.7.248.7) by orsmsx602.amr.corp.intel.com (10.22.229.15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.4 via Frontend Transport; Sun, 27 Jun 2021 18:34:56 -0700 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (104.47.57.177) by edgegateway.intel.com (134.134.137.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2242.4; Sun, 27 Jun 2021 18:34:56 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=WuWfGU7tX+eYFHzJhMz0LTaOhdrXM28nBAjtC7XmtNXFWG+W6S8SzYkK6Z0V6QHvmMLAo2RAR8nJfygHrkx4wvSWYr9TPw910s8KwDKNku7AYvLHI5J2SejeL/zyuWNkVCaoM4hsWVtH1LKMRuIYL6QU6o7jsVxT9F0uz715e9Ml1yeTMZi8k1fTkR4Pw7JM2hiOViuCgltYLZDCqHMxAljS6gZzfOTvE+ZT2Fkm2sVhWQAXgCjmh+DzcgUQmW4DBkDT0rmZVggJTDFWi6sIgk/KqKyajiWD9WzZVHyloV7jBPOGuiZL12JlFRTDRO7lxqYKU+MYf7Oa5w/FK6r+fQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=auIomfl77KYsMUkTcAL9RnPizL+edLmsg5bIHRRO2wc=; b=AtugU25NYCntninaML8Do25ZZAiAJlOxLWXw8hNNsGF/X4p0E3Qy3iVyHgD+AZElVvi9/qoGTHLSj2/DSlAN0iSW7mxQH/O5ERU0Wx4FHxUBs1NAV/JqwK+wu+kb7LTqn36pew6EOIzVTueDkMLEraEAec7pIXMlo4D+JpfTay8u8pZmjdST6WJgcMLhSMMlx6m2G7SyJhNs2EjgmpwxO0FTR02+T+3PQqh7In19WJFZ7II9NfgstkSdM3aXUFErgthZU2qHS/qtLuhpCzTxR+fyrRUtacvGpHQTeMNmEhJYH2WvDE1boUpMqT7fiYNgiPi7iFIQb2aLtFBZzijBiA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=intel.onmicrosoft.com; s=selector2-intel-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=auIomfl77KYsMUkTcAL9RnPizL+edLmsg5bIHRRO2wc=; b=jLuL1VMSCNQjaZShU+h6dV8j7a2gm4iJUnT3dGiuhLD8VELHgccsHHgpZqvY/8+2HqobYns66O1h7Osyt3+9p5eQ/npnvenPHNzLizEapzzl43jpTG18Avqf2lELNLVWS3ZYDHxlg2nCY4t3Ef1Y46NkNnrOvvELc9FccbZ9qN4= Received: from BN9PR11MB5483.namprd11.prod.outlook.com (2603:10b6:408:104::10) by BN7PR11MB2612.namprd11.prod.outlook.com (2603:10b6:406:b4::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4264.20; Mon, 28 Jun 2021 01:34:55 +0000 Received: from BN9PR11MB5483.namprd11.prod.outlook.com ([fe80::2162:be61:a479:4168]) by BN9PR11MB5483.namprd11.prod.outlook.com ([fe80::2162:be61:a479:4168%7]) with mapi id 15.20.4264.026; Mon, 28 Jun 2021 01:34:55 +0000 From: "Chiu, Chasel" To: "mikuback@linux.microsoft.com" , "devel@edk2.groups.io" CC: "Desimone, Nathaniel L" , "Chaganty, Rangasai V" , "Kethi Reddy, Deepika" , "Esakkithevar, Kathappan" Subject: Re: [edk2-platforms][PATCH v4 11/41] CometlakeOpenBoardPkg: Use IntelSiliconPkg BIOS area and ucode PCDs Thread-Topic: [edk2-platforms][PATCH v4 11/41] CometlakeOpenBoardPkg: Use IntelSiliconPkg BIOS area and ucode PCDs Thread-Index: AQHXaghKHOrSxbBhmUCz+OYD2zfroasop3RA Date: Mon, 28 Jun 2021 01:34:54 +0000 Message-ID: References: <20210625212120.235-1-mikuback@linux.microsoft.com> <20210625212120.235-12-mikuback@linux.microsoft.com> In-Reply-To: <20210625212120.235-12-mikuback@linux.microsoft.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.5.1.3 authentication-results: linux.microsoft.com; dkim=none (message not signed) header.d=none;linux.microsoft.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [114.43.34.211] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 83799732-44de-4eae-0127-08d939d4eeb4 x-ms-traffictypediagnostic: BN7PR11MB2612: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:2887; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: DGE9DERI8sFcutrGry5qw77Mmj0Iy7rKicZuqzChYPN2Ojf6I5cq53XyyluTeBEhcHMcN1TeTM/0kRU6gVt/coIxQSx8odUdvgj9I+rbIG71yFKFZqb6jrqRk8Rj2K4aiVnmP5XqfRrmq63pR9I5Nm/VNkN+wWUmxoZUIKDkvyxWvqBCNJtHCtmiKtsFMRmZ16PLiNjkpnjmS3qado3l0nWlQeqg8/j00aUa2pXcKKhnoUXAOc4wFCLHSsowVaeA8QGwIO0pHquqq9FWa05FhvYLqslpwMR4V23LI9n4vDteF+lhEsFqw3yxwcQ7nDAiNfHonwsRmWvl/YZp2aNeq+zCwUw6+7b26RU3RQNiKGiDy0vHYPOYsPWMl93hE5Te0wIqe4Ga6V/mElOQCaS+bi6i4qAsY3ZccmPfPMlrlX1Zim77PZB6G9i2eZCRd/x0zNtF9jicDRhpOtv/sMvhLlsDGl1nlQc6Ih6Md9v2cJa2xei0BMiw2tmG805mPjWzEWEhjhShCOTZx5SqedRBEwm7Y23Tg/Ws5fLBR2neyH1sLsTRxBNuFG3jNzKoOmCQ/LYGnG6kFnzOTlZNO0Mfax1upgzOv2lNcSu53D6FLud8thN58vbMvQAYKKoEoHn+4eL6j21i7pq9r1lXa/OvokDF0HiD9NHI2YwWCzGT0rBo+P6ktUovB/HLPgIBDyzw9flFPFSOlP7HAQE8KaVBE76EJnf5wEfSPtIOvYmOTpIblOCKwS4VpJYNIWtryk7P5OikZQBnqa1GzyXyeWspzgPbsOMvHoaymZpWzkwe5tuxShuWjnbsfElao6VdShv+ x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:BN9PR11MB5483.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFS:(396003)(366004)(136003)(376002)(346002)(39860400002)(38100700002)(26005)(8676002)(5660300002)(54906003)(2906002)(110136005)(83380400001)(86362001)(107886003)(6506007)(122000001)(19627235002)(478600001)(53546011)(33656002)(52536014)(66556008)(55016002)(76116006)(186003)(7696005)(66946007)(9686003)(30864003)(66446008)(316002)(64756008)(8936002)(4326008)(66476007)(71200400001)(11716005);DIR:OUT;SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?f/FNtZI/81SMCK3rvRvcGV40UEy5iLr/VdLNvJlWMr3d9bzmNawJJURv6lep?= =?us-ascii?Q?3qXiJV9V8cCvEv//EyRqgrqeMPFXQb2dWGBFrOynsc614CscgX2wuJ9vI/OO?= =?us-ascii?Q?zO+wfGhQVCStFOpdF+xBLU/sBpHYCYXkHlvbaxHYKO4qE8wr8uLchJ/pIUtC?= =?us-ascii?Q?pwoBMJORxWOBdU2n7NF5rm2absTE4deFZk4PTmCpmcJqmeS1PZO8ou3lRSoL?= =?us-ascii?Q?VgtTdGjZdKiVyXhGEPO991/CmBw5FtwyuHStJTuR98HrJaZiVFScnwPHIov3?= =?us-ascii?Q?Ogw4UjPGP92mFdYgDPCLE9uErdDQvA0HwBy5XUkAiU6DDVfUfLAL6z+sNzqJ?= =?us-ascii?Q?ieWCVjWlx/OhaNorfVj+kBgyKg9/Yrv3lC9Wk2ozzdHAXHVvaPfGEU093WSI?= =?us-ascii?Q?Bjk+rhnPpClqqC/yN9d6VtKFj29UVWSgJ9+lnugQ8b2qYbcj72+B0OISXQwG?= =?us-ascii?Q?ZCA5cMeyLMk9RUSwshwt6W+PHACvLAHzyLCzmXvuuzGSSOhTWpt+wn9yrRYe?= =?us-ascii?Q?gaND8BJIC2PQDIa1r3sSjSXuot22t35ZYXm4TwRbsCyLDaq8+tsB1l3AvqLF?= =?us-ascii?Q?Cc7JIQXfvbhvsgcff7RDC9+ptzK3Jlu0y7uIzIur9JV5IJ4zzUuc/RsTQRcw?= =?us-ascii?Q?jFWTyH0LgB5dAjSvBTt3/SfnosDJf9S9txHEQE6w0Nlrg6D4D2ywfBiLeKzr?= =?us-ascii?Q?zyHBQwnbwZ/cANib4lPP1Zvzo8MfOW2ut0cfP5p3IR6N6+71owtZL3ggswlD?= =?us-ascii?Q?coswRzsCYBNN767hv1vrEluZa8f0o1eef+JEVOR3PxYy3C6xEez0A3KW02Bo?= =?us-ascii?Q?mKBHlepeWYtsDCPDxhI3r62prSWLo0pjyjpb04NpX4zIUYNpipHTLIXz7TAv?= =?us-ascii?Q?naGxVb9O2q0vmcgzMGfSPdqEZTLGd2puZerwSdif1+uPZpA+t4NzgkWltNBF?= =?us-ascii?Q?hr28ONGKClQflqtTBUiik4YepVZYDJBb8NKBSk6/YLd/1Yn19YUGTiQUKbkB?= =?us-ascii?Q?92E+PLZWQ+GaEtDgOpuCYK+5lkjdeisaa2Ib4zU9wuyVXAUOovCvaakYeAud?= =?us-ascii?Q?zZN//6HKif6csXzbKsVVMHifiqKksm8r4nN5AscHp56Sga8oKKf07abQpGz5?= =?us-ascii?Q?xyapDuyTet8tTELpDHz8eV5YWpDwdjq2sb8Y8gPFUfjzb9UE1SjNId8/NKc/?= =?us-ascii?Q?rKM4Ph3Cnn4ZoY9n2fUMWBxrxeoRvvEZ0dUJI65aXDNsVbWNX5u6Jy7BhrqL?= =?us-ascii?Q?Vhc+uCMg9KIyzisidjg/SX8VH/OrO+mJtnW/1vO4xwHsm+xRdcYA9Pap63y2?= =?us-ascii?Q?mcXgYYw1ZUcE/F/6gyh6qNdA?= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BN9PR11MB5483.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 83799732-44de-4eae-0127-08d939d4eeb4 X-MS-Exchange-CrossTenant-originalarrivaltime: 28 Jun 2021 01:34:54.8676 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: MA9eEWqJMt3ZZEa6o4XZ5w5glIottO2Utsg9eYmZeXkb4Nh4ak5vT7IpD0Mf+sxjzW7ptYBc6k4zIz43t/567Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PR11MB2612 Return-Path: chasel.chiu@intel.com X-OriginatorOrg: intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Chasel Chiu > -----Original Message----- > From: mikuback@linux.microsoft.com > Sent: Saturday, June 26, 2021 5:21 AM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Desimone, Nathaniel L > ; Chaganty, Rangasai V > ; Kethi Reddy, Deepika > ; Esakkithevar, Kathappan > > Subject: [edk2-platforms][PATCH v4 11/41] CometlakeOpenBoardPkg: Use > IntelSiliconPkg BIOS area and ucode PCDs >=20 > From: Michael Kubacki >=20 > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3307 >=20 > Updates PCDs to use the IntelSiliconPkg PCD tokenspace now that the PCDs = are > declared in IntelSiliconPkg.dec. >=20 > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Rangasai V Chaganty > Cc: Deepika Kethi Reddy > Cc: Kathappan Esakkithevar > Signed-off-by: Michael Kubacki > Reviewed-by: Nate DeSimone > --- > Platform/Intel/CometlakeOpenBoardPkg/BiosInfo/BiosInfo.inf = | 4 > +-- >=20 > Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Fdf/FlashMa > pInclude.fdf | 4 +-- > Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fdf > | 36 ++++++++++---------- > Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.= inf > | 4 +-- > 4 files changed, 24 insertions(+), 24 deletions(-) >=20 > diff --git a/Platform/Intel/CometlakeOpenBoardPkg/BiosInfo/BiosInfo.inf > b/Platform/Intel/CometlakeOpenBoardPkg/BiosInfo/BiosInfo.inf > index 9208aeda5d2a..6ca0ada751f6 100644 > --- a/Platform/Intel/CometlakeOpenBoardPkg/BiosInfo/BiosInfo.inf > +++ b/Platform/Intel/CometlakeOpenBoardPkg/BiosInfo/BiosInfo.inf > @@ -36,8 +36,8 @@ [Packages] > MinPlatformPkg/MinPlatformPkg.dec >=20 > [Pcd] > - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## CON= SUMES > - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CON= SUMES > + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## > CONSUMES > + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## > CONSUMES >=20 > [Sources] > BiosInfo.c > diff --git > a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Fdf/Flash > MapInclude.fdf > b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Fdf/Flash > MapInclude.fdf > index d9959a79d0bb..7d2f4b2c0cb2 100644 > --- > a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Fdf/Flash > MapInclude.fdf > +++ > b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Fdf/Fla > +++ shMapInclude.fdf > @@ -34,8 +34,8 @@ > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize =3D > 0x00190000 # > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =3D > 0x00320000 # Flash addr (0xFFB20000) > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =3D > 0x00170000 # > -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D = 0x00490000 > # Flash addr (0xFFC90000) > -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D = 0x000B0000 > # > +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D > 0x00490000 # Flash addr (0xFFC90000) > +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D > 0x000B0000 # > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =3D > 0x00540000 # Flash addr (0xFFD40000) > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize =3D > 0x00070000 # > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D > 0x005B0000 # Flash addr (0xFFDB0000) > diff --git > a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fdf > b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fdf > index 795cc0da75d8..6397d80d3895 100644 > --- > a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fdf > +++ > b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fd > +++ f > @@ -31,8 +31,8 @@ [FD.CometlakeURvp] > # assigned with PCD values. Instead, it uses the definitions for its var= iety, which > # are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS. > # > -BaseAddress =3D $(FLASH_BASE) | > gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress #The base address of the > FLASH Device. > -Size =3D $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdBiosSize = #The size > in bytes of the FLASH Device > +BaseAddress =3D $(FLASH_BASE) | > gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress #The base address = of > the FLASH Device. > +Size =3D $(FLASH_SIZE) | gIntelSiliconPkgTokenSpaceGuid.PcdBios= Size > #The size in bytes of the FLASH Device > ErasePolarity =3D 1 > BlockSize =3D $(FLASH_BLOCK_SIZE) > NumBlocks =3D $(FLASH_NUM_BLOCKS) > @@ -43,21 +43,21 @@ [FD.CometlakeURvp] > # Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, > because macro expression is not supported. > # So, PlatformSecLib uses PcdBiosAreaBaseAddress + PcdNemCodeCacheBase > to get the real CodeCache base address. > SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase =3D > $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset) > -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D > $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset) > -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) > -SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 -SET > gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 > +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D > +$(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + > +$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset) > +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D > +$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) > +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D > +$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 SET > +gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D > +$(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 > SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv =3D 0x60 > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset > -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D > gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress > -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D > gSiPkgTokenSpaceGuid.PcdBiosSize > -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D > $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + > $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset) > -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D > $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + > $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset) > -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D > $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + > $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset) > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D > gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D > gSiPkgTokenSpaceGuid.PcdBiosSize > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D > gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D > gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D > +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D > gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D > gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D > $(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + > $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset) > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D > $(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + > $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset) > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D > $(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + > $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D > gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D > gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize >=20 > ################################################################# > ############### > # > # Following are lists of FD Region layout which correspond to the locati= ons of > different @@ -153,8 +153,8 @@ [FD.CometlakeURvp] > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPk > gTokenSpaceGuid.PcdFlashFvPostMemorySize > FV =3D FvPostMemory >=20 > - > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.Pcd > FlashMicrocodeFvSize > - > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFl > ashMicrocodeFvSize > +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gIntelSiliconP > +kgTokenSpaceGuid.PcdFlashMicrocodeFvSize > +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gIntelSiliconPkg > +TokenSpaceGuid.PcdFlashMicrocodeFvSize > #Microcode > FV =3D FvMicrocode >=20 > diff --git > a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe= .in > f > b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe= .in > f > index 1d09b990b163..abb79c111e0b 100644 > --- > a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe= .in > f > +++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyIn > +++ itDxe.inf > @@ -47,8 +47,8 @@ [Packages] >=20 > [Pcd] > gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress = ## > CONSUMES > - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = ## > CONSUMES > - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = ## CONSUMES > + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = ## > CONSUMES > + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = ## > CONSUMES > gCometlakeOpenBoardPkgTokenSpaceGuid.PcdIntelGopEnable > gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPlatformFlavor > gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPlatformType > -- > 2.28.0.windows.1