* Re: [edk2-devel] [PATCH v3] IntelFsp2Pkg: Fix NASM X64 build warnings.
[not found] <174E957ABDBD6AF4.22739@groups.io>
@ 2023-03-24 23:52 ` Chiu, Chasel
0 siblings, 0 replies; only message in thread
From: Chiu, Chasel @ 2023-03-24 23:52 UTC (permalink / raw)
To: devel@edk2.groups.io, Chiu, Chasel; +Cc: Desimone, Nathaniel L, Zeng, Star
Patch merged:
https://github.com/tianocore/edk2/commit/f6bd3286edfbe5eb6b50946cc8bb89e5c60b9388
Thanks,
Chasel
> -----Original Message-----
> From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Chiu, Chasel
> Sent: Tuesday, March 21, 2023 5:14 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desimone@intel.com>; Zeng, Star <star.zeng@intel.com>
> Subject: [edk2-devel] [PATCH v3] IntelFsp2Pkg: Fix NASM X64 build warnings.
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4377
>
> Fix below warnings generated by NASM X64 build:
> /X64/FspHelper.iii:26: warning: signed dword value exceeds bounds
> /X64/FspHelper.iii:35: warning: signed dword value exceeds bounds
> /X64/FspApiEntryT.iii:320: warning: dword data exceeds bounds
>
> Also replaced "cmp reg, 0" with "test reg, reg" per optimization suggestion.
>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Star Zeng <star.zeng@intel.com>
> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
> ---
> IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 18 +++++++++---------
> IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm | 2 --
> 2 files changed, 9 insertions(+), 11 deletions(-)
>
> diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
> b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
> index cdebe90fab..b32fa32a89 100644
> --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
> +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
> @@ -135,9 +135,9 @@ ASM_PFX(LoadMicrocodeDefault):
> ; LOAD_RBP - cmp rsp, 0+ test rsp, rsp jz ParamError- cmp rcx, 0+
> test rcx, rcx jz ParamError mov rsp, rcx @@ -151,13 +151,13 @@
> ASM_PFX(LoadMicrocodeDefault):
> ; UPD structure is compliant with FSP spec 2.4 mov rax, qword [rsp +
> LoadMicrocodeParamsFsp24.MicrocodeCodeSize]- cmp rax, 0+ test rax,
> rax jz Exit2 cmp rax, 0800h jl ParamError mov rsi, qword [rsp +
> LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]- cmp rsi, 0+ test rsi, rsi
> jnz CheckMainHeader ParamError:@@ -315,9 +315,9 @@ Done:
> mov ecx, MSR_IA32_BIOS_SIGN_ID rdmsr ; Get current
> microcode signature xor eax, eax- cmp edx, 0+ test edx, edx jnz Exit2-
> mov eax, 0800000000000000Eh+ mov rax, 0800000000000000Eh Exit2:
> jmp rbp@@ -464,7 +464,7 @@ ParamValid:
> ; Sec Platform Init ; CALL_YMM ASM_PFX(SecPlatformInit)- cmp eax, 0+
> test rax, rax jnz TempRamInitExit ; Load microcode@@ -476,12
> +476,12 @@ ParamValid:
> ; Call Sec CAR Init LOAD_RCX CALL_YMM ASM_PFX(SecCarInit)- cmp rax,
> 0+ test rax, rax jnz TempRamInitExit LOAD_RCX CALL_YMM
> ASM_PFX(EstablishStackFsp)- cmp rax, 0+ test rax, rax jnz
> TempRamInitExit LOAD_UCODE_STATUS rax ; Restore microcode status
> if no CAR init error from SLOT 0 in YMM9 (upper 128bits).diff --git
> a/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm
> b/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm
> index 71624a3aad..32a60270b8 100644
> --- a/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm
> +++ b/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm
> @@ -23,7 +23,6 @@ ASM_PFX(AsmGetFspInfoHeader):
> global ASM_PFX(FspInfoHeaderRelativeOff)
> ASM_PFX(FspInfoHeaderRelativeOff): DD 0x12345678 ; This value
> must be patched by the build script- and rax, 0xffffffff ret global
> ASM_PFX(AsmGetFspInfoHeaderNoStack)@@ -32,5 +31,4 @@
> ASM_PFX(AsmGetFspInfoHeaderNoStack):
> lea rcx, [ASM_PFX(FspInfoHeaderRelativeOff)] mov ecx, [rcx] sub rax,
> rcx- and rax, 0xffffffff jmp rdi--
> 2.35.0.windows.1
>
>
>
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