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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Chasel Chiu > -----Original Message----- > From: Desimone, Nathaniel L > Sent: Tuesday, August 17, 2021 5:54 AM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Chaganty, Rangasai V > ; Benjamin Doron > ; Michael Kubacki > > Subject: [edk2-platforms] [PATCH V2] KabylakeSiliconPkg: Default for > PeciC10Reset should be 1 >=20 > The default value for CpuConfigLibPreMemConfig->PeciC10Reset > should be 1 so that Peci Reset on C10 exit is disabled. >=20 > Other bug fixes in > KabylakeSiliconPkg\Cpu\Library\PeiCpuPolicyLibPreMem\PeiCpuPolicyLib.c >=20 > 1. PCI configuration space can only be read 32-bits at a time. > Converted MmioRead64 to MmioRead32. > 2. Added a RShiftU64() call to prevent compiler instrinsics from > being inserted. Since this is a 64-bit integer shift done in > IA-32 mode it is possible for intrinsic calls to be added. >=20 > Cc: Chasel Chiu > Cc: Sai Chaganty > Cc: Benjamin Doron > Cc: Michael Kubacki > Signed-off-by: Nate DeSimone > --- > .../PeiCpuPolicyLibPreMem/PeiCpuPolicyLib.c | 30 +++++++++++++++---- > 1 file changed, 25 insertions(+), 5 deletions(-) >=20 > diff --git > a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPreMem/Pei > CpuPolicyLib.c > b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPreMem/Pei > CpuPolicyLib.c > index 35041322a7..9a334d8ec2 100644 > --- > a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPreMem/Pei > CpuPolicyLib.c > +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPreMem > +++ /PeiCpuPolicyLib.c > @@ -1,7 +1,7 @@ > /** @file > This file is PeiCpuPolicy library. >=20 > -Copyright (c) 2017, Intel Corporation. All rights reserved.
> +Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > **/ > @@ -45,13 +45,31 @@ LoadCpuConfigLibPreMemConfigDefault ( > CpuConfigLibPreMemConfig->BootFrequency =3D 1; // Maximum= non- > turbo Performance > CpuConfigLibPreMemConfig->ActiveCoreCount =3D 0; // All cor= es active > CpuConfigLibPreMemConfig->VmxEnable =3D CPU_FEATURE_ENAB= LE; > - CpuConfigLibPreMemConfig->CpuRatio =3D ((AsmReadMsr64 > (MSR_PLATFORM_INFO) >> N_PLATFORM_INFO_MAX_RATIO) & > B_PLATFORM_INFO_RATIO_MASK); > + CpuConfigLibPreMemConfig->CpuRatio =3D RShiftU64 (AsmReadMsr64 > + (MSR_PLATFORM_INFO), N_PLATFORM_INFO_MAX_RATIO) & > + B_PLATFORM_INFO_RATIO_MASK; > + > /// > /// FCLK Frequency > /// > - CpuFamily =3D GetCpuFamily(); > - CpuSku =3D GetCpuSku(); > - MchBar =3D MmioRead64 (MmPciBase (SA_MC_BUS, SA_MC_DEV, > SA_MC_FUN) + R_SA_MCHBAR) &~BIT0; > + CpuFamily =3D GetCpuFamily (); > + CpuSku =3D GetCpuSku (); > + > + DEBUG_CODE_BEGIN (); > + /// > + /// Ensure the upper 7-bits [38:32] of MCHBAR are zero so we can acces= s > MCHBAR in 32-bit mode. > + /// > + MchBar =3D MmioRead32 (MmPciBase (SA_MC_BUS, SA_MC_DEV, > SA_MC_FUN) + > + R_SA_MCHBAR + 0x4) & 0x7F; if (MchBar !=3D 0x0) { > + DEBUG (( > + DEBUG_ERROR, > + "Error: [%a]:[%dL] MCHBAR configured to >4GB\n", > + __FUNCTION__, > + __LINE__ > + )); > + } > + ASSERT (MchBar =3D=3D 0x0); > + DEBUG_CODE_END (); > + > + MchBar =3D MmioRead32 (MmPciBase (SA_MC_BUS, SA_MC_DEV, > SA_MC_FUN) + > + R_SA_MCHBAR) &~BIT0; > if (IsPchLinkDmi (CpuFamily) && (MmioRead16 (MmPciBase > (SA_PEG_BUS_NUM, SA_PEG_DEV_NUM, SA_PEG10_FUN_NUM) + > PCI_VENDOR_ID_OFFSET) !=3D 0xFFFF)) { > PegDisabled =3D MmioRead32 ((UINTN) MchBar + > R_SA_MCHBAR_BIOS_RESET_CPL_OFFSET) & BIT3; > } else { > @@ -67,6 +85,8 @@ LoadCpuConfigLibPreMemConfigDefault ( > } else { > CpuConfigLibPreMemConfig->FClkFrequency =3D 0; // 800MHz > } > + > + CpuConfigLibPreMemConfig->PeciC10Reset =3D 1; // Disables Peci Reset > + on C10 exit > } >=20 > /** > -- > 2.27.0.windows.1