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From: "Chiu, Chasel" <chasel.chiu@intel.com>
To: "devel@edk2.groups.io" <devel@edk2.groups.io>,
	"Chiu, Chasel" <chasel.chiu@intel.com>
Cc: "Ma, Maurice" <maurice.ma@intel.com>,
	"Desimone, Nathaniel L" <nathaniel.l.desimone@intel.com>,
	"Zeng, Star" <star.zeng@intel.com>
Subject: Re: [edk2-devel] [PATCH] IntelFsp2Pkg/SplitFspBin.py: adopt FSP 2.3 specification.
Date: Wed, 27 Oct 2021 11:55:37 +0000	[thread overview]
Message-ID: <BN9PR11MB5483E3C9141F62B8F566DD67E6859@BN9PR11MB5483.namprd11.prod.outlook.com> (raw)
In-Reply-To: <16B18613046C3205.3758@groups.io>


Patch pushed:
https://github.com/tianocore/edk2/commit/9a95d11023ac2f2ee49a2958cf80658270442c42

Thanks,
Chasel


> -----Original Message-----
> From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Chiu, Chasel
> Sent: Tuesday, October 26, 2021 4:06 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Ma, Maurice
> <maurice.ma@intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desimone@intel.com>; Zeng, Star <star.zeng@intel.com>
> Subject: [edk2-devel] [PATCH] IntelFsp2Pkg/SplitFspBin.py: adopt FSP 2.3
> specification.
> 
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3705
> 
> FSP 2.3 has updated FSP_INFO_HEADER to support ExtendedImageRevision and
> SplitFspBin.py needs to support it.
> 
> Also updated script to display integer value basing on length.
> 
> Cc: Maurice Ma <maurice.ma@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Star Zeng <star.zeng@intel.com>
> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
> ---
>  IntelFsp2Pkg/Tools/SplitFspBin.py | 66
> ++++++++++++++++++++++++++++++++++++++++++++----------------------
>  1 file changed, 44 insertions(+), 22 deletions(-)
> 
> diff --git a/IntelFsp2Pkg/Tools/SplitFspBin.py
> b/IntelFsp2Pkg/Tools/SplitFspBin.py
> index 24272e82af..20e329a76e 100644
> --- a/IntelFsp2Pkg/Tools/SplitFspBin.py
> +++ b/IntelFsp2Pkg/Tools/SplitFspBin.py
> @@ -1,6 +1,6 @@
>  ## @ FspTool.py #-# Copyright (c) 2015 - 2020, Intel Corporation. All rights
> reserved.<BR>+# Copyright (c) 2015 - 2021, Intel Corporation. All rights
> reserved.<BR> # SPDX-License-Identifier: BSD-2-Clause-Patent # ##@@ -103,26
> +103,29 @@ class FSP_COMMON_HEADER(Structure):
>   class FSP_INFORMATION_HEADER(Structure):      _fields_ = [-        ('Signature',
> ARRAY(c_char, 4)),-        ('HeaderLength',         c_uint32),-        ('Reserved1',
> c_uint16),-        ('SpecVersion',          c_uint8),-        ('HeaderRevision',
> c_uint8),-        ('ImageRevision',        c_uint32),-        ('ImageId',
> ARRAY(c_char, 8)),-        ('ImageSize',            c_uint32),-        ('ImageBase',
> c_uint32),-        ('ImageAttribute',       c_uint16),-        ('ComponentAttribute',
> c_uint16),-        ('CfgRegionOffset',      c_uint32),-        ('CfgRegionSize',
> c_uint32),-        ('Reserved2',            c_uint32),-        ('TempRamInitEntryOffset',
> c_uint32),-        ('Reserved3',                  c_uint32),-        ('NotifyPhaseEntryOffset',
> c_uint32),-        ('FspMemoryInitEntryOffset',   c_uint32),-
> ('TempRamExitEntryOffset',     c_uint32),-        ('FspSiliconInitEntryOffset',
> c_uint32)+        ('Signature',                      ARRAY(c_char, 4)),+        ('HeaderLength',
> c_uint32),+        ('Reserved1',                      c_uint16),+        ('SpecVersion',
> c_uint8),+        ('HeaderRevision',                 c_uint8),+        ('ImageRevision',
> c_uint32),+        ('ImageId',                        ARRAY(c_char, 8)),+        ('ImageSize',
> c_uint32),+        ('ImageBase',                      c_uint32),+        ('ImageAttribute',
> c_uint16),+        ('ComponentAttribute',             c_uint16),+        ('CfgRegionOffset',
> c_uint32),+        ('CfgRegionSize',                  c_uint32),+        ('Reserved2',
> c_uint32),+        ('TempRamInitEntryOffset',         c_uint32),+        ('Reserved3',
> c_uint32),+        ('NotifyPhaseEntryOffset',         c_uint32),+
> ('FspMemoryInitEntryOffset',       c_uint32),+        ('TempRamExitEntryOffset',
> c_uint32),+        ('FspSiliconInitEntryOffset',      c_uint32),+
> ('FspMultiPhaseSiInitEntryOffset', c_uint32),+        ('ExtendedImageRevision',
> c_uint16),+        ('Reserved4',                      c_uint16)     ]  class
> FSP_PATCH_TABLE(Structure):@@ -390,7 +393,26 @@ def OutputStruct (obj,
> indent = 0, plen = 0):
>              if IsStrType (val):                 rep = HandleNameStr (val)             elif
> IsIntegerType (val):-                rep = '0x%X' % val+                if (key ==
> 'ImageRevision'):+                    FspImageRevisionMajor       = ((val >> 24) & 0xFF)+
> FspImageRevisionMinor       = ((val >> 16) & 0xFF)+
> FspImageRevisionRevision    = ((val >> 8) & 0xFF)+
> FspImageRevisionBuildNumber = (val & 0xFF)+                    rep = '0x%08X' % val+
> elif (key == 'ExtendedImageRevision'):+                    FspImageRevisionRevision
> |= (val & 0xFF00)+                    FspImageRevisionBuildNumber |= ((val << 8) &
> 0xFF00)+                    rep = "0x%04X ('%02X.%02X.%04X.%04X')" % (val,
> FspImageRevisionMajor, FspImageRevisionMinor, FspImageRevisionRevision,
> FspImageRevisionBuildNumber)+                elif field[1] == c_uint64:+
> rep = '0x%016X' % val+                elif field[1] == c_uint32:+                    rep =
> '0x%08X' % val+                elif field[1] == c_uint16:+                    rep = '0x%04X' %
> val+                elif field[1] == c_uint8:+                    rep = '0x%02X' % val+
> else:+                    rep = '0x%X' % val             elif isinstance(val, c_uint24):
> rep = '0x%X' % val.get_value()             elif 'c_ubyte_Array' in str(type(val)):--
> 2.28.0.windows.1
> 
> 
> 
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> 


           reply	other threads:[~2021-10-27 11:55 UTC|newest]

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