From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mx.groups.io with SMTP id smtpd.web11.12382.1600937776414377060 for ; Thu, 24 Sep 2020 01:56:16 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@intel.onmicrosoft.com header.s=selector2-intel-onmicrosoft-com header.b=ep7LMHh+; spf=pass (domain: intel.com, ip: 192.55.52.88, mailfrom: ray.ni@intel.com) IronPort-SDR: j/yOrV2XBOXWLSNbiSxkAFDJB5KHQhtGJF1IhjPOCbfeVKQN2kEV2iBG8ymuFoGL8QmLwN7IS1 kjXLgqlbWvww== X-IronPort-AV: E=McAfee;i="6000,8403,9753"; a="179223621" X-IronPort-AV: E=Sophos;i="5.77,296,1596524400"; d="scan'208";a="179223621" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Sep 2020 01:56:15 -0700 IronPort-SDR: kbLDKd/0QAV9+aTA5NwHaXNYtBV4s+NoIm2/lBbWuUSAHD1oZ/Y0QrkqClt3XFOyt814A3h5um mZQ3sAURV23Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,296,1596524400"; d="scan'208";a="512054854" Received: from fmsmsx604.amr.corp.intel.com ([10.18.126.84]) by fmsmga005.fm.intel.com with ESMTP; 24 Sep 2020 01:56:15 -0700 Received: from fmsmsx609.amr.corp.intel.com (10.18.126.89) by fmsmsx604.amr.corp.intel.com (10.18.126.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Thu, 24 Sep 2020 01:56:14 -0700 Received: from fmsmsx601.amr.corp.intel.com (10.18.126.81) by fmsmsx609.amr.corp.intel.com (10.18.126.89) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Thu, 24 Sep 2020 01:56:14 -0700 Received: from fmsedg601.ED.cps.intel.com (10.1.192.135) by fmsmsx601.amr.corp.intel.com (10.18.126.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5 via Frontend Transport; Thu, 24 Sep 2020 01:56:14 -0700 Received: from NAM02-SN1-obe.outbound.protection.outlook.com (104.47.36.50) by edgegateway.intel.com (192.55.55.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.1713.5; Thu, 24 Sep 2020 01:56:12 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=hjr+RF+l3gbUKY8EWfyBankSq+5hX0u7V1QaVvq+mPga44wQr+RQF4K8nOh312kbZdd1qaMkJDOwUXpI3T8JTP5zDT9g6LjkJJptludKMEvR7FQ0cqtpfTCAsQotX5Jq8oKvzsKZyP2xzHuYNezTs/nMDkXgQYI4g4tRdQWex3DS5Z/hbqWFP2unJWmbP/zlPr++Hu6BUpP+8ZbbUinTQ3hWCczpIDqf5YBcmUR3vuV36uBFUmLZPZ9ROZgWRRfLLdQJ/ple3W8vk25gwPtFgpFCfSa81k4jzKVPDTuFsm+IfPn2JKXVGuskplWbD5NPyoW5uCl9PBDPf9clDDXAgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=yX4iDV+fw7rhFyrsKitxJAoyS7m1uVkzngPAEncofAs=; b=SQrZ0V0Xp9L6NI57S4yK0zgt+6ZD1RuK2xgc/A26v/W/ud3UnHGJ3uTEfh5Y4aIGTaeYWk0dRyx3WGpgHC/9G2hBj/S7KaHjS+n1VdjcYCAucXmp6twESTT/9dCbnCLBtUJHcQEe1U4S4Pl2aA86DrcRwCztdXBZR9CJblFRsN8OZSnHLYxs+dfhRwvYbSEJtATm5+2xoo5EUxJ1fAWzD0vNQ2PLpkkdgZD9vR2AVfeKMU2X+/hE2Z/mZHeUiDkJ8NDmWc9R7T6CN5Jtn96nIBEqJJZFxfLBIyCeUG3M+f9OHWd6//OhrVsHdVubuCWOaClmulOHeIUYsMuVVfyivQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=intel.onmicrosoft.com; s=selector2-intel-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=yX4iDV+fw7rhFyrsKitxJAoyS7m1uVkzngPAEncofAs=; b=ep7LMHh+eOu6GilrdPyf30uHYbSr8nerpD3hSz6oawlZDOIT8kmDUnmbOM567Wq+FZ3N5hs0OKuxuSuYsuPfwQos9eZBh1GtOWrBtGpxBxqJ+vzfkd6XTpdQjC5rxELY77pURD1Kh5vj5k3vbB/SnbWsfkimfXo730lqz/Q9Tv4= Received: from BY5PR11MB4007.namprd11.prod.outlook.com (2603:10b6:a03:189::28) by BY5PR11MB3896.namprd11.prod.outlook.com (2603:10b6:a03:187::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3391.14; Thu, 24 Sep 2020 08:56:11 +0000 Received: from BY5PR11MB4007.namprd11.prod.outlook.com ([fe80::1533:4053:1c45:3596]) by BY5PR11MB4007.namprd11.prod.outlook.com ([fe80::1533:4053:1c45:3596%6]) with mapi id 15.20.3370.033; Thu, 24 Sep 2020 08:56:11 +0000 From: "Ni, Ray" To: "Li, Aaron" , "devel@edk2.groups.io" CC: "Chaganty, Rangasai V" , "Fu, Siyuan" Subject: Re: [PATCH v1 1/1] IntelSiliconPkg/ShadowMicrocodePei: Add PCD for shadowing all microcode. Thread-Topic: [PATCH v1 1/1] IntelSiliconPkg/ShadowMicrocodePei: Add PCD for shadowing all microcode. Thread-Index: AQHWcH3xyuJZ6EUoG028rAn2IG6CzKl2AuzAgAFBYQCAAGSP4A== Date: Thu, 24 Sep 2020 08:56:11 +0000 Message-ID: References: <20200812075452.9054-1-aaron.li@intel.com> In-Reply-To: Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [192.198.147.194] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 122b2811-ab44-4d4e-c912-08d86067afb0 x-ms-traffictypediagnostic: BY5PR11MB3896: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:5797; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: u/tGe1NOtS3Nv4bC3Aa5khm3aSM7THsnZ5lXTRDxU67Jh5GiL8a9C5jCZSreIptkGca1VK3IvT3CBhWcKCvj9sMrwyD8TUtVcN+J4FvH1ugSXPhS4buli37V5a9udl7onEfR6h9x//8ymfPPbvmi90IbxIMLC13moMAmEkydME/5ObSKgUOpxCTd/23F6yUQJLY4TiTpRszRyjsuwu4pwzSekoIieMZQJcaNNXEQxO0cvLAePTKoimk7CLnBbWhhWCaeSGVhdFc1xb0fXA4MDiDZKo5BUydrQJLT66KR+sZ0RO9Nw231H2Xh5x53ABFZ49J+SmFsNiY0Hod2ASUFyO0nv3wVV02j9IxPzzzUEN2cvdKuRvn8TQlgPs+uDzLp8BPFO2K1k0Id6fm5LI9sKCZG+zoNNNmT5BkKbbuoTnGVkyIDRg7vB4iG1vhlV81/Q/S9vnyUg7q/fmp/TGJnvr1NF27Z6UzK1rqrYTaqCpbfw8J7G+o2z2AFj0FhFPbg x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:BY5PR11MB4007.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFS:(4636009)(396003)(136003)(39860400002)(346002)(376002)(366004)(2906002)(71200400001)(5660300002)(186003)(83380400001)(4326008)(86362001)(33656002)(966005)(8936002)(26005)(107886003)(7696005)(66446008)(76116006)(64756008)(54906003)(66556008)(110136005)(8676002)(9686003)(53546011)(55016002)(316002)(66476007)(66946007)(52536014)(6506007)(478600001)(14943795004);DIR:OUT;SFP:1102; x-ms-exchange-antispam-messagedata: rXx2urccOMIPTicmyot+3NLbqhA37DfVakQBNzfVzSc0e7j3TObHEED6Jk2u9t07vREGqPMcji1DLQus2AiJRiqJVEGElg6XT7fdgAK0J8MbI3q7tzBarAqRH+MGapRohfbh+YsHVYy+YP2Dbm1XOxpMARmR7IlrSWQZuXkvZRm0+laSI0srq1TTTfezT34boYTbwtGri6kGSWofjqTi1FTV2GwFXdWaSTiH0GRBH19FU7E0RV4cOyDQ2dIY+QfwZzN7hCwtKarIwzYa5cXx57o0SUFsljeebhMukd0ibqnYphPu6k518K7XscNXWe+OLgjct0pkP9FlHwVkwlp/czTo+uJBGAU7KxX8DeH3W5opP+JTH7baBinSYkZ4W7H3v/uURoxmW4i4YArrF8z1sdyRG28l2VQUuedcPxl+fT+wICcqkuu5hEnie5Ydm0r0JiHwwTSLp0kiOtBD2etsNcXE3jOByD6BXCWxrcCREzPRC3bQtG/SWAjchcNeiao9JaQPbZby6Vc0AJb1ju/0MirxUMDPyop5/wkcVv0Ew9eYVjfdz5CBY7uuTBVnTRzLV04eD0IwGEpjBbKekAsJiV0DT7NwCFNinNwLig3Rjs//qcnltyHpmLAfGTcXpuJBVsXUtF1+4z/hMRwO8aDsFQ== MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BY5PR11MB4007.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 122b2811-ab44-4d4e-c912-08d86067afb0 X-MS-Exchange-CrossTenant-originalarrivaltime: 24 Sep 2020 08:56:11.6672 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: /tXvE/OOOBnzBm04IaDSz5rE9456R4kGGfnIJ2tzZz8hg8LXPKSWslZhFTNMSEkS5B1hkJANFiCeJQtN/GIYbw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR11MB3896 Return-Path: ray.ni@intel.com X-OriginatorOrg: intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Aaron, I understand the requirement now. Can we avoid adding new PCD but re-interpret the ShadowMicrocode() paramete= r to achieve the same result? For example, we can say when CpuIdCount is 0 and MicrocodeCpuId =3D=3D NULL= , it means all microcode need to be shadowed. The benefit is: platform can use the single interface to control the behavi= or. Thanks, Ray > -----Original Message----- > From: Li, Aaron > Sent: Thursday, September 24, 2020 9:38 AM > To: Ni, Ray ; devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Fu, Siyuan > > Subject: RE: [PATCH v1 1/1] IntelSiliconPkg/ShadowMicrocodePei: Add PCD f= or > shadowing all microcode. >=20 > Hi Ray, >=20 > Accroding to > https://edk2.groups.io/g/devel/files/Designs/2020/0214/Support%20the%202n= d > %20Microcode%20FV%20Flash%20Region.pdf > The ShadowMicrocodePei provide a FIT based shadow microcode ppi to > MpInitLib. It's needed. >=20 >=20 > Best, > Aaron >=20 > > -----Original Message----- > > From: Ni, Ray > > Sent: Wednesday, September 23, 2020 2:25 PM > > To: Li, Aaron ; devel@edk2.groups.io > > Cc: Chaganty, Rangasai V ; Fu, Siyuan > > > > Subject: RE: [PATCH v1 1/1] IntelSiliconPkg/ShadowMicrocodePei: Add PCD > > for shadowing all microcode. > > > > MpInitLib already contains logic to shadow microcode to memory. > > Is this still needed? > > > > > -----Original Message----- > > > From: Li, Aaron > > > Sent: Wednesday, August 12, 2020 3:55 PM > > > To: devel@edk2.groups.io > > > Cc: Ni, Ray ; Chaganty, Rangasai V > > > ; Fu, Siyuan > > > Subject: [PATCH v1 1/1] IntelSiliconPkg/ShadowMicrocodePei: Add PCD f= or > > > shadowing all microcode. > > > > > > This patch is to add a PCD PcdShadowAllMicrocode to support shadowing > > > all microcode patch to memory. > > > > > > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2891 > > > > > > Signed-off-by: Aaron Li > > > Cc: Ray Ni > > > Cc: Rangasai V Chaganty > > > Cc: Siyuan Fu > > > --- > > > > > > > > Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocodeP > > ei.c > > > | 4 ++++ > > > > > > > > Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocodeP > > ei.i > > > nf | 3 +++ > > > Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec = | 7 > +++++++ > > > 3 files changed, 14 insertions(+) > > > > > > diff --git > > > > > a/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocod > > ePei > > > .c > > > > > b/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocod > > ePei > > > .c > > > index 8d6574f66794..5c7ee6910c8e 100644 > > > --- > > > > > a/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocod > > ePei > > > .c > > > +++ > > > > > b/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocod > > ePei > > > .c > > > @@ -132,6 +132,10 @@ IsMicrocodePatchNeedLoad ( > > > CPU_MICROCODE_EXTENDED_TABLE *ExtendedTable; > > > > > > UINTN Index; > > > > > > > > > > > > + if (FeaturePcdGet (PcdShadowAllMicrocode)) { > > > > > > + return TRUE; > > > > > > + } > > > > > > + > > > > > > // > > > > > > // Check the 'ProcessorSignature' and 'ProcessorFlags' in microcod= e patch > > > header. > > > > > > // > > > > > > diff --git > > > > > a/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocod > > ePei > > > .inf > > > > > b/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocod > > ePei > > > .inf > > > index 019400ab31da..581780add891 100644 > > > --- > > > > > a/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocod > > ePei > > > .inf > > > +++ > > > > > b/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocod > > ePei > > > .inf > > > @@ -39,5 +39,8 @@ [Guids] > > > gEdkiiMicrocodeShadowInfoHobGuid > > > > > > gEdkiiMicrocodeStorageTypeFlashGuid > > > > > > > > > > > > +[Pcd] > > > > > > + gIntelSiliconPkgTokenSpaceGuid.PcdShadowAllMicrocode > > > > > > + > > > > > > [Depex] > > > > > > TRUE > > > > > > diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec > > > b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec > > > index e4a7fec3a3ea..3a12fe99fac6 100644 > > > --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec > > > +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec > > > @@ -76,6 +76,13 @@ [Protocols] > > > # Include/Protocol/PlatformDeviceSecurityPolicy.h > > > > > > gEdkiiDeviceSecurityPolicyProtocolGuid =3D {0x7ea41a99, 0x5e32, 0x= 4c97, > > > {0x88, 0xc4, 0xd6, 0xe7, 0x46, 0x84, 0x9, 0xd4}} > > > > > > > > > > > > +[PcdsFeatureFlag] > > > > > > + ## Indicates if all microcode update patches shall be shadowed to > > memory. > > > > > > + # TRUE - All microcode patches will be shadowed.
> > > > > > + # FALSE - Only the microcode for current present processors will= be > > > shadowed.
> > > > > > + # @Prompt Shadow all microcode update patches. > > > > > > + > > > > > gIntelSiliconPkgTokenSpaceGuid.PcdShadowAllMicrocode|FALSE|BOOLEAN| > > 0x > > > 00000006 > > > > > > + > > > > > > [PcdsFixedAtBuild, PcdsPatchableInModule] > > > > > > ## Error code for VTd error.

> > > > > > # EDKII_ERROR_CODE_VTD_ERROR =3D (EFI_IO_BUS_UNSPECIFIED | > > > (EFI_OEM_SPECIFIC | 0x00000000)) =3D 0x02008000
> > > > > > -- > > > 2.23.0.windows.1