From: Sebastien Boeuf <sebastien.boeuf@intel.com>

The goal of this series is to reduce the amount of inappropriate PIO
and MMIO accesses generated by the firmware when running on Cloud
Hypervisor.

For MMIO accesses, it is about providing the right base address where
the firmware will be loaded by the VMM in order to avoid unexpected
accesses to some address ranges.

For PIO accesses, it is about preventing some read/write to be performed
in the first place, as we know the underlying device is not emulated by
Cloud Hypervisor.

Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>

Sebastien Boeuf (4):
  OvmfPkg: CloudHv: Fix FW_BASE_ADDRESS
  OvmfPkg: Check for QemuFwCfg availability before accessing it
  OvmfPkg: CloudHv: Rely on QemuFwCfgLibNull implementation
  OvmfPkg: Don't access A20 gate register on Cloud Hypervisor

 OvmfPkg/CloudHv/CloudHvDefines.fdf.inc        | 65 +++++++++++++++++++
 OvmfPkg/CloudHv/CloudHvX64.dsc                |  4 +-
 OvmfPkg/CloudHv/CloudHvX64.fdf                |  2 +-
 OvmfPkg/Library/PlatformInitLib/Platform.c    | 13 ++--
 .../QemuBootOrderLib/QemuBootOrderLib.c       |  8 ++-
 5 files changed, 82 insertions(+), 10 deletions(-)
 create mode 100644 OvmfPkg/CloudHv/CloudHvDefines.fdf.inc

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2.32.0