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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Sai Chaganty =20 -----Original Message----- From: Luo, Heng =20 Sent: Tuesday, February 09, 2021 12:46 AM To: devel@edk2.groups.io Cc: Chaganty, Rangasai V ; Desimone, Nathani= el L Subject: [Patch V2 1/8] TigerlakeOpenBoardPkg: Add package and headers REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3175 Create the TigerlakeOpenBoardPkg to provide board support code. The package= may support Tigerlake boards. The package serves as a board support packag= e in the EDK II Minimum Platform design. Silicon support for this package i= s provided in TigerLakeFspBinPkg in the FSP repository and TigerlakeSilicon= Pkg in the edk2-platforms repository. Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Platform/Intel/TigerlakeOpenBoardPkg/Include/PlatformBoardConfig.h | 61 += ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/Include/PlatformBoardId.h | 17 += ++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/Include/PolicyUpdateMacro.h | 49 += ++++++++++++++++++++++++++++++++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/OpenBoardPkg.dec | 153 += +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++ 4 files changed, 280 insertions(+) diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Include/PlatformBoardConf= ig.h b/Platform/Intel/TigerlakeOpenBoardPkg/Include/PlatformBoardConfig.h new file mode 100644 index 0000000000..148abcce74 --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/Include/PlatformBoardConfig.h @@ -0,0 +1,61 @@ +/** @file+ Header file for Platform Boards Configurations.+++ Copyright = (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identi= fier: BSD-2-Clause-Patent+**/++#ifndef _PLATFORM_BOARD_CONFIG_H+#define _PL= ATFORM_BOARD_CONFIG_H++#include +#include +++#pragma pack(1)++typedef struct {+ UINT8 ClkReqNumber : 4;+ UINT8 Clk= ReqSupported : 1;+ UINT8 DeviceResetPadActiveHigh : 1;+ UINT32 DeviceRese= tPad;+} ROOT_PORT_CLK_INFO;++typedef struct {+ UINT8 Section;+ UINT8 Pin;= +} EXPANDER_GPIO_CONFIG;++typedef struct {+ UINT8 Type;+ UINT8 Reserved[3= ]; // alignment for COMMON_GPIO_CONFIG+ union {+ UINT32 Pin;+ EXPAN= DER_GPIO_CONFIG Expander;+ } u;+} BOARD_GPIO_CONFIG;++// Do not change the= encoding. It must correspond with PCH_PCIE_CLOCK_USAGE from PCH RC.+#defin= e NOT_USED 0xFF+#define FREE_RUNNING 0x80+#define LAN_CLOCK 0x70+#de= fine PCIE_PEG 0x40+#define PCIE_PCH 0x00++typedef struct {+ UINT32= ClockUsage;+ UINT32 ClkReqSupported;+} PCIE_CLOCK_CONFIG;++typedef union = {+ UINT64 Blob;+ BOARD_GPIO_CONFIG BoardGpioConfig;+ ROOT_PORT_CLK_INFO= Info;+ PCIE_CLOCK_CONFIG PcieClock;+} PCD64_BLOB;++#pragma pack()++#endi= f // _PLATFORM_BOARD_CONFIG_H+diff --git a/Platform/Intel/TigerlakeOpenBoar= dPkg/Include/PlatformBoardId.h b/Platform/Intel/TigerlakeOpenBoardPkg/Inclu= de/PlatformBoardId.h new file mode 100644 index 0000000000..2e1ee9eca4 --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/Include/PlatformBoardId.h @@ -0,0 +1,17 @@ +/** @file+ Defines Platform BoardIds++ Copyright (c) 2021, Intel Corpora= tion. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Pate= nt+**/++#ifndef _PLATFORM_BOARD_ID_H_+#define _PLATFORM_BOARD_ID_H_++// Tig= erLake Sku IDs+#define SkuIdTglU 0x1++// TigerLake = Board Id 0x01+#define BoardIdTglUDdr4 0x01++#endif // _PL= ATFORM_BOARD_ID_H_diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Include= /PolicyUpdateMacro.h b/Platform/Intel/TigerlakeOpenBoardPkg/Include/PolicyU= pdateMacro.h new file mode 100644 index 0000000000..0848efe5b6 --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/Include/PolicyUpdateMacro.h @@ -0,0 +1,49 @@ ++/** @file+ Macros for platform to update different types of policy.++ =20 ++Copyright (c) 2021, Intel Corporation. All rights reserved.
+ =20 ++SPDX-License-Identifier: BSD-2-Clause-Patent+**/++#ifndef=20 ++_POLICY_UPDATE_MACRO_H_+#define _POLICY_UPDATE_MACRO_H_++#ifdef=20 ++UPDATE_POLICY+#undef UPDATE_POLICY+#endif++#ifdef COPY_POLICY+#undef=20 ++COPY_POLICY+#endif++#ifdef GET_POLICY+#undef GET_POLICY+#endif++#ifdef=20 ++AND_POLICY+#undef AND_POLICY+#endif++#ifdef OR_POLICY+#undef=20 ++OR_POLICY+#endif++#if FixedPcdGetBool(PcdFspModeSelection) =3D=3D 1+//+//= =20 ++MACROS for platform code use+//+#define UPDATE_POLICY(UpdField,=20 ++ConfigField, Value) UpdField =3D Value;+#define COPY_POLICY(UpdField,=20 ++ConfigField, Value, Size) CopyMem (UpdField, Value, Size);+#define=20 ++GET_POLICY(UpdField, ConfigField, Value) Value =3D UpdField;+#define=20 ++AND_POLICY(UpdField, ConfigField, Value) UpdField &=3D Value;+#define=20 ++OR_POLICY(UpdField, ConfigField, Value) UpdField |=3D=20 ++Value;+#else+#define UPDATE_POLICY(UpdField, ConfigField, Value) =20 ++ConfigField =3D Value;+#define COPY_POLICY(UpdField, ConfigField, Value,= =20 ++Size) CopyMem (ConfigField, Value, Size);+#define=20 ++GET_POLICY(UpdField, ConfigField, Value) Value =3D ConfigField;+#define= =20 ++AND_POLICY(UpdField, ConfigField, Value) ConfigField &=3D=20 ++Value;+#define OR_POLICY(UpdField, ConfigField, Value) ConfigField |=3D= =20 ++Value;+#endif++#endif //_POLICY_UPDATE_MACRO_H_diff --git=20 ++a/Platform/Intel/TigerlakeOpenBoardPkg/OpenBoardPkg.dec=20 ++b/Platform/Intel/TigerlakeOpenBoardPkg/OpenBoardPkg.dec new file mode 100644 index 0000000000..91f0a88470 --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/OpenBoardPkg.dec @@ -0,0 +1,153 @@ +## @file+#+# The DEC files are used by the utilities that parse DSC and+# = INF files to generate AutoGen.c and AutoGen.h files+# for the build infrast= ructure.+#+# Copyright (c) 2021, Intel Corporation. All rights reserved.+# SPDX-License-Identifier: BSD-2-Clause-Patent+#+##+++[Defines]+DEC_SPE= CIFICATION =3D 0x00010017+PACKAGE_NAME =3D OpenBoardPkg+PACKAGE_VERSION =3D= 0.1+PACKAGE_GUID =3D 734F5E12-4C70-4EC9-908B-D7421B4B128C++[Includes]+Incl= ude+TigerlakeURvp/Include++[Guids]+ gBoardModuleTokenSpaceGuid = =3D {0x72d1fff7, 0xa42a, 0x4219, {0xb9, 0x95, 0x5a, 0x67, 0x53, 0x6e, 0xa4= , 0x2a}}+ # gUefiShellFileGuid is FILE GUID for MinUefiShell.inf/UefiShell= .inf/Shell.inf.+ gUefiShellFileGuid =3D {0x7c04a583, 0= x9e3e, 0x4f1c, {0xad, 0x65, 0xe0, 0x52, 0x68, 0xd0, 0xb4, 0xd1}}+ gPlatfor= mInitFvLocationGuid =3D {0xa564010a, 0x1d90, 0x4b1c, {0x8d, 0x10= , 0xcb, 0xba, 0xff, 0xb2, 0x55, 0x42}}+ gTianoLogoGuid = =3D {0x7BB28B99, 0x61BB, 0x11D5, {0x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F, = 0xC1, 0x4D}}++[Protocols]+ gPlatformNvsAreaProtocolGuid =3D {0xc= 77ae556, 0x40a3, 0x41c0, {0xac, 0xe6, 0x71, 0x43, 0x8c, 0x60, 0xf8, 0x71}}+= +[Ppis]++[LibraryClasses]++[PcdsFixedAtBuild, PcdsPatchableInModule]++[Pcds= FixedAtBuild]+ gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange|0x0010|UINT1= 6|0x10001004+ gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding|0x3c03|UIN= T16|0x10001005++ gBoardModuleTokenSpaceGuid.PcdLpcSioIndexPort|0x4e|UINT16= |0x90000018+ gBoardModuleTokenSpaceGuid.PcdLpcSioDataPort|0x4f|UINT16|0x90= 00001F++ gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort|0x164E|UINT= 16|0x9000001C+ gBoardModuleTokenSpaceGuid.PcdSioBaseAddress|0x0680|UINT16|= 0x9000001D++ gBoardModuleTokenSpaceGuid.PcdDmiBaseAddress|0xFED18000|UINT6= 4|0x90000003+ gBoardModuleTokenSpaceGuid.PcdDmiMmioSize|0x1000|UINT32|0x90= 000004++ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesBase|0x00000= 000|UINT32|0x20000040+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinari= esSize|0x00000000|UINT32|0x20000041+ gBoardModuleTokenSpaceGuid.PcdFlashFv= FirmwareBinariesOffset|0x00000000|UINT32|0x20000042+ gBoardModuleTokenSpac= eGuid.PcdFlashFvOptionalBase|0x00000000|UINT32|0x2000004C+ gBoardModuleTok= enSpaceGuid.PcdFlashFvOptionalSize|0x00000000|UINT32|0x2000004D+ gBoardMod= uleTokenSpaceGuid.PcdFlashFvOptionalOffset|0x00000000|UINT32|0x2000004E+ g= BoardModuleTokenSpaceGuid.PcdEpBaseAddress|0xFED19000|UINT64|0x90000005+ g= BoardModuleTokenSpaceGuid.PcdEpMmioSize|0x1000|UINT32|0x90000006++[PcdsDyna= mic]+ # Board GPIO Table+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTable|0|= UINT32|0x00000040+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize|0|UINT= 16|0x00000041+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem|0|UINT32= |0x00000042+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMemSize|0|UINT= 16|0x00000043++ # SA Misc Configuration+ gBoardModuleTokenSpaceGuid.PcdSa= MiscUserBd|0|UINT8|0x00000066+ gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSiz= eAdjustment|0|UINT16|0x00000067++ # DRAM Configuration+ gBoardModuleToken= SpaceGuid.PcdMrcSpdData|0|UINT32|0x00000174+ gBoardModuleTokenSpaceGuid.Pc= dMrcSpdDataSize|0|UINT16|0x00000175++ # SPD Address Table+ gBoardModuleTo= kenSpaceGuid.PcdMrcSpdAddressTable0|0|UINT8|0x00000099+ gBoardModuleTokenS= paceGuid.PcdMrcSpdAddressTable1|0|UINT8|0x0000009A+ gBoardModuleTokenSpace= Guid.PcdMrcSpdAddressTable2|0|UINT8|0x0000009B+ gBoardModuleTokenSpaceGuid= .PcdMrcSpdAddressTable3|0|UINT8|0x0001009C++ # Root Port Clock Info+ gBoa= rdModuleTokenSpaceGuid.PcdPcieClock0|0|UINT64|0x0000009E+ gBoardModuleToke= nSpaceGuid.PcdPcieClock1|0|UINT64|0x0000009F+ gBoardModuleTokenSpaceGuid.P= cdPcieClock2|0|UINT64|0x000000A0+ gBoardModuleTokenSpaceGuid.PcdPcieClock3= |0|UINT64|0x000000A1+ gBoardModuleTokenSpaceGuid.PcdPcieClock4|0|UINT64|0x= 000000A2+ gBoardModuleTokenSpaceGuid.PcdPcieClock5|0|UINT64|0x000000A3+ g= BoardModuleTokenSpaceGuid.PcdPcieClock6|0|UINT64|0x000000A4+ gBoardModuleT= okenSpaceGuid.PcdPcieClock7|0|UINT64|0x000000A5+ gBoardModuleTokenSpaceGui= d.PcdPcieClock8|0|UINT64|0x000000A6+ gBoardModuleTokenSpaceGuid.PcdPcieClo= ck9|0|UINT64|0x000000A7+ gBoardModuleTokenSpaceGuid.PcdPcieClock10|0|UINT6= 4|0x000000A8+ gBoardModuleTokenSpaceGuid.PcdPcieClock11|0|UINT64|0x000000A= 9+ gBoardModuleTokenSpaceGuid.PcdPcieClock12|0|UINT64|0x000000AA+ gBoardM= oduleTokenSpaceGuid.PcdPcieClock13|0|UINT64|0x000000AB+ gBoardModuleTokenS= paceGuid.PcdPcieClock14|0|UINT64|0x000000AC+ gBoardModuleTokenSpaceGuid.Pc= dPcieClock15|0|UINT64|0x000000AD++ # USB 2.0 Port Over Current Pin+ gBoar= dModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0|0xFF|UINT8|0x000000CF+ g= BoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1|0xFF|UINT8|0x000000D0= + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2|0xFF|UINT8|0x0000= 00D1+ gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3|0xFF|UINT8|0x= 000000D2+ gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4|0xFF|UINT= 8|0x000000D3+ gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5|0xFF|= UINT8|0x000000D4+ gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6|0= xFF|UINT8|0x000000D5+ gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPor= t7|0xFF|UINT8|0x000000D6+ gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPi= nPort8|0xFF|UINT8|0x000000D7+ gBoardModuleTokenSpaceGuid.PcdUsb20OverCurre= ntPinPort9|0xFF|UINT8|0x000000D8+ gBoardModuleTokenSpaceGuid.PcdUsb20OverC= urrentPinPort10|0xFF|UINT8|0x000000D9+ gBoardModuleTokenSpaceGuid.PcdUsb20= OverCurrentPinPort11|0xFF|UINT8|0x000000DA+ gBoardModuleTokenSpaceGuid.Pcd= Usb20OverCurrentPinPort12|0xFF|UINT8|0x000000DB+ gBoardModuleTokenSpaceGui= d.PcdUsb20OverCurrentPinPort13|0xFF|UINT8|0x000000DC+ gBoardModuleTokenSpa= ceGuid.PcdUsb20OverCurrentPinPort14|0xFF|UINT8|0x000000DD+ gBoardModuleTok= enSpaceGuid.PcdUsb20OverCurrentPinPort15|0xFF|UINT8|0x000000DE++ # USB 3.0= Port Over Current Pin+ gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinP= ort0|0xFF|UINT8|0x000000DF+ gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrent= PinPort1|0xFF|UINT8|0x000000E0+ gBoardModuleTokenSpaceGuid.PcdUsb30OverCur= rentPinPort2|0xFF|UINT8|0x000000E1+ gBoardModuleTokenSpaceGuid.PcdUsb30Ove= rCurrentPinPort3|0xFF|UINT8|0x000000E2+ gBoardModuleTokenSpaceGuid.PcdUsb3= 0OverCurrentPinPort4|0xFF|UINT8|0x000000E3+ gBoardModuleTokenSpaceGuid.Pcd= Usb30OverCurrentPinPort5|0xFF|UINT8|0x000000E4+ gBoardModuleTokenSpaceGuid= .PcdUsb30OverCurrentPinPort6|0xFF|UINT8|0x000000E5+ gBoardModuleTokenSpace= Guid.PcdUsb30OverCurrentPinPort7|0xFF|UINT8|0x000000E6+ gBoardModuleTokenS= paceGuid.PcdUsb30OverCurrentPinPort8|0xFF|UINT8|0x000000E7+ gBoardModuleTo= kenSpaceGuid.PcdUsb30OverCurrentPinPort9|0xFF|UINT8|0x000000E8+ gBoardModu= leTokenSpaceGuid.PcdCpuUsb30PortEnable|0|UINT8|0x00100032++ # CPU+ gBoard= ModuleTokenSpaceGuid.PcdCpuRatio|0x0|UINT8|0x00000200+ gBoardModuleTokenSp= aceGuid.PcdBiosGuard|0x0|UINT8|0x00000201++ # ACPI+ gBoardModuleTokenSpac= eGuid.PcdAcpiSleepState|1|UINT8|0x40000002+ gBoardModuleTokenSpaceGuid.Pcd= AcpiHibernate|1|UINT8|0x40000003+ gBoardModuleTokenSpaceGuid.PcdLowPowerS0= Idle|0|UINT8|0x40000004+ gBoardModuleTokenSpaceGuid.PcdDisableActiveTripPo= ints|1|UINT8|0x4000000A+ gBoardModuleTokenSpaceGuid.PcdDisablePassiveTripP= oints|0|UINT8|0x4000000B+ gBoardModuleTokenSpaceGuid.PcdDisableCriticalTri= pPoints|1|UINT8|0x4000000C+ gBoardModuleTokenSpaceGuid.PcdAcpiGnvsAddress|= 0|UINT64|0x40000013++ gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid|{0x22,= 0x61, 0xd4, 0x4a, 0xeb, 0xff, 0x52, 0x4a, 0xbf, 0xb0, 0x51, 0x8c, 0xfc, 0x= a0, 0x2d, 0xb0}|VOID*|0x40000014++[PcdsDynamicEx]++[PcdsDynamic, PcdsDynami= cEx]++[PcdsPatchableInModule]++[PcdsFeatureFlag]+ gBoardModuleTokenSpaceGu= id.PcdIntelGopEnable |TRUE|BOOLEAN|0xF0000062--=20 2.24.0.windows.2