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From: "Chaganty, Rangasai V" <rangasai.v.chaganty@intel.com>
To: "Luo, Heng" <heng.luo@intel.com>,
	"devel@edk2.groups.io" <devel@edk2.groups.io>
Cc: "Desimone, Nathaniel L" <nathaniel.l.desimone@intel.com>
Subject: Re: [Patch V2 3/8] TigerlakeOpenBoardPkg: Add library instances
Date: Tue, 9 Feb 2021 23:45:18 +0000	[thread overview]
Message-ID: <BY5PR11MB4467555F05CC46F00B9DBD10B68E9@BY5PR11MB4467.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20210209084549.4417-3-heng.luo@intel.com>

Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com> 

-----Original Message-----
From: Luo, Heng <heng.luo@intel.com> 
Sent: Tuesday, February 09, 2021 12:46 AM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
Subject: [Patch V2 3/8] TigerlakeOpenBoardPkg: Add library instances

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3175

Adds the following library instances:
  * FspWrapper/Library/PeiFspPolicyInitLib
  * FspWrapper/Library/PeiSiDefaultPolicyInitLib
  * FspWrapper/Library/PeiSiPreMemDefaultPolicyInitLib
  * Library/BasePlatformHookLib
  * Library/SmmSpiFlashCommonLib
  * Policy/Library/DxeSiliconPolicyUpdateLib

Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Signed-off-by: Heng Luo <heng.luo@intel.com>
---
 Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c                        |  79 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspMePolicyInitLib.c                         |  51 +++++++++++++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspMiscUpdInitLib.c                          |  27 +++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPchPolicyInitLib.c                        | 372 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.c                           | 308 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.h                           | 187 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf                         | 183 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspSaPolicyInitLib.c                         | 240 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspSecurityPolicyInitLib.c                   |  49 +++++++++++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiDefaultPolicyInitLib/PeiSiDefaultPolicyInitLib.c               |  39 +++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiDefaultPolicyInitLib/PeiSiDefaultPolicyInitLib.inf             |  38 ++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiPreMemDefaultPolicyInitLib/PeiSiPreMemDefaultPolicyInitLib.c   |  40 ++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiPreMemDefaultPolicyInitLib/PeiSiPreMemDefaultPolicyInitLib.inf |  38 ++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c                                      | 391 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.inf                                    |  51 +++++++++++++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf                                  |  49 +++++++++++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c                                          | 210 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c                                    |  58 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c                            | 168 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxePchPolicyInit.c                            |  61 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.c                             |  61 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c                  |  97 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf                 |  49 +++++++++++++++++++++++++++++++++++++++++++++++++
 23 files changed, 2846 insertions(+)

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c
new file mode 100644
index 0000000000..1358d6a19b
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c
@@ -0,0 +1,79 @@
+/** @file

+  Implementation of Fsp CPU Policy Initialization.

+

+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>

+  SPDX-License-Identifier: BSD-2-Clause-Patent

+**/

+

+#include <PeiFspPolicyInitLib.h>

+

+#include <Ppi/SiPolicy.h>

+#include <Ppi/SecPlatformInformation2.h>

+

+#include <CpuAccess.h>

+#include <Library/HobLib.h>

+#include <Library/BaseMemoryLib.h>

+#include <Library/ConfigBlockLib.h>

+#include <Library/MemoryAllocationLib.h>

+#include <Library/PeiServicesLib.h>

+#include <Library/PeiServicesTablePointerLib.h>

+#include <Library/PcdLib.h>

+#include <FspEas.h>

+#include <PolicyUpdateMacro.h>

+

+/**

+  Performs FSP CPU PEI Policy initialization.

+

+  @param[in][out]  FspmUpd             Pointer to FSP UPD Data.

+

+  @retval          EFI_SUCCESS         FSP UPD Data is updated.

+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.

+  @retval          Other               FSP UPD Data update process fail.

+**/

+EFI_STATUS

+EFIAPI

+PeiFspCpuPolicyInitPreMem (

+  IN OUT FSPM_UPD    *FspmUpd

+  )

+{

+  CPU_CONFIG_LIB_PREMEM_CONFIG    *CpuConfigLibPreMemConfig;

+  CPU_SECURITY_PREMEM_CONFIG      *CpuSecurityPreMemConfig;

+#if FixedPcdGet8(PcdFspModeSelection) == 0

+  EFI_STATUS                      Status;

+  SI_PREMEM_POLICY_PPI            *SiPreMemPolicyPpi;

+  SiPreMemPolicyPpi = NULL;

+#endif

+

+  CpuConfigLibPreMemConfig = NULL;

+  CpuSecurityPreMemConfig = NULL;

+  DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SiCpuPolicy Pre-Mem Start\n"));

+

+#if FixedPcdGet8(PcdFspModeSelection) == 0

+  //

+  // Locate SiPreMemPolicyPpi

+  //

+  Status = PeiServicesLocatePpi (

+             &gSiPreMemPolicyPpiGuid,

+             0,

+             NULL,

+             (VOID **) &SiPreMemPolicyPpi

+             );

+  if (EFI_ERROR (Status)) {

+    return EFI_NOT_FOUND;

+  }

+  Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuConfigLibPreMemConfigGuid, (VOID *) &CpuConfigLibPreMemConfig);

+  DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SiCpuPolicy Pre-Mem End\n"));

+  Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuSecurityPreMemConfigGuid, (VOID *) &CpuSecurityPreMemConfig);

+  ASSERT_EFI_ERROR(Status);

+#endif

+  //

+  //  Cpu Config Lib policies

+  //

+  UPDATE_POLICY (FspmUpd->FspmConfig.CpuRatio, CpuConfigLibPreMemConfig->CpuRatio, 0);

+  DEBUG ((DEBUG_INFO, "BIOS Guard PCD and Policy are disabled\n"));

+  UPDATE_POLICY (FspmUpd->FspmConfig.BiosGuard, CpuSecurityPreMemConfig->BiosGuard, 0);

+  UPDATE_POLICY (FspmUpd->FspmConfig.PrmrrSize, CpuSecurityPreMemConfig->PrmrrSize, SIZE_1MB);

+  UPDATE_POLICY (FspmUpd->FspmConfig.EnableC6Dram, CpuSecurityPreMemConfig->EnableC6Dram, 1);

+

+  return EFI_SUCCESS;

+}

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspMePolicyInitLib.c b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspMePolicyInitLib.c
new file mode 100644
index 0000000000..53b5ef43cd
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspMePolicyInitLib.c
@@ -0,0 +1,51 @@
+/** @file

+  Implementation of Fsp Me Policy Initialization.

+

+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>

+  SPDX-License-Identifier: BSD-2-Clause-Patent

+**/

+

+#include <PeiFspPolicyInitLib.h>

+#include <Ppi/SiPolicy.h>

+#include <Library/ConfigBlockLib.h>

+

+/**

+  Performs FSP ME PEI Policy pre mem initialization.

+

+  @param[in][out]  FspmUpd             Pointer to FSP UPD Data.

+

+  @retval          EFI_SUCCESS         FSP UPD Data is updated.

+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.

+  @retval          Other               FSP UPD Data update process fail.

+**/

+EFI_STATUS

+EFIAPI

+PeiFspMePolicyInitPreMem (

+  IN OUT FSPM_UPD    *FspmUpd

+  )

+{

+  DEBUG ((DEBUG_INFO, "PeiFspMePolicyInitPreMem\n"));

+

+  return EFI_SUCCESS;

+}

+

+/**

+  Performs FSP ME PEI Policy initialization.

+

+  @param[in][out]  FspsUpd             Pointer to FSP UPD Data.

+

+  @retval          EFI_SUCCESS         FSP UPD Data is updated.

+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.

+  @retval          Other               FSP UPD Data update process fail.

+**/

+EFI_STATUS

+EFIAPI

+PeiFspMePolicyInit (

+  IN OUT FSPS_UPD    *FspsUpd

+  )

+{

+  DEBUG ((DEBUG_INFO, "PeiFspMePolicyInit \n"));

+

+  return EFI_SUCCESS;

+}

+

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspMiscUpdInitLib.c b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspMiscUpdInitLib.c
new file mode 100644
index 0000000000..5a12e569d9
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspMiscUpdInitLib.c
@@ -0,0 +1,27 @@
+/** @file

+  Implementation of Fsp Misc UPD Initialization.

+

+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>

+  SPDX-License-Identifier: BSD-2-Clause-Patent

+**/

+

+#include <PeiFspPolicyInitLib.h>

+

+#include <Library/MemoryAllocationLib.h>

+#include <Library/HobLib.h>

+/**

+  Performs FSP Misc UPD initialization.

+

+  @param[in][out]  FspmUpd             Pointer to FSPM_UPD Data.

+

+  @retval          EFI_SUCCESS         FSP UPD Data is updated.

+**/

+EFI_STATUS

+EFIAPI

+PeiFspMiscUpdInitPreMem (

+  IN OUT FSPM_UPD    *FspmUpd

+  )

+{

+  return EFI_SUCCESS;

+}

+

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPchPolicyInitLib.c b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPchPolicyInitLib.c
new file mode 100644
index 0000000000..67b75d6faf
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPchPolicyInitLib.c
@@ -0,0 +1,372 @@
+/** @file

+  Implementation of Fsp PCH Policy Initialization.

+

+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>

+  SPDX-License-Identifier: BSD-2-Clause-Patent

+**/

+

+#include <PeiFspPolicyInitLib.h>

+

+#include <Ppi/SiPolicy.h>

+#include <Library/MemoryAllocationLib.h>

+#include <Library/PeiServicesLib.h>

+#include <Library/PchInfoLib.h>

+#include <Library/ConfigBlockLib.h>

+#include <Pins/GpioPinsVer2Lp.h>

+#include <TcssInfo.h>

+#include <TcssPeiConfig.h>

+#include <PolicyUpdateMacro.h>

+#include <PlatformBoardConfig.h>

+

+//

+// USB limits

+//

+#define PCH_MAX_USB2_PORTS                  16

+#define PCH_MAX_USB3_PORTS                  10

+

+//

+// TypeC port map GPIO pin

+//

+IOM_AUX_ORI_PAD_CONFIG mIomAuxNullTable[MAX_IOM_AUX_BIAS_COUNT] = {

+  // Pull UP GPIO Pin, Pull Down GPIO pin

+  {0,                  0}, // Port 0

+  {0,                  0}, // Port 1

+  {0,                  0}, // Port 2

+  {0,                  0}, // Port 3

+};

+

+

+VOID

+UpdatePcieClockInfo (

+  PCH_PCIE_RP_PREMEM_CONFIG  *PcieRpPreMemConfig,

+  IN FSPM_UPD                 *FspmUpd,

+  UINTN                      Index,

+  UINT64                     Data

+  )

+{

+  PCD64_BLOB Pcd64;

+

+  Pcd64.Blob = Data;

+  DEBUG ((DEBUG_INFO, "UpdatePcieClockInfo ClkIndex %x ClkUsage %x, Supported %x\n", Index, Pcd64.PcieClock.ClockUsage, Pcd64.PcieClock.ClkReqSupported));

+

+  UPDATE_POLICY (FspmUpd->FspmConfig.PcieClkSrcUsage[Index], PcieRpPreMemConfig->PcieClock[Index].Usage, (UINT8)Pcd64.PcieClock.ClockUsage);

+  UPDATE_POLICY (FspmUpd->FspmConfig.PcieClkSrcClkReq[Index], PcieRpPreMemConfig->PcieClock[Index].ClkReq, Pcd64.PcieClock.ClkReqSupported ? (UINT8)Index : 0xFF);

+}

+/**

+  Performs FSP PCH PEI Policy pre mem initialization.

+

+  @param[in][out]  FspmUpd             Pointer to FSP UPD Data.

+

+  @retval          EFI_SUCCESS         FSP UPD Data is updated.

+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.

+  @retval          Other               FSP UPD Data update process fail.

+**/

+EFI_STATUS

+EFIAPI

+PeiFspPchPolicyInitPreMem (

+  IN OUT FSPM_UPD    *FspmUpd

+  )

+{

+  UINTN                        Index;

+  PCH_PCIE_RP_PREMEM_CONFIG    *PcieRpPreMemConfig;

+  HDAUDIO_PREMEM_CONFIG        *HdaPreMemConfig;

+#if FixedPcdGet8(PcdFspModeSelection) == 0

+  SI_PREMEM_POLICY_PPI         *SiPreMemPolicy;

+  EFI_STATUS                   Status;

+

+  //

+  // Locate PchPreMemPolicyPpi

+  //

+  SiPreMemPolicy = NULL;

+  PcieRpPreMemConfig = NULL;

+  HdaPreMemConfig = NULL;

+  Status = PeiServicesLocatePpi (

+             &gSiPreMemPolicyPpiGuid,

+             0,

+             NULL,

+             (VOID **) &SiPreMemPolicy

+             );

+  if (EFI_ERROR (Status)) {

+    return EFI_NOT_FOUND;

+  }

+

+  Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gPcieRpPreMemConfigGuid, (VOID *) &PcieRpPreMemConfig);

+  ASSERT_EFI_ERROR (Status);

+  Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gHdAudioPreMemConfigGuid, (VOID *) &HdaPreMemConfig);

+  ASSERT_EFI_ERROR (Status);

+#else

+  PcieRpPreMemConfig = NULL;

+  HdaPreMemConfig = NULL;

+#endif

+

+  UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 0, PcdGet64  (PcdPcieClock0));

+  UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 1, PcdGet64  (PcdPcieClock1));

+  UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 2, PcdGet64  (PcdPcieClock2));

+  UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 3, PcdGet64  (PcdPcieClock3));

+  UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 4, PcdGet64  (PcdPcieClock4));

+  UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 5, PcdGet64  (PcdPcieClock5));

+  UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 6, PcdGet64  (PcdPcieClock6));

+  UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 7, PcdGet64  (PcdPcieClock7));

+  UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 8, PcdGet64  (PcdPcieClock8));

+  UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 9, PcdGet64  (PcdPcieClock9));

+  UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 10, PcdGet64 (PcdPcieClock10));

+  UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 11, PcdGet64 (PcdPcieClock11));

+  UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 12, PcdGet64 (PcdPcieClock12));

+  UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 13, PcdGet64 (PcdPcieClock13));

+  UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 14, PcdGet64 (PcdPcieClock14));

+  UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 15, PcdGet64 (PcdPcieClock15));

+

+  //

+  // Update HDA policies

+  //

+  UPDATE_POLICY (FspmUpd->FspmConfig.PchHdaIDispLinkTmode, HdaPreMemConfig->IDispLinkTmode, 0);

+  UPDATE_POLICY (FspmUpd->FspmConfig.PchHdaSdiEnable[0], HdaPreMemConfig->AudioLinkHda.SdiEnable[0], FALSE);

+

+  for (Index = 0; Index < GetPchHdaMaxDmicLinkNum (); Index++) {

+    UPDATE_POLICY (FspmUpd->FspmConfig.PchHdaAudioLinkDmicClockSelect[Index], HdaPreMemConfig->AudioLinkDmic[Index].DmicClockSelect, 0);

+  }

+  DEBUG((DEBUG_INFO | DEBUG_INIT, "UpdatePeiPchPolicyPreMem\n"));

+  return EFI_SUCCESS;

+}

+

+/**

+  This function updates USB Policy per port OC Pin number

+

+  @param[in]  PchUsbConfig     Pointer to USB_CONFIG data buffer

+  @param[in]  PortIndex        USB Port index

+  @param[in]  Pin              OverCurrent pin number

+**/

+VOID

+UpdateUsb20OverCurrentPolicy (

+  IN OUT FSPS_UPD               *FspsUpd,

+  IN USB_CONFIG                 *UsbConfig,

+  IN UINT8                      PortIndex,

+  UINT8                         Pin

+)

+{

+  if (PortIndex < MAX_USB2_PORTS && ((Pin < USB_OC_MAX_PINS) || (Pin == USB_OC_SKIP))) {

+      UPDATE_POLICY (

+        FspsUpd->FspsConfig.Usb2OverCurrentPin[PortIndex],

+        UsbConfig->PortUsb20[PortIndex].OverCurrentPin,

+        Pin

+        );

+  } else {

+    if (PortIndex >= MAX_USB2_PORTS) {

+      DEBUG ((DEBUG_ERROR, "UpdateUsb20OverCurrentPolicy: USB2 port number %d is not a valid USB2 port number\n", PortIndex));

+    } else {

+      DEBUG ((DEBUG_ERROR, "UpdateUsb20OverCurrentPolicy: Invalid OverCurrent pin specified USB2 port %d\n", PortIndex));

+    }

+  }

+}

+

+/**

+  This function updates USB Policy per port OC Pin number

+

+  @param[in]  PchUsbConfig     Pointer to USB_CONFIG data buffer

+  @param[in]  PortIndex        USB Port index

+  @param[in]  Pin              OverCurrent pin number

+**/

+VOID

+UpdateUsb30OverCurrentPolicy (

+  IN OUT FSPS_UPD               *FspsUpd,

+  IN USB_CONFIG                 *UsbConfig,

+  IN UINT8                      PortIndex,

+  UINT8                         Pin

+)

+{

+  if (PortIndex < MAX_USB3_PORTS && ((Pin < USB_OC_MAX_PINS) || (Pin == USB_OC_SKIP))) {

+    UPDATE_POLICY (

+        FspsUpd->FspsConfig.Usb3OverCurrentPin[PortIndex],

+        UsbConfig->PortUsb30[PortIndex].OverCurrentPin,

+        Pin

+        );

+  } else {

+    if (PortIndex >= MAX_USB2_PORTS) {

+      DEBUG ((DEBUG_ERROR, "UpdateUsb30OverCurrentPolicy: USB3 port number %d is not a valid USB3 port number\n", PortIndex));

+    } else {

+      DEBUG ((DEBUG_ERROR, "UpdateUsb30OverCurrentPolicy: Invalid OverCurrent pin specified USB3 port %d\n", PortIndex));

+    }

+  }

+}

+

+/**

+  This function performs PCH USB Platform Policy initialization

+

+  @param[in] PchUsbConfig         Pointer to USB_CONFIG data buffer

+  @param[in] PchSetup             Pointer to PCH_SETUP data buffer

+**/

+VOID

+UpdatePchUsbConfig (

+  IN OUT FSPS_UPD    *FspsUpd,

+  IN OUT USB_CONFIG  *UsbConfig

+  )

+{

+  UINTN              PortIndex;

+

+  UPDATE_POLICY (FspsUpd->FspsConfig.PchUsbOverCurrentEnable, UsbConfig->OverCurrentEnable, TRUE);

+

+  for (PortIndex = 0; PortIndex < GetPchUsb2MaxPhysicalPortNum (); PortIndex++) {

+    UPDATE_POLICY (FspsUpd->FspsConfig.PortUsb20Enable[PortIndex], UsbConfig->PortUsb20[PortIndex].Enable, TRUE);

+  }

+  for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb3PortNum (); PortIndex++) {

+    UPDATE_POLICY (FspsUpd->FspsConfig.PortUsb30Enable[PortIndex], UsbConfig->PortUsb30[PortIndex].Enable, TRUE);

+  }

+

+  UPDATE_POLICY (FspsUpd->FspsConfig.XdciEnable, UsbConfig->XdciConfig.Enable, FALSE);

+

+  //

+  // Platform Board programming per the layout of each port.

+  //

+  UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 0, PcdGet8 (PcdUsb20OverCurrentPinPort0));

+  UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 1, PcdGet8 (PcdUsb20OverCurrentPinPort1));

+  UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 2, PcdGet8 (PcdUsb20OverCurrentPinPort2));

+  UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 3, PcdGet8 (PcdUsb20OverCurrentPinPort3));

+  UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 4, PcdGet8 (PcdUsb20OverCurrentPinPort4));

+  UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 5, PcdGet8 (PcdUsb20OverCurrentPinPort5));

+  UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 6, PcdGet8 (PcdUsb20OverCurrentPinPort6));

+  UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 7, PcdGet8 (PcdUsb20OverCurrentPinPort7));

+  UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 8, PcdGet8 (PcdUsb20OverCurrentPinPort8));

+  UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 9, PcdGet8 (PcdUsb20OverCurrentPinPort9));

+  UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig,10, PcdGet8 (PcdUsb20OverCurrentPinPort10));

+  UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig,11, PcdGet8 (PcdUsb20OverCurrentPinPort11));

+  UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig,12, PcdGet8 (PcdUsb20OverCurrentPinPort12));

+  UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig,13, PcdGet8 (PcdUsb20OverCurrentPinPort13));

+  UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig,14, PcdGet8 (PcdUsb20OverCurrentPinPort14));

+  UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig,15, PcdGet8 (PcdUsb20OverCurrentPinPort15));

+

+  UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 0, PcdGet8 (PcdUsb30OverCurrentPinPort0));

+  UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 1, PcdGet8 (PcdUsb30OverCurrentPinPort1));

+  UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 2, PcdGet8 (PcdUsb30OverCurrentPinPort2));

+  UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 3, PcdGet8 (PcdUsb30OverCurrentPinPort3));

+  UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 4, PcdGet8 (PcdUsb30OverCurrentPinPort4));

+  UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 5, PcdGet8 (PcdUsb30OverCurrentPinPort5));

+  UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 6, PcdGet8 (PcdUsb30OverCurrentPinPort6));

+  UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 7, PcdGet8 (PcdUsb30OverCurrentPinPort7));

+  UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 8, PcdGet8 (PcdUsb30OverCurrentPinPort8));

+  UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 9, PcdGet8 (PcdUsb30OverCurrentPinPort9));

+

+}

+

+/**

+  Update CNVi config

+

+  @param[in] SiPolicy             Pointer to SI_POLICY_PPI

+  @param[in] FspsUpd              Pointer to FspsUpd structure

+  @param[in] PchSetup             Pointer to PCH_SETUP buffer

+**/

+STATIC

+VOID

+UpdateCnviConfig (

+  IN OUT FSPS_UPD              *FspsUpd,

+  IN OUT CNVI_CONFIG           *CnviConfig

+  )

+{

+

+  UPDATE_POLICY (FspsUpd->FspsConfig.CnviMode,           CnviConfig->Mode,           CnviModeDisabled);

+  UPDATE_POLICY (FspsUpd->FspsConfig.CnviBtCore,         CnviConfig->BtCore,         FALSE);

+  UPDATE_POLICY (FspsUpd->FspsConfig.CnviBtAudioOffload, CnviConfig->BtAudioOffload, 0);

+}

+

+/**

+  Performs FSP PCH PEI Policy initialization.

+

+  @param[in][out]  FspsUpd             Pointer to FSP UPD Data.

+

+  @retval          EFI_SUCCESS         FSP UPD Data is updated.

+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.

+  @retval          Other               FSP UPD Data update process fail.

+**/

+EFI_STATUS

+EFIAPI

+PeiFspPchPolicyInit (

+  IN OUT FSPS_UPD    *FspsUpd

+  )

+{

+  UINTN                        Index;

+  SATA_CONFIG                  *SataConfig;

+  USB_CONFIG                   *UsbConfig;

+  TCSS_PEI_CONFIG              *TcssConfig;

+  SERIAL_IO_CONFIG             *SerialIoConfig;

+  CNVI_CONFIG                  *CnviConfig;

+#if FixedPcdGet8(PcdFspModeSelection) == 0

+  SI_POLICY_PPI                *SiPolicy;

+  EFI_STATUS                   Status;

+#endif

+  DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP UpdatePeiPchPolicy\n"));

+

+  SataConfig = NULL;

+  UsbConfig = NULL;

+  TcssConfig = NULL;

+  SerialIoConfig = NULL;

+  CnviConfig = NULL;

+#if FixedPcdGet8(PcdFspModeSelection) == 0

+  //

+  // Locate SiPolicyPpi

+  //

+  SiPolicy = NULL;

+  Status = PeiServicesLocatePpi (

+             &gSiPolicyPpiGuid,

+             0,

+             NULL,

+             (VOID **) &SiPolicy

+             );

+  if (EFI_ERROR (Status)) {

+    return EFI_NOT_FOUND;

+  }

+

+  Status = GetConfigBlock ((VOID *) SiPolicy, &gSataConfigGuid, (VOID *) &SataConfig);

+  ASSERT_EFI_ERROR (Status);

+  Status = GetConfigBlock ((VOID *) SiPolicy, &gUsbConfigGuid, (VOID *) &UsbConfig);

+  ASSERT_EFI_ERROR (Status);

+  Status = GetConfigBlock ((VOID *) SiPolicy, &gTcssPeiConfigGuid, (VOID *) &TcssConfig);

+  ASSERT_EFI_ERROR (Status);

+  Status = GetConfigBlock ((VOID *) SiPolicy, &gSerialIoConfigGuid, (VOID *) &SerialIoConfig);

+  ASSERT_EFI_ERROR (Status);

+  Status = GetConfigBlock ((VOID *) SiPolicy, &gCnviConfigGuid, (VOID *) &CnviConfig);

+  ASSERT_EFI_ERROR (Status);

+  if (EFI_ERROR (Status)) {

+    return Status;

+  }

+#endif

+

+  //

+  // Update Sata Policies

+  //

+  UPDATE_POLICY (FspsUpd->FspsConfig.SataEnable, SataConfig->Enable, TRUE);

+  UPDATE_POLICY (FspsUpd->FspsConfig.SataMode, SataConfig->SataMode, SataModeAhci);

+

+  for (Index = 0; Index < PCH_MAX_SATA_PORTS; Index++) {

+    UPDATE_POLICY (FspsUpd->FspsConfig.SataPortsEnable[Index], SataConfig->PortSettings[Index].Enable, TRUE);

+  }

+

+  //

+  // Update Pch Usb Config

+  //

+  UpdatePchUsbConfig (FspsUpd, UsbConfig);

+

+  //

+  // I2C

+  //

+  for (Index = 0; Index < 8; Index++) {

+    UPDATE_POLICY (FspsUpd->FspsConfig.SerialIoI2cMode[Index], SerialIoConfig->I2cDeviceConfig[Index].Mode, 0);

+    UPDATE_POLICY (FspsUpd->FspsConfig.PchSerialIoI2cPadsTermination[Index], SerialIoConfig->I2cDeviceConfig[Index].PadTermination, 0);

+  }

+

+  UPDATE_POLICY (FspsUpd->FspsConfig.PchSerialIoI2cSdaPinMux[4],  SerialIoConfig->I2cDeviceConfig[4].PinMux.Sda,  GPIO_VER2_LP_MUXING_SERIALIO_I2C4_SDA_GPP_H8);

+  UPDATE_POLICY (FspsUpd->FspsConfig.PchSerialIoI2cSclPinMux[4],  SerialIoConfig->I2cDeviceConfig[4].PinMux.Scl,  GPIO_VER2_LP_MUXING_SERIALIO_I2C4_SCL_GPP_H9);

+

+  //

+  // Type C

+  //

+  for (Index = 0; Index < MAX_IOM_AUX_BIAS_COUNT; Index++) {

+    UPDATE_POLICY (FspsUpd->FspsConfig.IomTypeCPortPadCfg[(Index * 2)],     TcssConfig->IomConfig.IomAuxPortPad[Index].GpioPullN, mIomAuxNullTable[Index].GpioPullN);

+    UPDATE_POLICY (FspsUpd->FspsConfig.IomTypeCPortPadCfg[(Index * 2) + 1], TcssConfig->IomConfig.IomAuxPortPad[Index].GpioPullP, mIomAuxNullTable[Index].GpioPullP);

+  }

+

+  //

+  // Cnvi

+  //

+  UpdateCnviConfig (FspsUpd, CnviConfig);

+

+  return EFI_SUCCESS;

+}

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.c b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.c
new file mode 100644
index 0000000000..fc523e93d1
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.c
@@ -0,0 +1,308 @@
+/** @file

+  Instance of Fsp Policy Initialization Library.

+

+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>

+  SPDX-License-Identifier: BSD-2-Clause-Patent

+**/

+

+#include <PeiFspPolicyInitLib.h>

+#include <Library/FspWrapperApiLib.h>

+#include <Library/BaseMemoryLib.h>

+#include <Library/MemoryAllocationLib.h>

+#include <Ppi/FspmArchConfigPpi.h>

+

+VOID

+EFIAPI

+FspPolicyInitPreMem(

+  IN FSPM_UPD           *FspmUpdDataPtr

+);

+

+VOID *

+EFIAPI

+SiliconPolicyInitPreMem(

+  IN OUT VOID    *FspmUpd

+)

+{

+  DEBUG ((DEBUG_INFO, "FspmUpd - 0x%x\n", FspmUpd));

+  FspPolicyInitPreMem ((FSPM_UPD *) FspmUpd);

+  return FspmUpd;

+}

+

+/**

+  SiPreMemInstallPolicyReadyPpi installs SiPreMemPolicyReadyPpi.

+  While installed, RC assumes the Policy is ready and finalized. So please update and override

+  any setting before calling this function.

+

+  @retval EFI_SUCCESS            The policy is installed.

+  @retval EFI_OUT_OF_RESOURCES   Insufficient resources to create buffer

+**/

+EFI_STATUS

+EFIAPI

+SiPreMemInstallPolicyReadyPpi (

+  VOID

+  )

+{

+  EFI_STATUS             Status;

+  EFI_PEI_PPI_DESCRIPTOR *SiPolicyReadyPreMemPpiDesc;

+

+  SiPolicyReadyPreMemPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR));

+  if (SiPolicyReadyPreMemPpiDesc == NULL) {

+    ASSERT (FALSE);

+    return EFI_OUT_OF_RESOURCES;

+  }

+

+  SiPolicyReadyPreMemPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;

+  SiPolicyReadyPreMemPpiDesc->Guid  = &gSiPreMemPolicyReadyPpiGuid;

+  SiPolicyReadyPreMemPpiDesc->Ppi   = NULL;

+

+  //

+  // Install PreMem Silicon Policy Ready PPI

+  //

+  Status = PeiServicesInstallPpi (SiPolicyReadyPreMemPpiDesc);

+  ASSERT_EFI_ERROR (Status);

+  return Status;

+}

+

+RETURN_STATUS

+EFIAPI

+SiliconPolicyDonePreMem(

+  IN VOID *FspmUpd

+)

+{

+  EFI_STATUS                   Status;

+#if FixedPcdGet8(PcdFspModeSelection) == 0

+  FSPM_ARCH_CONFIG_PPI                  *FspmArchConfigPpi;

+  EFI_PEI_PPI_DESCRIPTOR                *FspmArchConfigPpiDesc;

+

+  FspmArchConfigPpi = (FSPM_ARCH_CONFIG_PPI *) AllocateZeroPool (sizeof (FSPM_ARCH_CONFIG_PPI));

+  if (FspmArchConfigPpi == NULL) {

+    ASSERT (FALSE);

+    return EFI_OUT_OF_RESOURCES;

+  }

+  FspmArchConfigPpi->Revision            = 1;

+  FspmArchConfigPpi->NvsBufferPtr        = NULL;

+  FspmArchConfigPpi->BootLoaderTolumSize = 0;

+

+  FspmArchConfigPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR));

+  if (FspmArchConfigPpiDesc == NULL) {

+    ASSERT (FALSE);

+    return EFI_OUT_OF_RESOURCES;

+  }

+  FspmArchConfigPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;

+  FspmArchConfigPpiDesc->Guid  = &gFspmArchConfigPpiGuid;

+  FspmArchConfigPpiDesc->Ppi   = FspmArchConfigPpi;

+  //

+  // Install FSP-M Arch Config PPI

+  //

+  Status = PeiServicesInstallPpi (FspmArchConfigPpiDesc);

+  ASSERT_EFI_ERROR (Status);

+#endif

+

+  //

+  // Install Policy Ready PPI

+  // While installed, RC assumes the Policy is ready and finalized. So please

+  // update and override any setting before calling this function.

+  //

+  Status = SiPreMemInstallPolicyReadyPpi ();

+  ASSERT_EFI_ERROR (Status);

+

+  DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Done in Pre-Memory\n"));

+

+  return Status;

+}

+

+/**

+  Performs FSP PEI Policy Pre-memory initialization.

+

+  @param[in] FspmUpdDataPtr       Pointer to FSPM UPD data.

+**/

+VOID

+EFIAPI

+FspPolicyInitPreMem (

+  IN FSPM_UPD           *FspmUpdDataPtr

+  )

+{

+  EFI_STATUS            Status;

+

+  //

+  // PCH Pei Fsp Policy Initialization

+  //

+  Status = PeiFspPchPolicyInitPreMem (FspmUpdDataPtr);

+  if (EFI_ERROR (Status)) {

+    DEBUG ((DEBUG_ERROR, "ERROR - PCH Pei Fsp Policy in Pre-Memory Initialization fail, Status = %r\n", Status));

+  }

+

+  //

+  // Cpu Pei Fsp Policy Initialization

+  //

+  Status = PeiFspCpuPolicyInitPreMem (FspmUpdDataPtr);

+  if (EFI_ERROR (Status)) {

+    DEBUG ((DEBUG_ERROR, "ERROR - CPU Pei Fsp Policy in Pre-Memory Initialization fail, Status = %r\n", Status));

+  }

+

+  //

+  // Security Pei Fsp Policy Initialization

+  //

+  Status = PeiFspSecurityPolicyInitPreMem (FspmUpdDataPtr);

+  if (EFI_ERROR (Status)) {

+    DEBUG ((DEBUG_ERROR, "ERROR - Security Pei Fsp Policy in Pre-Memory Initialization fail, Status = %r\n", Status));

+  }

+

+  //

+  // ME Pei Fsp Policy Initialization

+  //

+  Status = PeiFspMePolicyInitPreMem (FspmUpdDataPtr);

+  if (EFI_ERROR (Status)) {

+    DEBUG ((DEBUG_ERROR, "ERROR - ME Pei Fsp Policy in Pre-Memory Initialization fail, Status = %r\n", Status));

+  }

+

+  //

+  // SystemAgent Pei Fsp Policy Initialization

+  //

+  Status = PeiFspSaPolicyInitPreMem (FspmUpdDataPtr);

+  if (EFI_ERROR (Status)) {

+    DEBUG ((DEBUG_ERROR, "ERROR - SystemAgent Pei Fsp Policy in Pre-Memory Initialization fail, Status = %r\n", Status));

+  }

+

+  //

+  // Other Upd Initialization

+  //

+  Status = PeiFspMiscUpdInitPreMem (FspmUpdDataPtr);

+

+}

+

+/**

+  Performs FSP PEI Policy initialization.

+

+  @param[in][out] FspsUpd  Pointer UPD data region

+

+**/

+VOID

+EFIAPI

+FspPolicyInit (

+  IN OUT FSPS_UPD    *FspsUpd

+  )

+{

+  EFI_STATUS            Status;

+

+  //

+  // PCH Pei Fsp Policy Initialization

+  //

+  Status = PeiFspPchPolicyInit (FspsUpd);

+  if (EFI_ERROR (Status)) {

+    DEBUG ((DEBUG_ERROR, "ERROR - PCH Pei Fsp Policy iInitialization fail, Status = %r\n", Status));

+  }

+

+  //

+  // ME Pei Fsp Policy Initialization

+  //

+  Status = PeiFspMePolicyInit (FspsUpd);

+  if (EFI_ERROR (Status)) {

+    DEBUG ((DEBUG_ERROR, "ERROR - ME Pei Fsp Policy Initialization fail, Status = %r\n", Status));

+  }

+

+  //

+  // SystemAgent Pei Fsp Policy Initialization

+  //

+  Status = PeiFspSaPolicyInit (FspsUpd);

+  if (EFI_ERROR (Status)) {

+    DEBUG ((DEBUG_ERROR, "ERROR - SystemAgent Pei Fsp Policy Initialization fail, Status = %r\n", Status));

+  }

+

+  //

+  // Security Pei Fsp Policy Initialization

+  //

+  Status = PeiFspSecurityPolicyInit(FspsUpd);

+  if (EFI_ERROR(Status)) {

+    DEBUG((DEBUG_ERROR, "ERROR - Security Pei Fsp Policy Initialization fail, Status = %r\n", Status));

+  }

+

+}

+

+/**

+Performs silicon post-mem policy initialization.

+

+The meaning of Policy is defined by silicon code.

+It could be the raw data, a handle, a PPI, etc.

+

+The returned data must be used as input data for SiliconPolicyDonePostMem(),

+and SiliconPolicyUpdateLib.SiliconPolicyUpdatePostMem().

+

+1) In FSP path, the input Policy should be FspsUpd.

+Value of FspsUpd has been initialized by FSP binary default value.

+Only a subset of FspsUpd needs to be updated for different silicon sku.

+The return data is same FspsUpd.

+

+2) In non-FSP path, the input policy could be NULL.

+The return data is the initialized policy.

+

+@param[in, out] Policy       Pointer to policy.

+

+@return the initialized policy.

+**/

+VOID *

+EFIAPI

+SiliconPolicyInitPostMem(

+  IN OUT VOID    *FspsUpd

+)

+{

+  DEBUG ((DEBUG_INFO, "FspsUpd - 0x%x\n", FspsUpd));

+  FspPolicyInit ((FSPS_UPD *) FspsUpd);

+  return FspsUpd;

+}

+

+/**

+  SiInstallPolicyReadyPpi installs SiPolicyReadyPpi.

+  While installed, RC assumes the Policy is ready and finalized. So please update and override

+  any setting before calling this function.

+

+  @retval EFI_SUCCESS            The policy is installed.

+  @retval EFI_OUT_OF_RESOURCES   Insufficient resources to create buffer

+**/

+EFI_STATUS

+EFIAPI

+SiInstallPolicyReadyPpi (

+  VOID

+  )

+{

+  EFI_STATUS             Status;

+  EFI_PEI_PPI_DESCRIPTOR *SiPolicyReadyPpiDesc;

+

+  SiPolicyReadyPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR));

+  if (SiPolicyReadyPpiDesc == NULL) {

+    ASSERT (FALSE);

+    return EFI_OUT_OF_RESOURCES;

+  }

+

+  SiPolicyReadyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;

+  SiPolicyReadyPpiDesc->Guid  = &gSiPolicyReadyPpiGuid;

+  SiPolicyReadyPpiDesc->Ppi   = NULL;

+

+  //

+  // Install Silicon Policy Ready PPI

+  //

+  Status = PeiServicesInstallPpi (SiPolicyReadyPpiDesc);

+  ASSERT_EFI_ERROR (Status);

+  return Status;

+}

+

+/*

+The silicon post-mem policy is finalized.

+Silicon code can do initialization based upon the policy data.

+

+The input Policy must be returned by SiliconPolicyInitPostMem().

+

+@param[in] Policy       Pointer to policy.

+

+@retval EFI_SUCCESS The policy is handled consumed by silicon code.

+*/

+EFI_STATUS

+EFIAPI

+SiliconPolicyDonePostMem(

+  IN OUT VOID    *FspsUpd

+)

+{

+  SiInstallPolicyReadyPpi();

+  return EFI_SUCCESS;

+}

+

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.h b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.h
new file mode 100644
index 0000000000..cce0de0089
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.h
@@ -0,0 +1,187 @@
+/** @file

+  Internal header file for Fsp Policy Initialization Library.

+

+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>

+  SPDX-License-Identifier: BSD-2-Clause-Patent

+**/

+

+#ifndef _PEI_FSP_POLICY_INIT_LIB_H_

+#define _PEI_FSP_POLICY_INIT_LIB_H_

+

+#include <PiPei.h>

+

+#include <Library/DebugLib.h>

+#include <Library/PeiServicesLib.h>

+

+#include <FspEas.h>

+#include <FspmUpd.h>

+#include <FspsUpd.h>

+

+/**

+  Performs FSP PCH PEI Policy pre mem initialization.

+

+  @param[in][out]  FspmUpd             Pointer to FSP UPD Data.

+

+  @retval          EFI_SUCCESS         FSP UPD Data is updated.

+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.

+  @retval          Other               FSP UPD Data update process fail.

+**/

+EFI_STATUS

+EFIAPI

+PeiFspPchPolicyInitPreMem (

+  IN OUT FSPM_UPD    *FspmUpd

+  );

+

+/**

+  Performs FSP PCH PEI Policy initialization.

+

+  @param[in][out]  FspsUpd             Pointer to FSP UPD Data.

+

+  @retval          EFI_SUCCESS         FSP UPD Data is updated.

+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.

+  @retval          Other               FSP UPD Data update process fail.

+**/

+EFI_STATUS

+EFIAPI

+PeiFspPchPolicyInit (

+  IN OUT FSPS_UPD     *FspsUpd

+  );

+

+/**

+  Performs FSP CPU PEI Policy initialization.

+

+  @param[in][out]  FspmUpd             Pointer to FSP UPD Data.

+

+  @retval          EFI_SUCCESS         FSP UPD Data is updated.

+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.

+  @retval          Other               FSP UPD Data update process fail.

+**/

+EFI_STATUS

+EFIAPI

+PeiFspCpuPolicyInitPreMem (

+  IN OUT FSPM_UPD    *FspmUpd

+  );

+

+/**

+Performs FSP Security PEI Policy initialization.

+

+@param[in][out]  FspmUpd             Pointer to FSP UPD Data.

+

+@retval          EFI_SUCCESS         FSP UPD Data is updated.

+@retval          EFI_NOT_FOUND       Fail to locate required PPI.

+@retval          Other               FSP UPD Data update process fail.

+**/

+EFI_STATUS

+EFIAPI

+PeiFspSecurityPolicyInitPreMem(

+IN OUT FSPM_UPD    *FspmUpd

+);

+

+/**

+  Performs FSP ME PEI Policy pre mem initialization.

+

+  @param[in][out]  FspmUpd             Pointer to FSP UPD Data.

+

+  @retval          EFI_SUCCESS         FSP UPD Data is updated.

+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.

+  @retval          Other               FSP UPD Data update process fail.

+**/

+EFI_STATUS

+EFIAPI

+PeiFspMePolicyInitPreMem (

+  IN OUT FSPM_UPD    *FspmUpd

+  );

+

+/**

+  Performs FSP ME PEI Policy initialization.

+

+  @param[in][out]  FspsUpd             Pointer to FSP UPD Data.

+

+  @retval          EFI_SUCCESS         FSP UPD Data is updated.

+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.

+  @retval          Other               FSP UPD Data update process fail.

+**/

+EFI_STATUS

+EFIAPI

+PeiFspMePolicyInit (

+  IN OUT FSPS_UPD     *FspsUpd

+  );

+

+/**

+  Performs FSP SA PEI Policy initialization in pre-memory.

+

+  @param[in][out]  FspmUpd             Pointer to FSP UPD Data.

+

+  @retval          EFI_SUCCESS         FSP UPD Data is updated.

+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.

+  @retval          Other               FSP UPD Data update process fail.

+**/

+EFI_STATUS

+EFIAPI

+PeiFspSaPolicyInitPreMem (

+  IN OUT FSPM_UPD    *FspmUpd

+  );

+

+/**

+  Performs FSP SA PEI Policy initialization.

+

+  @param[in][out]  FspsUpd             Pointer to FSP UPD Data.

+

+  @retval          EFI_SUCCESS         FSP UPD Data is updated.

+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.

+  @retval          Other               FSP UPD Data update process fail.

+**/

+EFI_STATUS

+EFIAPI

+PeiFspSaPolicyInit (

+  IN OUT FSPS_UPD    *FspsUpd

+  );

+

+

+/**

+Performs FSP Security PEI Policy post memory initialization.

+

+@param[in][out]  FspsUpd             Pointer to FSP UPD Data.

+

+@retval          EFI_SUCCESS         FSP UPD Data is updated.

+@retval          EFI_NOT_FOUND       Fail to locate required PPI.

+@retval          Other               FSP UPD Data update process fail.

+**/

+EFI_STATUS

+EFIAPI

+PeiFspSecurityPolicyInit(

+IN OUT FSPS_UPD    *FspsUpd

+);

+

+/**

+  PeiGetSectionFromFv finds the file in FV and gets file Address and Size

+

+  @param[in] NameGuid              - File GUID

+  @param[out] Address              - Pointer to the File Address

+  @param[out] Size                 - Pointer to File Size

+

+  @retval EFI_SUCCESS                Successfull in reading the section from FV

+**/

+EFI_STATUS

+EFIAPI

+PeiGetSectionFromFv (

+  IN CONST  EFI_GUID        NameGuid,

+  OUT VOID                  **Address,

+  OUT UINT32               *Size

+  );

+

+/**

+  Performs FSP Misc UPD initialization.

+

+  @param[in][out]  FspmUpd             Pointer to FSPM_UPD Data.

+

+  @retval          EFI_SUCCESS         FSP UPD Data is updated.

+**/

+EFI_STATUS

+EFIAPI

+PeiFspMiscUpdInitPreMem (

+  IN OUT FSPM_UPD    *FspmUpd

+  );

+

+#endif // _PEI_FSP_POLICY_INIT_LIB_H_

+

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf
new file mode 100644
index 0000000000..9d85d855f5
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf
@@ -0,0 +1,183 @@
+## @file

+# Library functions for Fsp Policy Initialization Library.

+#

+#  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>

+#  SPDX-License-Identifier: BSD-2-Clause-Patent

+#

+##

+

+################################################################################

+#

+# Defines Section - statements that will be processed to create a Makefile.

+#

+################################################################################

+[Defines]

+  INF_VERSION                    = 0x00010005

+  BASE_NAME                      = PeiFspPolicyInitLib

+  FILE_GUID                      = 2CB87D67-D1A4-4CD3-8CD7-91A1FA1DF6E0

+  MODULE_TYPE                    = BASE

+  VERSION_STRING                 = 1.0

+  LIBRARY_CLASS                  = SiliconPolicyInitLib

+

+#

+# The following information is for reference only and not required by the build tools.

+#

+#  VALID_ARCHITECTURES           = IA32

+#

+

+################################################################################

+#

+# Sources Section - list of files that are required for the build to succeed.

+#

+################################################################################

+

+[Sources]

+  PeiFspPolicyInitLib.c

+  PeiFspPchPolicyInitLib.c

+  PeiFspCpuPolicyInitLib.c

+  PeiFspMePolicyInitLib.c

+  PeiFspSaPolicyInitLib.c

+  PeiFspSecurityPolicyInitLib.c

+  PeiFspMiscUpdInitLib.c

+

+################################################################################

+#

+# Package Dependency Section - list of Package files that are required for

+#                              this module.

+#

+################################################################################

+

+[Packages]

+  MdePkg/MdePkg.dec

+  MdeModulePkg/MdeModulePkg.dec

+  IntelFsp2Pkg/IntelFsp2Pkg.dec

+  TigerlakeSiliconPkg/SiPkg.dec

+  TigerLakeFspBinPkg/TigerLakeFspBinPkg.dec

+  TigerlakeOpenBoardPkg/OpenBoardPkg.dec

+  UefiCpuPkg/UefiCpuPkg.dec

+  IntelSiliconPkg/IntelSiliconPkg.dec

+  IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec

+  MinPlatformPkg/MinPlatformPkg.dec

+

+[LibraryClasses]

+  BaseMemoryLib

+  DebugLib

+  IoLib

+  PeiServicesLib

+  ConfigBlockLib

+  PcdLib

+  MemoryAllocationLib

+  PchInfoLib

+  FspWrapperApiLib

+  PeiLib

+  BmpSupportLib

+

+[Pcd]

+  gSiPkgTokenSpaceGuid.PcdTsegSize                                  ## CONSUMES

+

+  gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase                   ## CONSUMES

+  gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize                   ## CONSUMES

+  gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize                ## CONSUMES

+  gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize              ## CONSUMES

+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress             ## CONSUMES

+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress                ## CONSUMES

+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress             ## CONSUMES

+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress                ## CONSUMES

+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection               ## CONSUMES

+  # SA Misc Config

+  gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd                        ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment            ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdMrcSpdData                          ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize                      ## CONSUMES

+

+  # SPD Address Table

+  gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0            ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1            ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2            ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3            ## CONSUMES

+

+  # PCIe Clock Info

+  gBoardModuleTokenSpaceGuid.PcdPcieClock0                     ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdPcieClock1                     ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdPcieClock2                     ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdPcieClock3                     ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdPcieClock4                     ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdPcieClock5                     ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdPcieClock6                     ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdPcieClock7                     ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdPcieClock8                     ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdPcieClock9                     ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdPcieClock10                    ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdPcieClock11                    ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdPcieClock12                    ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdPcieClock13                    ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdPcieClock14                    ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdPcieClock15                    ## CONSUMES

+

+  # USB 2.0 Port Over Current Pin

+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0       ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1       ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2       ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3       ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4       ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5       ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6       ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7       ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8       ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9       ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10      ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11      ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12      ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13      ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort14      ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort15      ## CONSUMES

+

+  # USB 3.0 Port Over Current Pin

+  gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0       ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1       ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2       ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3       ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4       ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5       ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort6       ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort7       ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort8       ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort9       ## CONSUMES

+

+  gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid   ## CONSUMES

+

+  gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr    ## CONSUMES

+  gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr ## CONSUMES

+

+[Ppis]

+  gSiPolicyPpiGuid                        ## CONSUMES

+  gSiPreMemPolicyPpiGuid                  ## CONSUMES

+  gSiPreMemPolicyReadyPpiGuid             ## CONSUMES

+  gSiPolicyReadyPpiGuid                   ## CONSUMES

+  gFspmArchConfigPpiGuid                  ## SOMETIMES_PRODUCES

+

+[Guids]

+  gPcieRpPreMemConfigGuid                 ## CONSUMES

+  gPchGeneralPreMemConfigGuid             ## CONSUMES

+  gPcieRpPreMemConfigGuid                 ## CONSUMES

+  gSataConfigGuid                         ## CONSUMES

+  gHdAudioConfigGuid                      ## CONSUMES

+  gSataConfigGuid                         ## CONSUMES

+  gUsbConfigGuid                          ## CONSUMES

+  gSaMiscPeiPreMemConfigGuid              ## PRODUCES

+  gHostBridgePeiPreMemConfigGuid          ## CONSUMES

+  gSaMiscPeiConfigGuid                    ## PRODUCES

+  gMemoryConfigNoCrcGuid                  ## CONSUMES

+  gSaMiscPeiConfigGuid                    ## CONSUMES

+  gGraphicsPeiConfigGuid                  ## CONSUMES

+  gMePeiPreMemConfigGuid                  ## CONSUMES

+  gMePeiConfigGuid                        ## CONSUMES

+  gPchGeneralConfigGuid                   ## CONSUMES

+  gCpuConfigGuid                          ## CONSUMES

+  gCpuConfigLibPreMemConfigGuid           ## CONSUMES

+  gTcssPeiConfigGuid                      ## CONSUMES

+  gSerialIoConfigGuid                     ## CONSUMES

+  gCpuSecurityPreMemConfigGuid            ## CONSUMES

+  gTianoLogoGuid                          ## CONSUMES

+  gCnviConfigGuid                         ## CONSUMES

+  gHdAudioPreMemConfigGuid                ## CONSUMES

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspSaPolicyInitLib.c b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspSaPolicyInitLib.c
new file mode 100644
index 0000000000..8f426ddb8d
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspSaPolicyInitLib.c
@@ -0,0 +1,240 @@
+/** @file

+  Implementation of Fsp SA Policy Initialization.

+

+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>

+  SPDX-License-Identifier: BSD-2-Clause-Patent

+**/

+

+#include <PeiFspPolicyInitLib.h>

+

+#include <Ppi/SiPolicy.h>

+#include <MemoryConfig.h>

+#include <Library/IoLib.h>

+#include <Library/BaseMemoryLib.h>

+#include <Library/ConfigBlockLib.h>

+#include <Library/PcdLib.h>

+#include <Library/PeiLib.h>

+#include <IndustryStandard/Pci.h>

+#include <IndustryStandard/Bmp.h>

+#include <Ppi/FirmwareVolume.h>

+#include <Pi/PiFirmwareFile.h>

+#include <Pi/PiPeiCis.h>

+#include <Core/Pei/PeiMain.h>

+#include <Library/ConfigBlockLib.h>

+#include <PolicyUpdateMacro.h>

+#include <Pi/PiFirmwareFile.h>

+#include <Protocol/GraphicsOutput.h>

+#include <Library/BmpSupportLib.h>

+

+/**

+  Performs FSP SA PEI Policy initialization in pre-memory.

+

+  @param[in][out]  FspmUpd             Pointer to FSP UPD Data.

+

+  @retval          EFI_SUCCESS         FSP UPD Data is updated.

+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.

+  @retval          Other               FSP UPD Data update process fail.

+**/

+EFI_STATUS

+EFIAPI

+PeiFspSaPolicyInitPreMem (

+  IN OUT FSPM_UPD    *FspmUpd

+  )

+{

+  SA_MISC_PEI_PREMEM_CONFIG   *MiscPeiPreMemConfig;

+  HOST_BRIDGE_PREMEM_CONFIG   *HostBridgePreMemConfig;

+  MEMORY_CONFIG_NO_CRC        *MemConfigNoCrc;

+#if FixedPcdGet8(PcdFspModeSelection) == 0

+  EFI_STATUS                  Status;

+  SI_PREMEM_POLICY_PPI        *SiPreMemPolicyPpi;

+#endif

+

+  DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Pre Mem\n"));

+  MiscPeiPreMemConfig = NULL;

+  HostBridgePreMemConfig = NULL;

+  MemConfigNoCrc      = NULL;

+#if FixedPcdGet8(PcdFspModeSelection) == 0

+  //

+  // Locate SiPreMemPolicyPpi

+  //

+  SiPreMemPolicyPpi   = NULL;

+  Status = PeiServicesLocatePpi(

+             &gSiPreMemPolicyPpiGuid,

+             0,

+             NULL,

+             (VOID **) &SiPreMemPolicyPpi

+             );

+  ASSERT_EFI_ERROR (Status);

+  if ((Status == EFI_SUCCESS) && (SiPreMemPolicyPpi != NULL)) {

+    Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig);

+    ASSERT_EFI_ERROR (Status);

+    Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gHostBridgePeiPreMemConfigGuid, (VOID *) &HostBridgePreMemConfig);

+    ASSERT_EFI_ERROR(Status);

+    Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gMemoryConfigNoCrcGuid, (VOID *) &MemConfigNoCrc);

+    ASSERT_EFI_ERROR (Status);

+    ZeroMem ((VOID *) MemConfigNoCrc->SpdData->SpdData, sizeof (SPD_DATA_BUFFER));

+  }

+#endif

+

+  UPDATE_POLICY (FspmUpd->FspmConfig.SpdAddressTable[0], MiscPeiPreMemConfig->SpdAddressTable[0], PcdGet8 (PcdMrcSpdAddressTable0));

+  UPDATE_POLICY (FspmUpd->FspmConfig.SpdAddressTable[1], MiscPeiPreMemConfig->SpdAddressTable[1], PcdGet8 (PcdMrcSpdAddressTable1));

+  UPDATE_POLICY (FspmUpd->FspmConfig.SpdAddressTable[2], MiscPeiPreMemConfig->SpdAddressTable[2], PcdGet8 (PcdMrcSpdAddressTable2));

+  UPDATE_POLICY (FspmUpd->FspmConfig.SpdAddressTable[3], MiscPeiPreMemConfig->SpdAddressTable[3], PcdGet8 (PcdMrcSpdAddressTable3));

+

+  if (PcdGet32 (PcdMrcSpdData)) {

+    DEBUG((DEBUG_INFO, "PcdMrcSpdData != NULL, MemConfigNoCrc->SpdData\n"));

+    COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr000, (VOID *)MemConfigNoCrc->SpdData->SpdData[0][0][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16(PcdMrcSpdDataSize));

+    COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr010, (VOID *)MemConfigNoCrc->SpdData->SpdData[0][1][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16(PcdMrcSpdDataSize));

+    COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr020, (VOID *)MemConfigNoCrc->SpdData->SpdData[0][2][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16(PcdMrcSpdDataSize));

+    COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr030, (VOID *)MemConfigNoCrc->SpdData->SpdData[0][3][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16(PcdMrcSpdDataSize));

+    COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr100, (VOID *)MemConfigNoCrc->SpdData->SpdData[1][0][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16(PcdMrcSpdDataSize));

+    COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr110, (VOID *)MemConfigNoCrc->SpdData->SpdData[1][1][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16(PcdMrcSpdDataSize));

+    COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr120, (VOID *)MemConfigNoCrc->SpdData->SpdData[1][2][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16(PcdMrcSpdDataSize));

+    COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr130, (VOID *)MemConfigNoCrc->SpdData->SpdData[1][3][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16(PcdMrcSpdDataSize));

+  }

+  UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.TsegSize,           MiscPeiPreMemConfig->TsegSize,           PcdGet32 (PcdTsegSize));

+  UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.UserBd,             MiscPeiPreMemConfig->UserBd,             PcdGet8 (PcdSaMiscUserBd));

+  UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.MmioSizeAdjustment, HostBridgePreMemConfig->MmioSizeAdjustment, PcdGet16 (PcdSaMiscMmioSizeAdjustment));

+

+  return EFI_SUCCESS;

+}

+

+

+/**

+  Performs FSP SA PEI Policy initialization.

+

+  @param[in][out]  FspsUpd             Pointer to FSP UPD Data.

+

+  @retval          EFI_SUCCESS         FSP UPD Data is updated.

+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.

+  @retval          Other               FSP UPD Data update process fail.

+**/

+EFI_STATUS

+EFIAPI

+UpdateGraphics(

+    IN OUT FSPS_UPD *FspsUpd,

+    GRAPHICS_PEI_CONFIG *GtConfig

+  )

+{

+  EFI_STATUS                      Status;

+  VOID                            *Buffer;

+  UINT32                          Size;

+  EFI_GRAPHICS_OUTPUT_BLT_PIXEL   *Blt;

+  UINTN                           BltSize;

+  UINTN                           Height;

+  UINTN                           Width;

+

+  DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n"));

+  UPDATE_POLICY (FspsUpd->FspsConfig.PeiGraphicsPeimInit, GtConfig->PeiGraphicsPeimInit, 1);

+

+  Size = 0;

+  Buffer = NULL;

+  PeiGetSectionFromAnyFv(PcdGetPtr(PcdIntelGraphicsVbtFileGuid), EFI_SECTION_RAW, 0, &Buffer, &Size);

+  DEBUG((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromAnyFv is 0x%x\n", Buffer));

+  DEBUG((DEBUG_INFO, "Vbt Size from PeiGetSectionFromAnyFv is 0x%x\n", Size));

+#if FixedPcdGet8(PcdFspModeSelection) == 1

+  FspsUpd->FspsConfig.GraphicsConfigPtr = (UINT32)(UINTN)Buffer;

+#else

+  GtConfig->GraphicsConfigPtr = Buffer;

+#endif

+

+  Size = 0;

+  Buffer = NULL;

+  PeiGetSectionFromAnyFv(&gTianoLogoGuid, EFI_SECTION_RAW, 0, &Buffer, &Size);

+  DEBUG((DEBUG_INFO, "LogoPtr from PeiGetSectionFromAnyFv is 0x%x\n", Buffer));

+  DEBUG((DEBUG_INFO, "LogoSize from PeiGetSectionFromAnyFv is 0x%x\n", Size));

+#if FixedPcdGet8(PcdFspModeSelection) == 1

+  FspsUpd->FspsConfig.LogoPtr = (UINT32)Buffer;

+  FspsUpd->FspsConfig.LogoSize = Size;

+#else

+  GtConfig->LogoPtr = Buffer;

+  GtConfig->LogoSize = Size;

+#endif

+

+  if (Buffer != NULL) {

+    Blt = NULL;

+    Status = TranslateBmpToGopBlt (

+              Buffer,

+              Size,

+              &Blt,

+              &BltSize,

+              &Height,

+              &Width

+              );

+    if (EFI_ERROR (Status)) {

+        DEBUG ((DEBUG_ERROR, "TranslateBmpToGopBlt, Status = %r\n", Status));

+        ASSERT_EFI_ERROR (Status);

+        return Status;

+    }

+

+    UPDATE_POLICY(FspsUpd->FspsConfig.BltBufferSize,  GtConfig->BltBufferSize, BltSize);

+    UPDATE_POLICY(FspsUpd->FspsConfig.LogoPixelWidth,  GtConfig->LogoPixelWidth, Width);

+    UPDATE_POLICY(FspsUpd->FspsConfig.LogoPixelHeight,  GtConfig->LogoPixelHeight, Height);

+#if FixedPcdGet8(PcdFspModeSelection) == 1

+    FspsUpd->FspsConfig.BltBufferAddress  = (UINT32) Blt;

+#else

+    GtConfig->BltBufferAddress = (VOID *) Blt;

+#endif

+  }

+

+  return EFI_SUCCESS;

+}

+

+/**

+  Performs FSP SA PEI Policy initialization.

+

+  @param[in][out]  FspsUpd             Pointer to FSP UPD Data.

+

+  @retval          EFI_SUCCESS         FSP UPD Data is updated.

+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.

+  @retval          Other               FSP UPD Data update process fail.

+**/

+EFI_STATUS

+EFIAPI

+PeiFspSaPolicyInit (

+  IN OUT FSPS_UPD    *FspsUpd

+  )

+{

+#if FixedPcdGet8(PcdFspModeSelection) == 0

+  EFI_STATUS                Status;

+  SI_POLICY_PPI             *SiPolicyPpi;

+#endif

+  SA_MISC_PEI_CONFIG        *MiscPeiConfig;

+  GRAPHICS_PEI_CONFIG       *GtConfig;

+

+  MiscPeiConfig = NULL;

+  GtConfig      = NULL;

+

+#if FixedPcdGet8(PcdFspModeSelection) == 0

+  //

+  // Locate SiPolicyPpi

+  //

+  SiPolicyPpi = NULL;

+  Status = PeiServicesLocatePpi(

+             &gSiPolicyPpiGuid,

+             0,

+             NULL,

+             (VOID **)&SiPolicyPpi

+             );

+  if ((Status == EFI_SUCCESS) && (SiPolicyPpi != NULL)) {

+    MiscPeiConfig = NULL;

+    Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gSaMiscPeiConfigGuid, (VOID *) &MiscPeiConfig);

+    ASSERT_EFI_ERROR (Status);

+

+    GtConfig = NULL;

+    Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gGraphicsPeiConfigGuid, (VOID *) &GtConfig);

+    ASSERT_EFI_ERROR (Status);

+

+  }

+#endif

+

+  DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Wrapper UpdatePeiSaPolicy\n"));

+

+  //

+  // Update UPD: VBT & LogoPtr

+  //

+  UpdateGraphics(FspsUpd, GtConfig);

+

+  return EFI_SUCCESS;

+}

+

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspSecurityPolicyInitLib.c b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspSecurityPolicyInitLib.c
new file mode 100644
index 0000000000..91a60a6bd3
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspSecurityPolicyInitLib.c
@@ -0,0 +1,49 @@
+/** @file

+  Implementation of Fsp Security Policy Initialization.

+

+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>

+  SPDX-License-Identifier: BSD-2-Clause-Patent

+**/

+

+#include <PeiFspPolicyInitLib.h>

+#include <Library/PeiServicesLib.h>

+#include <Ppi/SiPolicy.h>

+

+/**

+  Performs FSP Security PEI Policy initialization.

+

+  @param[in][out]  FspmUpd             Pointer to FSP UPD Data.

+

+  @retval          EFI_SUCCESS         FSP UPD Data is updated.

+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.

+  @retval          Other               FSP UPD Data update process fail.

+**/

+EFI_STATUS

+EFIAPI

+PeiFspSecurityPolicyInitPreMem (

+  IN OUT FSPM_UPD    *FspmUpd

+  )

+{

+  DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SecurityPolicy Pre-Mem End\n"));

+

+  return EFI_SUCCESS;

+}

+

+/**

+  Performs FSP Security PEI Policy post memory initialization.

+

+  @param[in][out]  FspsUpd             Pointer to FSP UPD Data.

+

+  @retval          EFI_SUCCESS         FSP UPD Data is updated.

+  @retval          EFI_NOT_FOUND       Fail to locate required PPI.

+  @retval          Other               FSP UPD Data update process fail.

+**/

+EFI_STATUS

+EFIAPI

+PeiFspSecurityPolicyInit (

+  IN OUT FSPS_UPD    *FspsUpd

+  )

+{

+  return EFI_SUCCESS;

+}

+

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiDefaultPolicyInitLib/PeiSiDefaultPolicyInitLib.c b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiDefaultPolicyInitLib/PeiSiDefaultPolicyInitLib.c
new file mode 100644
index 0000000000..b864753258
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiDefaultPolicyInitLib/PeiSiDefaultPolicyInitLib.c
@@ -0,0 +1,39 @@
+/** @file

+  Instance of Fsp Policy Initialization Library.

+

+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>

+  SPDX-License-Identifier: BSD-2-Clause-Patent

+**/

+

+#include <PiPei.h>

+#include <Library/DebugLib.h>

+#include <Library/PeiServicesLib.h>

+#include <Ppi/PeiSiDefaultPolicy.h>

+

+EFI_STATUS

+EFIAPI

+PeiSiDefaultPolicyInitLibConstructor (

+  VOID

+  )

+{

+  EFI_STATUS Status;

+  PEI_SI_DEFAULT_POLICY_INIT_PPI *PeiSiDefaultPolicyInitPpi;

+

+  //

+  // Locate Policy init PPI to install default silicon policy

+  //

+  Status = PeiServicesLocatePpi (

+              &gSiDefaultPolicyInitPpiGuid,

+              0,

+              NULL,

+              (VOID **) &PeiSiDefaultPolicyInitPpi

+              );

+  ASSERT_EFI_ERROR (Status);

+  if (PeiSiDefaultPolicyInitPpi == NULL) {

+    return Status;

+  }

+  Status = PeiSiDefaultPolicyInitPpi->PeiPolicyInit ();

+  ASSERT_EFI_ERROR (Status);

+

+  return Status;

+}

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiDefaultPolicyInitLib/PeiSiDefaultPolicyInitLib.inf b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiDefaultPolicyInitLib/PeiSiDefaultPolicyInitLib.inf
new file mode 100644
index 0000000000..bcad97c267
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiDefaultPolicyInitLib/PeiSiDefaultPolicyInitLib.inf
@@ -0,0 +1,38 @@
+## @file

+# Library functions for Fsp Policy Initialization Library.

+#

+#  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>

+#  SPDX-License-Identifier: BSD-2-Clause-Patent

+#

+##

+

+################################################################################

+#

+# Defines Section - statements that will be processed to create a Makefile.

+#

+################################################################################

+[Defines]

+  INF_VERSION                    = 0x00010005

+  BASE_NAME                      = PeiSiDefaultPolicyInitLib

+  FILE_GUID                      = ADA1D87B-6891-453C-A0DB-92D4CFD46693

+  MODULE_TYPE                    = BASE

+  VERSION_STRING                 = 1.0

+  LIBRARY_CLASS                  = NULL

+  CONSTRUCTOR                    = PeiSiDefaultPolicyInitLibConstructor

+

+[Packages]

+  MdePkg/MdePkg.dec

+  TigerlakeSiliconPkg/SiPkg.dec

+

+[Sources]

+  PeiSiDefaultPolicyInitLib.c

+

+[LibraryClasses]

+  PeiServicesLib

+  DebugLib

+

+[Ppis]

+  gSiDefaultPolicyInitPpiGuid             ## CONSUMES

+

+[Depex]

+  gSiDefaultPolicyInitPpiGuid

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiPreMemDefaultPolicyInitLib/PeiSiPreMemDefaultPolicyInitLib.c b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiPreMemDefaultPolicyInitLib/PeiSiPreMemDefaultPolicyInitLib.c
new file mode 100644
index 0000000000..f0eb3f3f14
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiPreMemDefaultPolicyInitLib/PeiSiPreMemDefaultPolicyInitLib.c
@@ -0,0 +1,40 @@
+/** @file

+  Instance of Fsp Policy Initialization Library.

+

+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>

+  SPDX-License-Identifier: BSD-2-Clause-Patent

+**/

+

+#include <PiPei.h>

+#include <Library/DebugLib.h>

+#include <Library/PeiServicesLib.h>

+#include <Ppi/PeiPreMemSiDefaultPolicy.h>

+

+EFI_STATUS

+EFIAPI

+PeiSiPreMemDefaultPolicyInitLibConstructor (

+  VOID

+  )

+{

+  EFI_STATUS Status;

+  PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI *PeiPreMemSiDefaultPolicyInitPpi;

+

+  //

+  // Locate Policy init PPI to install default silicon policy

+  //

+  Status = PeiServicesLocatePpi (

+              &gSiPreMemDefaultPolicyInitPpiGuid,

+              0,

+              NULL,

+              (VOID **) &PeiPreMemSiDefaultPolicyInitPpi

+              );

+  ASSERT_EFI_ERROR (Status);

+  if (PeiPreMemSiDefaultPolicyInitPpi == NULL) {

+    return Status;

+  }

+  DEBUG ((DEBUG_INFO, "PeiPreMemSiDefaultPolicyInitPpi->PeiPreMemPolicyInit ()\n", Status));

+  Status = PeiPreMemSiDefaultPolicyInitPpi->PeiPreMemPolicyInit ();

+  ASSERT_EFI_ERROR (Status);

+

+  return Status;

+}

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiPreMemDefaultPolicyInitLib/PeiSiPreMemDefaultPolicyInitLib.inf b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiPreMemDefaultPolicyInitLib/PeiSiPreMemDefaultPolicyInitLib.inf
new file mode 100644
index 0000000000..c118d7fe2c
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiPreMemDefaultPolicyInitLib/PeiSiPreMemDefaultPolicyInitLib.inf
@@ -0,0 +1,38 @@
+## @file

+# Library functions for Fsp Policy Initialization Library.

+#

+#  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>

+#  SPDX-License-Identifier: BSD-2-Clause-Patent

+#

+##

+

+################################################################################

+#

+# Defines Section - statements that will be processed to create a Makefile.

+#

+################################################################################

+[Defines]

+  INF_VERSION                    = 0x00010005

+  BASE_NAME                      = PeiSiPreMemDefaultPolicyInitLib

+  FILE_GUID                      = F13311AD-9C5C-4212-AB02-9D0435B3FCF1

+  MODULE_TYPE                    = BASE

+  VERSION_STRING                 = 1.0

+  LIBRARY_CLASS                  = NULL

+  CONSTRUCTOR                    = PeiSiPreMemDefaultPolicyInitLibConstructor

+

+[Packages]

+  MdePkg/MdePkg.dec

+  TigerlakeSiliconPkg/SiPkg.dec

+

+[Sources]

+  PeiSiPreMemDefaultPolicyInitLib.c

+

+[LibraryClasses]

+  PeiServicesLib

+  DebugLib

+

+[Ppis]

+  gSiPreMemDefaultPolicyInitPpiGuid       ## CONSUMES

+

+[Depex]

+  gSiPreMemDefaultPolicyInitPpiGuid

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c b/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c
new file mode 100644
index 0000000000..6209e50450
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c
@@ -0,0 +1,391 @@
+/** @file

+  Platform Hook Library instances

+

+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>

+  SPDX-License-Identifier: BSD-2-Clause-Patent

+**/

+

+#include <Base.h>

+#include <Uefi/UefiBaseType.h>

+#include <Library/PlatformHookLib.h>

+#include <Library/BaseLib.h>

+#include <Library/IoLib.h>

+#include <Library/PciSegmentLib.h>

+#include <Library/PcdLib.h>

+#include <Library/MmPciLib.h>

+#include <Library/PchCycleDecodingLib.h>

+#include <Register/PchRegs.h>

+#include <Register/PchRegsLpc.h>

+#include <Library/SaPlatformLib.h>

+#include <Library/PchPciBdfLib.h>

+

+#define COM1_BASE                                 0x3f8

+#define COM2_BASE                                 0x2f8

+

+#define SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS   0x0690

+

+#define LPC_SIO_INDEX_DEFAULT_PORT_2              0x2E

+#define LPC_SIO_DATA_DEFAULT_PORT_2               0x2F

+#define LPC_SIO_GPIO_REGISTER_ADDRESS_2           0x0A20

+

+#define LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT       0x2E

+#define LEGACY_DAUGHTER_CARD_SIO_DATA_PORT        0x2F

+#define LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT     0x4E

+#define LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT      0x4F

+

+#define IT8628_ENTER_CONFIG_WRITE_SEQ_0           0x87

+#define IT8628_ENTER_CONFIG_WRITE_SEQ_1           0x01

+#define IT8628_ENTER_CONFIG_WRITE_SEQ_2           0x55

+#define IT8628_ENTER_CONFIG_WRITE_SEQ_3           0x55

+#define IT8628_EXIT_CONFIG                        0x2

+#define IT8628_CHIPID_BYTE1                       0x86

+#define IT8628_CHIPID_BYTE2                       0x28

+

+typedef struct {

+  UINT8 Register;

+  UINT8 Value;

+} EFI_SIO_TABLE;

+

+

+GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableWpcn381u[] = {

+  {0x29, 0x0A0},                  // Enable super I/O clock and set to 48MHz

+  {0x22, 0x003},                  //

+  {0x07, 0x003},                  // Select UART0 device

+  {0x60, (COM1_BASE >> 8)},       // Set Base Address MSB

+  {0x61, (COM1_BASE & 0x00FF)},   // Set Base Address LSB

+  {0x70, 0x004},                  // Set to IRQ4

+  {0x30, 0x001},                  // Enable it with Activation bit

+  {0x07, 0x002},                  // Select UART1 device

+  {0x60, (COM2_BASE >> 8)},       // Set Base Address MSB

+  {0x61, (COM2_BASE & 0x00FF)},   // Set Base Address LSB

+  {0x70, 0x003},                  // Set to IRQ3

+  {0x30, 0x001},                  // Enable it with Activation bit

+  {0x07, 0x007},                  // Select GPIO device

+  {0x60, (LPC_SIO_GPIO_REGISTER_ADDRESS_2 >> 8)},      // Set Base Address MSB

+  {0x61, (LPC_SIO_GPIO_REGISTER_ADDRESS_2 & 0x00FF)},  // Set Base Address LSB

+  {0x30, 0x001},                  // Enable it with Activation bit

+  {0x21, 0x001},                  // Global Device Enable

+  {0x26, 0x000}                   // Fast Enable UART 0 & 1 as their enable & activation bit

+};

+

+//

+// IT8628

+//

+GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioIt8628TableSerialPort[] = {

+  {0x023, 0x09}, // Clock Selection register

+  {0x007, 0x01}, // Com1 Logical Device Number select

+  {0x061, 0xF8}, // Serial Port 1 Base Address MSB Register

+  {0x060, 0x03}, // Serial Port 1 Base Address LSB Register

+  {0x070, 0x04}, // Serial Port 1 Interrupt Level Select

+  {0x030, 0x01}, // Serial Port 1 Activate

+  {0x007, 0x02}, // Com1 Logical Device Number select

+  {0x061, 0xF8}, // Serial Port 2 Base Address MSB Register

+  {0x060, 0x02}, // Serial Port 2 Base Address MSB Register

+  {0x070, 0x03}, // Serial Port 2 Interrupt Level Select

+  {0x030, 0x01}  // Serial Port 2 Activate

+

+};

+

+GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableWinbond_x374[] = {

+  {0x07, 0x03},                   // Select UART0 device

+  {0x60, (COM1_BASE >> 8)},       // Set Base Address MSB

+  {0x61, (COM1_BASE & 0x00FF)},   // Set Base Address LSB

+  {0x70, 0x04},                   // Set to IRQ4

+  {0x30, 0x01}                    // Enable it with Activation bit

+};

+

+/**

+  Detect if a National 393 SIO is docked. If yes, enable the docked SIO

+  and its serial port, and disable the onboard serial port.

+

+  @retval EFI_SUCCESS     Operations performed successfully.

+**/

+STATIC

+VOID

+CheckNationalSio (

+  VOID

+  )

+{

+  UINT8           Data8;

+

+  //

+  // Pc87393 access is through either (0x2e, 0x2f) or (0x4e, 0x4f).

+  // We use (0x2e, 0x2f) which is determined by BADD default strapping

+  //

+

+  //

+  // Read the Pc87393 signature

+  //

+  IoWrite8 (0x2e, 0x20);

+  Data8 = IoRead8 (0x2f);

+

+  if (Data8 == 0xea) {

+    //

+    // Signature matches - National PC87393 SIO is docked

+    //

+

+    //

+    // Enlarge the LPC decode scope to accommodate the Docking LPC Switch

+    // Register (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS is allocated at

+    // SIO_BASE_ADDRESS + 0x10)

+    //

+    PchLpcGenIoRangeSet ((FixedPcdGet16 (PcdSioBaseAddress) & (UINT16)~0x7F), 0x20);

+

+    //

+    // Enable port switch

+    //

+    IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x06);

+

+    //

+    // Turn on docking power

+    //

+    IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x8c);

+

+    IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x9c);

+

+    IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0xBc);

+

+    //

+    // Enable port switch

+    //

+    IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x7);

+

+    //

+    // GPIO setting

+    //

+    IoWrite8 (0x2e, 0x24);

+    IoWrite8 (0x2f, 0x29);

+

+    //

+    // Enable chip clock

+    //

+    IoWrite8 (0x2e, 0x29);

+    IoWrite8 (0x2f, 0x1e);

+

+

+    //

+    // Enable serial port

+    //

+

+    //

+    // Select com1

+    //

+    IoWrite8 (0x2e, 0x7);

+    IoWrite8 (0x2f, 0x3);

+

+    //

+    // Base address: 0x3f8

+    //

+    IoWrite8 (0x2e, 0x60);

+    IoWrite8 (0x2f, 0x03);

+    IoWrite8 (0x2e, 0x61);

+    IoWrite8 (0x2f, 0xf8);

+

+    //

+    // Interrupt: 4

+    //

+    IoWrite8 (0x2e, 0x70);

+    IoWrite8 (0x2f, 0x04);

+

+    //

+    // Enable bank selection

+    //

+    IoWrite8 (0x2e, 0xf0);

+    IoWrite8 (0x2f, 0x82);

+

+    //

+    // Activate

+    //

+    IoWrite8 (0x2e, 0x30);

+    IoWrite8 (0x2f, 0x01);

+

+    //

+    // Disable onboard serial port

+    //

+    IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0x55);

+

+    //

+    // Power Down UARTs

+    //

+    IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x2);

+    IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x00);

+

+    //

+    // Dissable COM1 decode

+    //

+    IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x24);

+    IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0);

+

+    //

+    // Disable COM2 decode

+    //

+    IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x25);

+    IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0);

+

+    //

+    // Disable interrupt

+    //

+    IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x28);

+    IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x0);

+

+    IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA);

+

+    //

+    // Enable floppy

+    //

+

+    //

+    // Select floppy

+    //

+    IoWrite8 (0x2e, 0x7);

+    IoWrite8 (0x2f, 0x0);

+

+    //

+    // Base address: 0x3f0

+    //

+    IoWrite8 (0x2e, 0x60);

+    IoWrite8 (0x2f, 0x03);

+    IoWrite8 (0x2e, 0x61);

+    IoWrite8 (0x2f, 0xf0);

+

+    //

+    // Interrupt: 6

+    //

+    IoWrite8 (0x2e, 0x70);

+    IoWrite8 (0x2f, 0x06);

+

+    //

+    // DMA 2

+    //

+    IoWrite8 (0x2e, 0x74);

+    IoWrite8 (0x2f, 0x02);

+

+    //

+    // Activate

+    //

+    IoWrite8 (0x2e, 0x30);

+    IoWrite8 (0x2f, 0x01);

+

+  } else {

+

+    //

+    // No National pc87393 SIO is docked, turn off dock power and

+    // disable port switch

+    //

+    // IoWrite8 (SIO_BASE_ADDRESS + 0x0E, 0xbf);

+    // IoWrite8 (0x690, 0);

+

+    //

+    // If no National pc87393, just return

+    //

+    return ;

+  }

+}

+

+/**

+Check whether the IT8628 SIO present on LPC. If yes, enable its serial ports

+

+@retval EFI_SUCCESS     Operations performed successfully.

+**/

+STATIC

+VOID

+It8628SioSerialPortInit (

+  VOID

+  )

+{

+  UINT8   ChipId0              = 0;

+  UINT8   ChipId1              = 0;

+  UINT16  LpcIoDecondeRangeSet = 0;

+  UINT16  LpcIoDecoodeSet      = 0;

+  UINT8   Index;

+  UINTN   LpcBaseAddr;

+

+

+

+  //

+  // Enable I/O decoding for COM1 (3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2Eh/2Fh.

+  //

+  LpcBaseAddr = MmPciBase (

+                  DEFAULT_PCI_BUS_NUMBER_PCH,

+                  LpcDevNumber (),

+                  LpcFuncNumber ()

+                  );

+

+  LpcIoDecondeRangeSet = (UINT16) MmioRead16 (LpcBaseAddr + R_LPC_CFG_IOD);

+  LpcIoDecoodeSet = (UINT16) MmioRead16 (LpcBaseAddr + R_LPC_CFG_IOE);

+  MmioWrite16 ((LpcBaseAddr + R_LPC_CFG_IOD), (LpcIoDecondeRangeSet | ((V_LPC_CFG_IOD_COMB_2F8 << 4) | V_LPC_CFG_IOD_COMA_3F8)));

+  MmioWrite16 ((LpcBaseAddr + R_LPC_CFG_IOE), (LpcIoDecoodeSet | (B_LPC_CFG_IOE_SE | B_LPC_CFG_IOE_CBE | B_LPC_CFG_IOE_CAE|B_LPC_CFG_IOE_KE)));

+

+

+  //

+  // Enter MB PnP Mode

+  //

+  IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, IT8628_ENTER_CONFIG_WRITE_SEQ_0);

+  IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, IT8628_ENTER_CONFIG_WRITE_SEQ_1);

+  IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, IT8628_ENTER_CONFIG_WRITE_SEQ_2);

+  IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, IT8628_ENTER_CONFIG_WRITE_SEQ_3);

+

+  //

+  // Read Chip Id of SIO IT8628 (registers 0x20 and 0x21)

+  //

+  IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x20);

+  ChipId0 = IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2);

+

+  IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x21);

+  ChipId1 = IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2);

+

+  //

+  // Enable Serial Port 1, Port 2

+  //

+  if ((ChipId0 == IT8628_CHIPID_BYTE1) && (ChipId1 == IT8628_CHIPID_BYTE2)) {

+    for (Index = 0; Index < sizeof (mSioIt8628TableSerialPort) / sizeof (EFI_SIO_TABLE); Index++) {

+      IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, mSioIt8628TableSerialPort[Index].Register);

+      IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, mSioIt8628TableSerialPort[Index].Value);

+    }

+  }

+

+  //

+  // Exit MB PnP Mode

+  //

+  IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, IT8628_EXIT_CONFIG);

+  IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, IT8628_EXIT_CONFIG);

+

+  return;

+}

+

+/**

+  Performs platform specific initialization required for the CPU to access

+  the hardware associated with a SerialPortLib instance.  This function does

+  not initialize the serial port hardware itself.  Instead, it initializes

+  hardware devices that are required for the CPU to access the serial port

+  hardware.  This function may be called more than once.

+

+  @retval RETURN_SUCCESS       The platform specific initialization succeeded.

+  @retval RETURN_DEVICE_ERROR  The platform specific initialization could not be completed.

+

+**/

+RETURN_STATUS

+EFIAPI

+PlatformHookSerialPortInitialize (

+  VOID

+  )

+{

+  UINT16  IndexPort;

+  UINT16  DataPort;

+  UINT8   Index;

+

+  IndexPort = 0;

+  DataPort = 0;

+  Index = 0;

+

+  //

+  // Enable I/O decoding for COM1(3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2Eh/2Fh, 4Eh/4Fh, 60h/64Fh and 62h/66h.

+  //

+  PchLpcIoDecodeRangesSet (PcdGet16 (PcdLpcIoDecodeRange));

+  PchLpcIoEnableDecodingSet (PcdGet16 (PchLpcIoEnableDecoding));

+

+  // Configure Sio IT8628

+  It8628SioSerialPortInit ();

+

+  return RETURN_SUCCESS;

+}

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.inf b/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.inf
new file mode 100644
index 0000000000..cf01780101
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.inf
@@ -0,0 +1,51 @@
+## @file

+# Platform Hook Library instance for Tigerlake Mobile/Desktop CRB.

+#

+#  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>

+#  SPDX-License-Identifier: BSD-2-Clause-Patent

+#

+##

+

+[Defines]

+  INF_VERSION                    = 0x00010017

+  BASE_NAME                      = BasePlatformHookLib

+  FILE_GUID                      = E22ADCC6-ED90-4A90-9837-C8E7FF9E963D

+  VERSION_STRING                 = 1.0

+  MODULE_TYPE                    = BASE

+  LIBRARY_CLASS                  = PlatformHookLib

+#

+# The following information is for reference only and not required by the build tools.

+#

+# VALID_ARCHITECTURES = IA32 X64 IPF EBC

+#

+

+[LibraryClasses]

+  BaseLib

+  IoLib

+  PciSegmentLib

+  MmPciLib

+  PciLib

+  PchCycleDecodingLib

+  SaPlatformLib

+  PchPciBdfLib

+

+[Packages]

+  MdePkg/MdePkg.dec

+  MdeModulePkg/MdeModulePkg.dec

+  MinPlatformPkg/MinPlatformPkg.dec

+  TigerlakeOpenBoardPkg/OpenBoardPkg.dec

+  TigerlakeSiliconPkg/SiPkg.dec

+

+[Pcd]

+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress            ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdLpcSioIndexPort                ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdLpcSioDataPort                 ## CONSUMES

+

+[FixedPcd]

+  gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort        ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdSioBaseAddress                 ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange               ## CONSUMES

+  gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding            ## CONSUMES

+

+[Sources]

+  BasePlatformHookLib.c

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf b/Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
new file mode 100644
index 0000000000..374f5ea52b
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
@@ -0,0 +1,49 @@
+## @file

+# SMM Library instance of Spi Flash Common Library Class

+#

+#  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>

+#  SPDX-License-Identifier: BSD-2-Clause-Patent

+#

+##

+

+[Defines]

+  INF_VERSION                    = 0x00010017

+  BASE_NAME                      = SmmSpiFlashCommonLib

+  FILE_GUID                      = 9632D96E-E849-4217-9217-DC500B8AAE47

+  VERSION_STRING                 = 1.0

+  MODULE_TYPE                    = DXE_SMM_DRIVER

+  LIBRARY_CLASS                  = SpiFlashCommonLib|DXE_SMM_DRIVER

+  CONSTRUCTOR                    = SmmSpiFlashCommonLibConstructor

+#

+# The following information is for reference only and not required by the build tools.

+#

+# VALID_ARCHITECTURES = IA32 X64

+#

+

+[LibraryClasses]

+  IoLib

+  MemoryAllocationLib

+  BaseLib

+  UefiLib

+  SmmServicesTableLib

+  BaseMemoryLib

+  DebugLib

+

+[Packages]

+  MdePkg/MdePkg.dec

+  MinPlatformPkg/MinPlatformPkg.dec

+  TigerlakeSiliconPkg/SiPkg.dec

+

+[Pcd]

+  gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress   ## CONSUMES

+  gSiPkgTokenSpaceGuid.PcdBiosSize              ## CONSUMES

+

+[Sources]

+  SpiFlashCommonSmmLib.c

+  SpiFlashCommon.c

+

+[Protocols]

+  gPchSmmSpiProtocolGuid                        ## CONSUMES

+

+[Depex.X64.DXE_SMM_DRIVER]

+  gPchSmmSpiProtocolGuid

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c b/Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c
new file mode 100644
index 0000000000..f86896dd1f
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c
@@ -0,0 +1,210 @@
+/** @file

+  Wrap EFI_SPI_PROTOCOL to provide some library level interfaces

+  for module use.

+

+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>

+  SPDX-License-Identifier: BSD-2-Clause-Patent

+**/

+

+#include <Library/SpiFlashCommonLib.h>

+#include <Library/IoLib.h>

+#include <Protocol/Spi.h>

+

+PCH_SPI_PROTOCOL       *mSpiProtocol;

+

+//

+// Variables for boottime and runtime usage.

+//

+UINTN mBiosAreaBaseAddress = 0;

+UINTN mBiosSize            = 0;

+UINTN mBiosOffset          = 0;

+

+/**

+  Enable block protection on the Serial Flash device.

+

+  @retval     EFI_SUCCESS       Opertion is successful.

+  @retval     EFI_DEVICE_ERROR  If there is any device errors.

+

+**/

+EFI_STATUS

+EFIAPI

+SpiFlashLock (

+  VOID

+  )

+{

+  return EFI_SUCCESS;

+}

+

+/**

+  Read NumBytes bytes of data from the address specified by

+  PAddress into Buffer.

+

+  @param[in]      Address       The starting physical address of the read.

+  @param[in,out]  NumBytes      On input, the number of bytes to read. On output, the number

+                                of bytes actually read.

+  @param[out]     Buffer        The destination data buffer for the read.

+

+  @retval         EFI_SUCCESS       Operation is successful.

+  @retval         EFI_DEVICE_ERROR  If there is any device errors.

+

+**/

+EFI_STATUS

+EFIAPI

+SpiFlashRead (

+  IN     UINTN                        Address,

+  IN OUT UINT32                       *NumBytes,

+     OUT UINT8                        *Buffer

+  )

+{

+  ASSERT ((NumBytes != NULL) && (Buffer != NULL));

+  if ((NumBytes == NULL) || (Buffer == NULL)) {

+    return EFI_INVALID_PARAMETER;

+  }

+

+  //

+  // This function is implemented specifically for those platforms

+  // at which the SPI device is memory mapped for read. So this

+  // function just do a memory copy for Spi Flash Read.

+  //

+  CopyMem (Buffer, (VOID *) Address, *NumBytes);

+

+  return EFI_SUCCESS;

+}

+

+/**

+  Write NumBytes bytes of data from Buffer to the address specified by

+  PAddresss.

+

+  @param[in]      Address         The starting physical address of the write.

+  @param[in,out]  NumBytes        On input, the number of bytes to write. On output,

+                                  the actual number of bytes written.

+  @param[in]      Buffer          The source data buffer for the write.

+

+  @retval         EFI_SUCCESS            Operation is successful.

+  @retval         EFI_DEVICE_ERROR       If there is any device errors.

+  @retval         EFI_INVALID_PARAMETER  Invalid parameter.

+

+**/

+EFI_STATUS

+EFIAPI

+SpiFlashWrite (

+  IN     UINTN                      Address,

+  IN OUT UINT32                     *NumBytes,

+  IN     UINT8                      *Buffer

+  )

+{

+  EFI_STATUS                Status;

+  UINTN                     Offset;

+  UINT32                    Length;

+  UINT32                    RemainingBytes;

+

+  ASSERT ((NumBytes != NULL) && (Buffer != NULL));

+  if ((NumBytes == NULL) || (Buffer == NULL)) {

+    return EFI_INVALID_PARAMETER;

+  }

+

+  ASSERT (Address >= mBiosAreaBaseAddress);

+  if (Address < mBiosAreaBaseAddress) {

+    return EFI_INVALID_PARAMETER;

+  }

+

+  Offset = Address - mBiosAreaBaseAddress;

+

+  ASSERT ((*NumBytes + Offset) <= mBiosSize);

+  if ((*NumBytes + Offset) > mBiosSize) {

+    return EFI_INVALID_PARAMETER;

+  }

+

+  Status = EFI_SUCCESS;

+  RemainingBytes = *NumBytes;

+

+

+  while (RemainingBytes > 0) {

+    if (RemainingBytes > SECTOR_SIZE_4KB) {

+      Length = SECTOR_SIZE_4KB;

+    } else {

+      Length = RemainingBytes;

+    }

+    Status = mSpiProtocol->FlashWrite (

+                             mSpiProtocol,

+                             FlashRegionBios,

+                             (UINT32) Offset,

+                             Length,

+                             Buffer

+                             );

+    if (EFI_ERROR (Status)) {

+      break;

+    }

+    RemainingBytes -= Length;

+    Offset += Length;

+    Buffer += Length;

+  }

+

+  //

+  // Actual number of bytes written

+  //

+  *NumBytes -= RemainingBytes;

+

+  return Status;

+}

+

+/**

+  Erase the block starting at Address.

+

+  @param[in]  Address         The starting physical address of the block to be erased.

+                              This library assume that caller garantee that the PAddress

+                              is at the starting address of this block.

+  @param[in]  NumBytes        On input, the number of bytes of the logical block to be erased.

+                              On output, the actual number of bytes erased.

+

+  @retval     EFI_SUCCESS.           Operation is successful.

+  @retval     EFI_DEVICE_ERROR       If there is any device errors.

+  @retval     EFI_INVALID_PARAMETER  Invalid parameter.

+

+**/

+EFI_STATUS

+EFIAPI

+SpiFlashBlockErase (

+  IN    UINTN                     Address,

+  IN    UINTN                     *NumBytes

+  )

+{

+  EFI_STATUS          Status;

+  UINTN               Offset;

+  UINTN               RemainingBytes;

+

+  ASSERT (NumBytes != NULL);

+  if (NumBytes == NULL) {

+    return EFI_INVALID_PARAMETER;

+  }

+

+  ASSERT (Address >= mBiosAreaBaseAddress);

+  if (Address < mBiosAreaBaseAddress) {

+    return EFI_INVALID_PARAMETER;

+  }

+

+  Offset = Address - mBiosAreaBaseAddress;

+

+  ASSERT ((*NumBytes % SECTOR_SIZE_4KB) == 0);

+  if ((*NumBytes % SECTOR_SIZE_4KB) != 0) {

+    return EFI_INVALID_PARAMETER;

+  }

+

+  ASSERT ((*NumBytes + Offset) <= mBiosSize);

+  if ((*NumBytes + Offset) > mBiosSize) {

+    return EFI_INVALID_PARAMETER;

+  }

+

+  Status = EFI_SUCCESS;

+  RemainingBytes = *NumBytes;

+

+

+  Status = mSpiProtocol->FlashErase (

+                           mSpiProtocol,

+                           FlashRegionBios,

+                           (UINT32) Offset,

+                           (UINT32) RemainingBytes

+                           );

+  return Status;

+}

+

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c b/Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c
new file mode 100644
index 0000000000..7941b8f872
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c
@@ -0,0 +1,58 @@
+/** @file

+  SMM Library instance of SPI Flash Common Library Class

+

+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>

+  SPDX-License-Identifier: BSD-2-Clause-Patent

+**/

+

+#include <Library/SmmServicesTableLib.h>

+#include <Protocol/Spi.h>

+#include <Library/DebugLib.h>

+

+extern PCH_SPI_PROTOCOL   *mSpiProtocol;

+

+extern UINTN mBiosAreaBaseAddress;

+extern UINTN mBiosSize;

+extern UINTN mBiosOffset;

+

+/**

+  The library constructuor.

+

+  The function does the necessary initialization work for this library

+  instance.

+

+  @param[in]  ImageHandle       The firmware allocated handle for the UEFI image.

+  @param[in]  SystemTable       A pointer to the EFI system table.

+

+  @retval     EFI_SUCCESS       The function always return EFI_SUCCESS for now.

+                                It will ASSERT on error for debug version.

+  @retval     EFI_ERROR         Please reference LocateProtocol for error code details.

+**/

+EFI_STATUS

+EFIAPI

+SmmSpiFlashCommonLibConstructor (

+  IN EFI_HANDLE        ImageHandle,

+  IN EFI_SYSTEM_TABLE  *SystemTable

+  )

+{

+  EFI_STATUS Status;

+  UINT32     BaseAddr;

+  UINT32     RegionSize;

+

+  mBiosAreaBaseAddress = (UINTN)PcdGet32 (PcdBiosAreaBaseAddress);

+  mBiosSize            = (UINTN)PcdGet32 (PcdBiosSize);

+

+  //

+  // Locate the SMM SPI protocol.

+  //

+  Status = gSmst->SmmLocateProtocol (

+                    &gPchSmmSpiProtocolGuid,

+                    NULL,

+                    (VOID **) &mSpiProtocol

+                    );

+  ASSERT_EFI_ERROR (Status);

+

+  mSpiProtocol->GetRegionAddress (mSpiProtocol, FlashRegionBios, &BaseAddr, &RegionSize);

+  mBiosOffset = BaseAddr;

+  return Status;

+}

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c
new file mode 100644
index 0000000000..a2367047cd
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c
@@ -0,0 +1,168 @@
+/** @file

+  This file initialises and Installs GopPolicy Protocol.

+

+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>

+  SPDX-License-Identifier: BSD-2-Clause-Patent

+**/

+

+#include <PiDxe.h>

+#include <Library/UefiBootServicesTableLib.h>

+#include <Library/BaseMemoryLib.h>

+#include <Library/MemoryAllocationLib.h>

+#include <Protocol/FirmwareVolume2.h>

+#include <Protocol/GopPolicy.h>

+

+GLOBAL_REMOVE_IF_UNREFERENCED GOP_POLICY_PROTOCOL        mGOPPolicy;

+GLOBAL_REMOVE_IF_UNREFERENCED UINT32                     mVbtSize = 0;

+GLOBAL_REMOVE_IF_UNREFERENCED EFI_PHYSICAL_ADDRESS       mVbtAddress = 0;

+

+/**

+  @param[out] CurrentLidStatus

+

+  @retval     EFI_SUCCESS

+  @retval     EFI_UNSUPPORTED

+**/

+EFI_STATUS

+EFIAPI

+GetPlatformLidStatus (

+  OUT LID_STATUS *CurrentLidStatus

+  )

+{

+  return EFI_UNSUPPORTED;

+}

+

+/**

+  @param[out] CurrentDockStatus

+

+  @retval     EFI_SUCCESS

+  @retval     EFI_UNSUPPORTED

+**/

+EFI_STATUS

+EFIAPI

+GetPlatformDockStatus (

+  OUT DOCK_STATUS  CurrentDockStatus

+  )

+{

+    return EFI_UNSUPPORTED;

+}

+

+/**

+  @param[out] VbtAddress

+  @param[out] VbtSize

+

+  @retval     EFI_SUCCESS

+  @retval     EFI_NOT_FOUND

+**/

+EFI_STATUS

+EFIAPI

+GetVbtData (

+  OUT EFI_PHYSICAL_ADDRESS *VbtAddress,

+  OUT UINT32               *VbtSize

+  )

+{

+  EFI_STATUS                    Status;

+  UINTN                         FvProtocolCount;

+  EFI_HANDLE                    *FvHandles;

+  EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;

+  UINTN                         Index;

+  UINT32                        AuthenticationStatus;

+  UINT8                         *Buffer;

+  UINTN                         VbtBufferSize;

+

+

+  Status = EFI_NOT_FOUND;

+  if ( mVbtAddress == 0) {

+    Fv           = NULL;

+

+    Buffer = 0;

+    FvHandles = NULL;

+    Status = gBS->LocateHandleBuffer (

+                    ByProtocol,

+                    &gEfiFirmwareVolume2ProtocolGuid,

+                    NULL,

+                    &FvProtocolCount,

+                    &FvHandles

+                    );

+    if (!EFI_ERROR (Status)) {

+      for (Index = 0; Index < FvProtocolCount; Index++) {

+        Status = gBS->HandleProtocol (

+                        FvHandles[Index],

+                        &gEfiFirmwareVolume2ProtocolGuid,

+                        (VOID **) &Fv

+                        );

+        VbtBufferSize = 0;

+        Status = Fv->ReadSection (

+                       Fv,

+                       PcdGetPtr (PcdIntelGraphicsVbtFileGuid),

+                       EFI_SECTION_RAW,

+                       0,

+                       (VOID **) &Buffer,

+                       &VbtBufferSize,

+                       &AuthenticationStatus

+                       );

+        if (!EFI_ERROR (Status)) {

+          *VbtAddress = (EFI_PHYSICAL_ADDRESS)Buffer;

+          *VbtSize = (UINT32)VbtBufferSize;

+          mVbtAddress = *VbtAddress;

+          mVbtSize = *VbtSize;

+          Status = EFI_SUCCESS;

+          break;

+        }

+      }

+    } else {

+      Status = EFI_NOT_FOUND;

+    }

+

+    if (FvHandles != NULL) {

+      FreePool (FvHandles);

+      FvHandles = NULL;

+    }

+  } else {

+    *VbtAddress = mVbtAddress;

+    *VbtSize = mVbtSize;

+    Status = EFI_SUCCESS;

+  }

+

+  return Status;

+}

+

+/**

+Initialize GOP DXE Policy

+

+@param[in] ImageHandle          Image handle of this driver.

+

+@retval EFI_SUCCESS             Initialization complete.

+@retval EFI_UNSUPPORTED         The chipset is unsupported by this driver.

+@retval EFI_OUT_OF_RESOURCES    Do not have enough resources to initialize the driver.

+@retval EFI_DEVICE_ERROR        Device error, driver exits abnormally.

+**/

+EFI_STATUS

+EFIAPI

+GopPolicyInitDxe (

+  IN EFI_HANDLE       ImageHandle

+  )

+{

+  EFI_STATUS         Status;

+

+  //

+  // Initialize the EFI Driver Library

+  //

+  SetMem (&mGOPPolicy, sizeof (GOP_POLICY_PROTOCOL), 0);

+

+  mGOPPolicy.Revision                = GOP_POLICY_PROTOCOL_REVISION_03;

+  mGOPPolicy.GetPlatformLidStatus    = GetPlatformLidStatus;

+  mGOPPolicy.GetVbtData              = GetVbtData;

+  mGOPPolicy.GetPlatformDockStatus   = GetPlatformDockStatus;

+

+  //

+  // Install protocol to allow access to this Policy.

+  //

+  Status = gBS->InstallMultipleProtocolInterfaces (

+                  &ImageHandle,

+                  &gGopPolicyProtocolGuid,

+                  &mGOPPolicy,

+                  NULL

+                  );

+

+  return Status;

+}

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxePchPolicyInit.c b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxePchPolicyInit.c
new file mode 100644
index 0000000000..e75abcb42a
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxePchPolicyInit.c
@@ -0,0 +1,61 @@
+/** @file

+  This file initialises and Installs GopPolicy Protocol.

+

+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>

+  SPDX-License-Identifier: BSD-2-Clause-Patent

+**/

+

+#include <Uefi.h>

+#include <Library/DebugLib.h>

+

+EFI_STATUS

+EFIAPI

+CreatePchDxeConfigBlocks (

+  IN OUT  VOID      **SaPolicy

+  );

+

+EFI_STATUS

+EFIAPI

+PchInstallPolicyProtocol (

+  IN  EFI_HANDLE                  ImageHandle,

+  IN  VOID                        *PchPolicy

+  );

+

+/**

+  Initialize PCH DXE Policy

+

+  @param[in] ImageHandle          Image handle of this driver.

+

+  @retval EFI_SUCCESS             Initialization complete.

+  @retval EFI_UNSUPPORTED         The chipset is unsupported by this driver.

+  @retval EFI_OUT_OF_RESOURCES    Do not have enough resources to initialize the driver.

+  @retval EFI_DEVICE_ERROR        Device error, driver exits abnormally.

+**/

+EFI_STATUS

+EFIAPI

+PchPolicyInitDxe (

+  IN EFI_HANDLE           ImageHandle

+  )

+{

+  EFI_STATUS    Status;

+  EFI_HANDLE    PchHandle;

+  VOID          *PchPolicy;

+

+  //

+  // Call CreatePchDxeConfigBlocks to create & initialize platform policy structure

+  // and get all Intel default policy settings.

+  //

+  Status = CreatePchDxeConfigBlocks (&PchPolicy);

+  ASSERT_EFI_ERROR (Status);

+

+  //

+  // Install PchInstallPolicyProtocol.

+  // While installed, RC assumes the Policy is ready and finalized. So please

+  // update and override any setting before calling this function.

+  //

+  PchHandle = NULL;

+  Status = PchInstallPolicyProtocol (PchHandle, PchPolicy);

+  ASSERT_EFI_ERROR (Status);

+

+  return EFI_SUCCESS;

+}

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.c b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.c
new file mode 100644
index 0000000000..5a9def9d13
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.c
@@ -0,0 +1,61 @@
+/** @file

+  This file initialises and Installs GopPolicy Protocol.

+

+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>

+  SPDX-License-Identifier: BSD-2-Clause-Patent

+**/

+

+#include <Uefi.h>

+#include <Library/DebugLib.h>

+

+EFI_STATUS

+EFIAPI

+CreateSaDxeConfigBlocks (

+  IN OUT  VOID      **SaPolicy

+  );

+

+EFI_STATUS

+EFIAPI

+SaInstallPolicyProtocol (

+  IN  EFI_HANDLE                  ImageHandle,

+  IN  VOID                        *SaPolicy

+  );

+

+/**

+  Initialize SA DXE Policy

+

+  @param[in] ImageHandle          Image handle of this driver.

+

+  @retval EFI_SUCCESS             Initialization complete.

+  @retval EFI_UNSUPPORTED         The chipset is unsupported by this driver.

+  @retval EFI_OUT_OF_RESOURCES    Do not have enough resources to initialize the driver.

+  @retval EFI_DEVICE_ERROR        Device error, driver exits abnormally.

+**/

+EFI_STATUS

+EFIAPI

+SaPolicyInitDxe (

+  IN EFI_HANDLE           ImageHandle

+  )

+{

+  EFI_STATUS    Status;

+  EFI_HANDLE    SaHandle;

+  VOID          *SaPolicy;

+

+  //

+  // Call CreateSaDxeConfigBlocks to create & initialize platform policy structure

+  // and get all Intel default policy settings.

+  //

+  Status = CreateSaDxeConfigBlocks (&SaPolicy);

+  ASSERT_EFI_ERROR (Status);

+

+  //

+  // Install SaInstallPolicyProtocol.

+  // While installed, RC assumes the Policy is ready and finalized. So please

+  // update and override any setting before calling this function.

+  //

+  SaHandle = NULL;

+  Status = SaInstallPolicyProtocol (SaHandle, SaPolicy);

+  ASSERT_EFI_ERROR (Status);

+

+  return EFI_SUCCESS;

+}

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c
new file mode 100644
index 0000000000..2eee9958be
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c
@@ -0,0 +1,97 @@
+/** @file

+

+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>

+  SPDX-License-Identifier: BSD-2-Clause-Patent

+**/

+

+#include <PiDxe.h>

+#include <Library/PcdLib.h>

+#include <Library/DebugLib.h>

+#include <Library/UefiBootServicesTableLib.h>

+

+/**

+  Initialize SA DXE Policy

+

+  @param[in] ImageHandle          Image handle of this driver.

+

+  @retval EFI_SUCCESS             Initialization complete.

+  @retval EFI_UNSUPPORTED         The chipset is unsupported by this driver.

+  @retval EFI_OUT_OF_RESOURCES    Do not have enough resources to initialize the driver.

+  @retval EFI_DEVICE_ERROR        Device error, driver exits abnormally.

+**/

+EFI_STATUS

+EFIAPI

+SaPolicyInitDxe (

+  IN EFI_HANDLE           ImageHandle

+  );

+

+/**

+  Initialize PCH DXE Policy

+

+  @param[in] ImageHandle          Image handle of this driver.

+

+  @retval EFI_SUCCESS             Initialization complete.

+  @retval EFI_UNSUPPORTED         The chipset is unsupported by this driver.

+  @retval EFI_OUT_OF_RESOURCES    Do not have enough resources to initialize the driver.

+  @retval EFI_DEVICE_ERROR        Device error, driver exits abnormally.

+**/

+EFI_STATUS

+EFIAPI

+PchPolicyInitDxe (

+  IN EFI_HANDLE           ImageHandle

+  );

+

+/**

+  Initialize GOP DXE Policy

+

+  @param[in] ImageHandle          Image handle of this driver.

+

+  @retval EFI_SUCCESS             Initialization complete.

+  @retval EFI_UNSUPPORTED         The chipset is unsupported by this driver.

+  @retval EFI_OUT_OF_RESOURCES    Do not have enough resources to initialize the driver.

+  @retval EFI_DEVICE_ERROR        Device error, driver exits abnormally.

+**/

+EFI_STATUS

+EFIAPI

+GopPolicyInitDxe (

+  IN EFI_HANDLE           ImageHandle

+  );

+

+/**

+  Performs silicon late policy update.

+

+  The meaning of Policy is defined by silicon code.

+  It could be the raw data, a handle, a Protocol, etc.

+

+  The input Policy must be returned by SiliconPolicyDoneLate().

+

+  In FSP or non-FSP path, the board may use additional way to get

+  the silicon policy data field based upon the input Policy.

+

+  @param[in, out] Policy       Pointer to policy.

+

+  @return the updated policy.

+**/

+VOID *

+EFIAPI

+SiliconPolicyUpdateLate (

+  IN OUT VOID *Policy

+  )

+{

+  EFI_STATUS               Status;

+

+  SaPolicyInitDxe (gImageHandle);

+  PchPolicyInitDxe (gImageHandle);

+

+  if (PcdGetBool (PcdIntelGopEnable)) {

+    //

+    // GOP Dxe Policy Initialization

+    //

+    Status = GopPolicyInitDxe (gImageHandle);

+    RETURN_ERROR (Status);

+    DEBUG ((DEBUG_INFO, "GOP Dxe Policy Initialization done\n"));

+  }

+

+  return Policy;

+}

+

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf
new file mode 100644
index 0000000000..573dbfa04a
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf
@@ -0,0 +1,49 @@
+## @file

+#  Component information file for Silicon Policy Update Library

+#

+#  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>

+#  SPDX-License-Identifier: BSD-2-Clause-Patent

+#

+##

+

+[Defines]

+  INF_VERSION                    = 0x00010005

+  BASE_NAME                      = DxeSiliconUpdateLib

+  FILE_GUID                      = C523609D-E354-416B-B24F-33468D4BD21D

+  MODULE_TYPE                    = DXE_DRIVER

+  VERSION_STRING                 = 1.0

+  LIBRARY_CLASS                  = SiliconPolicyUpdateLib

+

+[LibraryClasses]

+  BaseLib

+  PcdLib

+  DebugLib

+  UefiBootServicesTableLib

+  DxeSaPolicyLib

+  DxePchPolicyLib

+

+[Packages]

+  MdePkg/MdePkg.dec

+  MdeModulePkg/MdeModulePkg.dec

+  TigerlakeSiliconPkg/SiPkg.dec

+  MinPlatformPkg/MinPlatformPkg.dec

+  TigerlakeOpenBoardPkg/OpenBoardPkg.dec

+  IntelSiliconPkg/IntelSiliconPkg.dec

+

+[Sources]

+  DxeSiliconPolicyUpdateLate.c

+  DxeSaPolicyInit.c

+  DxePchPolicyInit.c

+  DxeGopPolicyInit.c

+

+[Pcd]

+  gBoardModuleTokenSpaceGuid.PcdIntelGopEnable

+  gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid

+  gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid

+

+[Protocols]

+  gEfiFirmwareVolume2ProtocolGuid               ## CONSUMES

+  gGopPolicyProtocolGuid                        ## PRODUCES

+

+[Depex]

+  gEfiVariableArchProtocolGuid

-- 
2.24.0.windows.2


  reply	other threads:[~2021-02-09 23:45 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-09  8:45 [Patch V2 1/8] TigerlakeOpenBoardPkg: Add package and headers Heng Luo
2021-02-09  8:45 ` [Patch V2 2/8] TigerlakeOpenBoardPkg/TigerlakeURvp: Add fdf and header file Heng Luo
2021-02-09 23:42   ` Chaganty, Rangasai V
2021-02-09  8:45 ` [Patch V2 3/8] TigerlakeOpenBoardPkg: Add library instances Heng Luo
2021-02-09 23:45   ` Chaganty, Rangasai V [this message]
2021-02-09  8:45 ` [Patch V2 4/8] TigerlakeOpenBoardPkg/TigerlakeURvp: " Heng Luo
2021-02-10  0:38   ` Chaganty, Rangasai V
2021-02-10  3:58     ` Heng Luo
2021-02-09  8:45 ` [Patch V2 5/8] TigerlakeOpenBoardPkg: Add modules Heng Luo
2021-02-10  0:22   ` Chaganty, Rangasai V
2021-02-10  0:27   ` Chaganty, Rangasai V
2021-02-09  8:45 ` [Patch V2 6/8] TigerlakeOpenBoardPkg/TigerlakeURvp: Add DSC and build files Heng Luo
2021-02-10  0:29   ` Chaganty, Rangasai V
2021-02-09  8:45 ` [Patch V2 7/8] Enable build for TigerlakeOpenBoardPkg Heng Luo
2021-02-10  0:30   ` Chaganty, Rangasai V
2021-02-09  8:45 ` [Patch V2 8/8] Update Maintainers.txt " Heng Luo
2021-02-10  0:31   ` Chaganty, Rangasai V
2021-02-09 23:41 ` [Patch V2 1/8] TigerlakeOpenBoardPkg: Add package and headers Chaganty, Rangasai V

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