From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web10.963.1573872821602701723 for ; Fri, 15 Nov 2019 18:53:41 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@intel.onmicrosoft.com header.s=selector2-intel-onmicrosoft-com header.b=zvqkNMHq; spf=pass (domain: intel.com, ip: 192.55.52.151, mailfrom: michael.a.kubacki@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Nov 2019 18:53:41 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,310,1569308400"; d="scan'208";a="405533346" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by fmsmga005.fm.intel.com with ESMTP; 15 Nov 2019 18:53:41 -0800 Received: from fmsmsx122.amr.corp.intel.com (10.18.125.37) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.439.0; Fri, 15 Nov 2019 18:53:41 -0800 Received: from FMSEDG001.ED.cps.intel.com (10.1.192.133) by fmsmsx122.amr.corp.intel.com (10.18.125.37) with Microsoft SMTP Server (TLS) id 14.3.439.0; Fri, 15 Nov 2019 18:53:41 -0800 Received: from NAM04-BN3-obe.outbound.protection.outlook.com (104.47.46.57) by edgegateway.intel.com (192.55.55.68) with Microsoft SMTP Server (TLS) id 14.3.439.0; Fri, 15 Nov 2019 18:53:40 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=KIvc5TIeI3VwM6Gg2aYNfMZbq0mm3+YbWNYZj41kCuyAymLLKnN8H1KWzlIylaYxyhblGhx505ws/fIKBFEamRpDOPBagpGrC8w7XT7XXXDiPqaCG0+LbobKh3YoJOtlQocySrGur67PB2ygRquUEqDgGk4e7+ZbApk7/sjbyUsGq2pJXgMKGVtUsFi1CQsXGxkAYxTrDR2rX+JFr+UV1v1VK9LBiG/Ndnn/zSCiZbjiSqHege3vv5ih9dCqEtI88xsF797s5IFtRuxJysm/4Q/uyed4ITfm3ZYzcid/QIJbwr6/KFdD3ErsZR/U4VIMNEGCIUy8ChoFlNIGdpWXsw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=U/2UPC3QjvOtJUHsCNxOVqJECXuZolt+AeGhaxY1RSY=; b=kvCoCHet5+UWbf3G6nML5YZSLJdpVeKANaI3euJi8gPM7npSG5XECVGw39LD9n90H91NoISeExdd0wNjmWD4bs8l9xSIEGkgQPfj9RrmFklOIzeWTdk6P2D5aiWG6302niCWMbkhiixOfse5LMYn2lQTzRUevuh8ELEjfFHMjbgxtdCNuCR3wZX2cVwHjP8XoEKwPNBt3HKAZon1B9Vw9fyowov60LkHiLChM7tQx+ZqVMCWyP9iLk9Ry1JzpC9CDQnQEH+qPMsZvBjklE+3tgS01Sn05UiS9RXh84Y+3xoolk5Xt64LcLMaUONW4qe8CoN7UFNgEicLbmcHLz3hww== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=intel.onmicrosoft.com; s=selector2-intel-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=U/2UPC3QjvOtJUHsCNxOVqJECXuZolt+AeGhaxY1RSY=; b=zvqkNMHqv50lcezmthLcv0zzvKh0GacSMvDwfRc7P7ATt6b7eB3yDnJ8oiniB48+VWrWfZJODoudjZLtEO5SWp4FJ5NIL5hZOePHYbUmVrFq+kQ6yrSoJ67A8HoafVJSS7muFK2ipERBJTCj7hDa7bSYXF+gzUo/+PMVRxix+oc= Received: from BY5PR11MB4484.namprd11.prod.outlook.com (52.132.254.155) by BY5PR11MB4226.namprd11.prod.outlook.com (52.132.253.140) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2451.23; Sat, 16 Nov 2019 02:53:38 +0000 Received: from BY5PR11MB4484.namprd11.prod.outlook.com ([fe80::a114:604b:7ca3:5420]) by BY5PR11MB4484.namprd11.prod.outlook.com ([fe80::a114:604b:7ca3:5420%7]) with mapi id 15.20.2451.027; Sat, 16 Nov 2019 02:53:38 +0000 From: "Kubacki, Michael A" To: "Desimone, Nathaniel L" , "devel@edk2.groups.io" CC: "Chiu, Chasel" , "Chaganty, Rangasai V" Subject: Re: [edk2-platforms] [PATCH V1 05/13] CoffeelakeSiliconPkg: Add SiliconInitLib Thread-Topic: [edk2-platforms] [PATCH V1 05/13] CoffeelakeSiliconPkg: Add SiliconInitLib Thread-Index: AQHVmrP9eVWAE4Z0xkqas0EvhjBb7KeNGVtw Date: Sat, 16 Nov 2019 02:53:38 +0000 Message-ID: References: <20191114060655.5161-1-nathaniel.l.desimone@intel.com> <20191114060655.5161-6-nathaniel.l.desimone@intel.com> In-Reply-To: <20191114060655.5161-6-nathaniel.l.desimone@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows x-ctpclassification: CTP_NT x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiOWNhNDcwZjMtNTI2OC00MDk4LTllMzktOGYzMzkxMTIxMGEyIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoieUdLcEY0K3o2OWFOZkRKWEJkRGt3UU11OXowWFBxeWN0aEUxQTQweFFxZzdXb0RDblo5eUhtRW4yZjIyZTR5UiJ9 dlp-reaction: no-action dlp-version: 11.2.0.6 authentication-results: spf=none (sender IP is ) smtp.mailfrom=michael.a.kubacki@intel.com; x-originating-ip: [134.134.136.217] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 21052152-e61c-4d4c-096b-08d76a402ea3 x-ms-traffictypediagnostic: BY5PR11MB4226: x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:10000; x-forefront-prvs: 02234DBFF6 x-forefront-antispam-report: SFV:NSPM;SFS:(10019020)(136003)(366004)(346002)(396003)(39860400002)(376002)(13464003)(189003)(199004)(76116006)(66946007)(55016002)(25786009)(66476007)(66556008)(52536014)(4326008)(14454004)(5660300002)(9686003)(64756008)(2906002)(3846002)(6116002)(66446008)(6436002)(229853002)(8936002)(81166006)(81156014)(8676002)(478600001)(6246003)(107886003)(14444005)(256004)(2501003)(76176011)(74316002)(102836004)(53546011)(6506007)(486006)(7736002)(476003)(305945005)(71200400001)(71190400001)(7696005)(11346002)(446003)(110136005)(54906003)(66066001)(316002)(99286004)(33656002)(86362001)(186003)(26005);DIR:OUT;SFP:1102;SCL:1;SRVR:BY5PR11MB4226;H:BY5PR11MB4484.namprd11.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;MX:1;A:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: mDH4JvF0uhzTL/c6D5f1bvBMrJ7DrJFSrNjgXu9r4R7DQ4rGg2n3gmhydaem9c1Ra20/1Uzp3pYndKBgveZuM5ELsc5zovbv0YYKYXSK9UhKsK8KnI8dVg6pMk5b062LU1yQmMeANPFhjBH3/ZQt8ZxN9ZTVWhtrm8xwaP5kiggv+cPjL7J20i9m5kQbLJHhuZdoNqDMESuyEh56iG0hBUoIALAxp142527nHF7KHrf3xb+2mYz9msRiOxQYIYI7GKX+rXPzx0Im6jSUdvRyBKF+3ZDV8XEVRzGf5i4YCJTOCid5feS3r74NZ5PWGTxoeENLC1007HK6XeTGzNq34OZ2meI9ULPcDTDHQDGxY/8uW7Roa0HtuSfuiqfrItcfIb0waPNRFmbjfWe6o7lVEKrDVidEFMGCAlGukh78pxQbkV7n1SkbJuGFqofLUxk+ MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 21052152-e61c-4d4c-096b-08d76a402ea3 X-MS-Exchange-CrossTenant-originalarrivaltime: 16 Nov 2019 02:53:38.7483 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: UyeiVcs4s1uch/Rj7+Ts4ef59xFnFTww0XEsyYg8wq34b2yW1tvyQzW0J5xFLzApqIGW2HLtwaeHZEwRpArIjspI2EZOFJDmTpl/om94VcM= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR11MB4226 Return-Path: michael.a.kubacki@intel.com X-OriginatorOrg: intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Michael Kubacki > -----Original Message----- > From: Desimone, Nathaniel L > Sent: Wednesday, November 13, 2019 10:07 PM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Kubacki, Michael A > ; Chaganty, Rangasai V > > Subject: [edk2-platforms] [PATCH V1 05/13] CoffeelakeSiliconPkg: Add > SiliconInitLib >=20 > SiliconInitLib contains Silicon Init APIs that can be reused by BoardInit= Lib. It is > expected that several implementations of BoardInitLib exist for a given S= OC, > these APIs allow the various BoardInitLib implementations to reuse common > silicon initialization code. This matches the implementation already foun= d in > KabylakeSiliconPkg. This change also adds halting the TCO watch dog timer= to > PEI, which was previously done in SEC. >=20 > Cc: Chasel Chiu > Cc: Michael Kubacki > Cc: Sai Chaganty > Signed-off-by: Nate DeSimone > --- > .../Include/Library/SiliconInitLib.h | 28 +++++ > .../PeiSiliconInitLib/PeiSiliconInitLib.inf | 46 ++++++++ > .../Library/PeiSiliconInitLib/SiliconInit.c | 19 +++ > .../PeiSiliconInitLib/SiliconInitPreMem.c | 109 ++++++++++++++++++ > 4 files changed, 202 insertions(+) > create mode 100644 > Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconInitLib.h > create mode 100644 > Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconIn= itLib.in > f > create mode 100644 > Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInit.= c > create mode 100644 > Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInitP= reMem > .c >=20 > diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconIn= itLib.h > b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconInitLib.h > new file mode 100644 > index 0000000000..a3411126a7 > --- /dev/null > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconInitLib. > +++ h > @@ -0,0 +1,28 @@ > +/** @file++Copyright (c) 2019, Intel Corporation. All rights > +reserved.
+SPDX-License-Identifier: > +BSD-2-Clause-Patent++**/++#ifndef _SILICON_INIT_LIB_H_+#define > +_SILICON_INIT_LIB_H_++#include ++VOID+EarlySiliconInit (+ > +VOID+ );++VOID+SiliconInit (+ VOID+ );++VOID+LateSiliconInit (+ > +VOID+ );++#endif > \ No newline at end of file > diff --git > a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSilicon= InitLib. > inf > b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSilicon= InitLib. > inf > new file mode 100644 > index 0000000000..47da5f608b > --- /dev/null > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSi > +++ liconInitLib.inf > @@ -0,0 +1,46 @@ > +### @file+#+# Copyright (c) 2019, Intel Corporation. All rights > reserved.
+#+# SPDX-License-Identifier: BSD-2-Clause- > Patent+#+###++[Defines]+ INF_VERSION =3D 0x00010017+ > BASE_NAME =3D SiliconInitLib+ FILE_GUID = =3D 82F2ACF0- > 2EBE-48C8-AC58-9D0F8BC1E16E+ VERSION_STRING =3D 1.0+ > MODULE_TYPE =3D PEIM+ LIBRARY_CLASS = =3D > SiliconInitLib+#+# The following information is for reference only and no= t > required by the build tools.+#+# VALID_ARCHITECTURES =3D IA32 X64 IPF > EBC+#++[LibraryClasses]+ BaseLib+ BaseMemoryLib+ DebugLib+ HobLib+ > IoLib+ PcdLib+ PeiServicesLib+ PchCycleDecodingLib+ > PmcLib++[Packages]+ MdePkg/MdePkg.dec+ > CoffeelakeSiliconPkg/SiPkg.dec++[Sources]+ SiliconInit.c+ > SiliconInitPreMem.c++[Guids]+ gTcoWdtHobGuid = ## > CONSUMES++[Pcd]+ gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## > CONSUMES+ gSiPkgTokenSpaceGuid.PcdTcoBaseAddress ## > CONSUMESdiff --git > a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconIni= t.c > b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconIni= t.c > new file mode 100644 > index 0000000000..122c02a3e5 > --- /dev/null > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/Silic > +++ onInit.c > @@ -0,0 +1,19 @@ > +/** @file+ Silicon Init APIs for MinPlatform BoardInitLib > +implementations.++Copyright (c) 2019, Intel Corporation. All rights > +reserved.
+SPDX-License-Identifier: > +BSD-2-Clause-Patent++**/++#include ++/**+ Late PCH > +Init+**/+VOID+LateSiliconInit (+ VOID+ )+{+}diff --git > +a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconI > +nitPreMem.c > +b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconI > +nitPreMem.c > new file mode 100644 > index 0000000000..23e4a3d4a0 > --- /dev/null > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/Silic > +++ onInitPreMem.c > @@ -0,0 +1,109 @@ > +/** @file+ Silicon Init APIs for MinPlatform BoardInitLib > implementations.++Copyright (c) 2019, Intel Corporation. All rights > reserved.
+SPDX-License-Identifier: BSD-2-Clause- > Patent++**/++#include +#include +#include > +#include +#include > +#include +#include > +#include > +#include +#include > +#include ++/**+ Early > PCH initialization+**/+VOID+EarlySiliconInit (+ VOID+ )+{+ UINT16 > Data16;+ UINT8 Data8;+ UINT8 TcoRebootHappened;+ > TCO_WDT_HOB *TcoWdtHobPtr;+ EFI_STATUS Status;++ ///+ /// LPC I/O > Configuration+ ///+ PchLpcIoDecodeRangesSet (+ > (V_LPC_CFG_IOD_LPT_378 << N_LPC_CFG_IOD_LPT) |+ > (V_LPC_CFG_IOD_COMB_3E8 << N_LPC_CFG_IOD_COMB) |+ > (V_LPC_CFG_IOD_COMA_3F8 << N_LPC_CFG_IOD_COMA)+ );++ > PchLpcIoEnableDecodingSet (+ B_LPC_CFG_IOE_ME2 |+ > B_LPC_CFG_IOE_SE |+ B_LPC_CFG_IOE_ME1 |+ B_LPC_CFG_IOE_KE |+ > B_LPC_CFG_IOE_HGE |+ B_LPC_CFG_IOE_LGE |+ B_LPC_CFG_IOE_FDE > |+ B_LPC_CFG_IOE_PPE |+ B_LPC_CFG_IOE_CBE |+ > B_LPC_CFG_IOE_CAE+ );++ ///+ /// Halt the TCO timer+ ///+ Data16 = =3D > IoRead16 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO1_CNT);+ > Data16 |=3D B_TCO_IO_TCO1_CNT_TMR_HLT;+ IoWrite16 (PcdGet16 > (PcdTcoBaseAddress) + R_TCO_IO_TCO1_CNT, Data16);++ ///+ /// Read the > Second TO status bit+ ///+ Data8 =3D IoRead8 (PcdGet16 > (PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS);+ if ((Data8 & > B_TCO_IO_TCO2_STS_SECOND_TO) =3D=3D B_TCO_IO_TCO2_STS_SECOND_TO) > {+ TcoRebootHappened =3D 1;+ DEBUG ((DEBUG_INFO, > "PlatformInitPreMem - TCO Second TO status bit is set. This might be a TC= O > reboot\n"));+ }+ else {+ TcoRebootHappened =3D 0;+ }++ ///+ /// C= reate > HOB+ ///+ Status =3D PeiServicesCreateHob > (EFI_HOB_TYPE_GUID_EXTENSION, sizeof(TCO_WDT_HOB), (VOID > **)&TcoWdtHobPtr);+ if (!EFI_ERROR (Status)) {+ TcoWdtHobPtr- > >Header.Name =3D gTcoWdtHobGuid;+ TcoWdtHobPtr- > >TcoRebootHappened =3D TcoRebootHappened;+ }++ ///+ /// Clear the > Second TO status bit+ ///+ IoWrite8 (PcdGet16 (PcdTcoBaseAddress) + > R_TCO_IO_TCO2_STS, B_TCO_IO_TCO2_STS_SECOND_TO);+}++/**+ > Initialize the GPIO IO selection, GPIO USE selection, and GPIO signal inv= ersion > registers++**/+VOID+SiliconInit (+ VOID+ )+{+ UINT16 ABase;++ A= Base > =3D PmcGetAcpiBase ();++ ///+ /// Clear all pending SMI. On S3 clear po= wer > button enable so it will not generate an SMI.+ ///+ IoWrite16 (ABase + > R_ACPI_IO_PM1_EN, 0);+ IoWrite32 (ABase + > R_ACPI_IO_GPE0_EN_127_96, 0);+}-- > 2.23.0.windows.1