From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web09.511.1576112489172399378 for ; Wed, 11 Dec 2019 17:01:29 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@intel.onmicrosoft.com header.s=selector2-intel-onmicrosoft-com header.b=wL+xtVY9; spf=pass (domain: intel.com, ip: 134.134.136.31, mailfrom: michael.a.kubacki@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Dec 2019 17:01:28 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,303,1571727600"; d="scan'208";a="245505231" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by fmsmga002.fm.intel.com with ESMTP; 11 Dec 2019 17:01:26 -0800 Received: from fmsmsx151.amr.corp.intel.com (10.18.125.4) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 11 Dec 2019 17:01:24 -0800 Received: from FMSEDG001.ED.cps.intel.com (10.1.192.133) by FMSMSX151.amr.corp.intel.com (10.18.125.4) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 11 Dec 2019 17:01:23 -0800 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (104.47.55.103) by edgegateway.intel.com (192.55.55.68) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 11 Dec 2019 17:01:23 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Zn2BcE82QpTkswwDkpJBrkpjwURHqWQ85zS2rOVkZPuiEIobub6PzZDCznawM2NlBLiu7DPopKzbIlHNBqDGc2DTaWoE/NM2v5xUnWhr0ZkYnF3EgMVQHIDqxT2Lk8hDf9lqeiAcLJinmNq/GU8pMnBwd9b/2ZxEYMgtx/3S8ru0umI39y1pfLdvhPdEYzdX0jMAopy/oewFphBvSX98J1yetbIFJYcFy9QtJavYHEOgJkcHv1u90cCpaF/AQ1SCCoW1aQIrMG+LJOaK7shtjexkxQbb9tepMcEh4OLfRXO7qGagDeOhtqolcQT1cz8ZFEzR8pl0a/xqzWpm+tJdCA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=KeDJ9JYvssDZPF4KIS7txIX4s0koDNU+8hiUgAq42rA=; b=IUT6m4NDuegtZoaeTBFbv6OsdZtJjIOznvkB2D+afZs4X9shkSOgrC8trEK85m69fMO2mZbnmDyNwaq2Bos8Cftx25RWIHs1azKzTVC9niHtv8gLtFefPJ3i1PQkrq/kuWOE7erllfR6SKOE3Mm6ONMhObzMqZrU5TNdsLNpmPraUM9GCA4RTd9e5u4Co500nI+2O8yN7BEbVNpKKzZpI+0KOP8aLTVx6PIRkzogDxRZhFOPXfHbi6rJr0FYh9Fgud3ay8LrHy+MoGK5t2AQYDUIqR8vdYS6CI95bl2sErrXNVLmmLg5hhkPhNoBN0kA780YpP/pHtbuk6AsSzyEVw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=intel.onmicrosoft.com; s=selector2-intel-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=KeDJ9JYvssDZPF4KIS7txIX4s0koDNU+8hiUgAq42rA=; b=wL+xtVY9VoqhmNJErnZl9e6wj6N6HM4xmNWqr+Q0Mu9w7j8cukxxsAgFQzrx7k3bTAPG6syGz4dWoavXzRmDGMFHaZUgc3PTN4JYsgHb26iaZ7OHT3A7QJN3czjZ15g75YVqgRrAcFJrLA7gPzdzuaNd9DUHYxX8iUn9XvqzPak= Received: from BY5PR11MB4484.namprd11.prod.outlook.com (52.132.254.155) by BY5PR11MB4433.namprd11.prod.outlook.com (52.132.255.140) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2538.14; Thu, 12 Dec 2019 01:01:21 +0000 Received: from BY5PR11MB4484.namprd11.prod.outlook.com ([fe80::a114:604b:7ca3:5420]) by BY5PR11MB4484.namprd11.prod.outlook.com ([fe80::a114:604b:7ca3:5420%7]) with mapi id 15.20.2516.018; Thu, 12 Dec 2019 01:01:21 +0000 From: "Kubacki, Michael A" To: "Agyeman, Prince" , "devel@edk2.groups.io" CC: "Desimone, Nathaniel L" Subject: Re: [PATCH] SimicsOpenBoardPkg: Replace CMOS Hardcoded Addresses Thread-Topic: [PATCH] SimicsOpenBoardPkg: Replace CMOS Hardcoded Addresses Thread-Index: AQHVrFsUpteP0HXyXUuLHpNKCnuwe6e1ti7Q Date: Thu, 12 Dec 2019 01:01:21 +0000 Message-ID: References: <20191206173135.9112-1-prince.agyeman@intel.com> In-Reply-To: <20191206173135.9112-1-prince.agyeman@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows x-ctpclassification: CTP_NT x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNjhkMjNiZDctZTg1OS00NGE0LWJhZGItMmE1Mjg3ODk0OTdkIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoibDlVVWlMbHdDeFwvcjlPOWxxbVZaQjN1aENsb1wvQlJmT2U3RmJxUzB2NXVxWDJXMnNHeW5ERCt1a0FjWU9vWjk0In0= dlp-reaction: no-action dlp-version: 11.2.0.6 authentication-results: spf=none (sender IP is ) smtp.mailfrom=michael.a.kubacki@intel.com; x-originating-ip: [134.134.136.217] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 01e6047f-db50-41f7-ef7c-08d77e9ecd6d x-ms-traffictypediagnostic: BY5PR11MB4433: x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:849; x-forefront-prvs: 0249EFCB0B x-forefront-antispam-report: SFV:NSPM;SFS:(10019020)(136003)(39860400002)(376002)(346002)(396003)(366004)(199004)(13464003)(189003)(81156014)(66946007)(66476007)(71200400001)(66446008)(55016002)(966005)(64756008)(66556008)(81166006)(76116006)(8936002)(8676002)(52536014)(33656002)(5660300002)(107886003)(86362001)(316002)(7696005)(2906002)(110136005)(19627235002)(186003)(26005)(9686003)(4326008)(478600001)(53546011)(6506007);DIR:OUT;SFP:1102;SCL:1;SRVR:BY5PR11MB4433;H:BY5PR11MB4484.namprd11.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: W8pJtuPsu5zifS+dWeFf+F4NrPFqdkCFr908ClKEiwyNptRguASkfSoxUIX5iCd1fnVYXylHtkIibeGP9qDr9ZN2ch7n9NHik2FJGpczD+R5zPMo3d3OiGGbSWgLq3PzhlYoqqY6/ipAJSL02ifsEBLpCdg/zzKM3nTsJXvGFvdpBVQ4b8pLnVC+rdjY57qLXGb7Udio2FhVEDF4FbJjO0Rph2hG7JoOcRKizTwkFffDB6dzTRVTork/SEfuFaC1SI2zfrCLV5H4+zO56E7KKgWEfbVDJK5x8k2N9OIKKtLminN7/NnCJ5zSPqthSsysNl+5/TcKrX9k43wEoDZfIp2qSFmDR6ZAQ/aXoh6rO6MXENhBON4T5dxuGpS18JLllHvvcRxLBZryjNWTPm1GvbO8E80YjM9/KsxrysYV1zfgt8P6SoYXkWZvNNyqQ+aOl8vhnbqiuEzTMPKf0yH9QHggpAn1UcKVBNXiUZiW9aS0PA6ReagyQZQ62Tteb4StEnILLngva1za002pmOQyLliMc3u/nMbIQoTJExSz8EE= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 01e6047f-db50-41f7-ef7c-08d77e9ecd6d X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Dec 2019 01:01:21.1082 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: WZALkr4ZnlF1RQynDeNgRIPy9i+0IgQqQEB4GkhxQdjY7zmWYFATvHarkoK7sGaAGHbySIZ9euOlGrxJ2Lm9gdifvWHNpRxpkIgtyq+wpsE= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR11MB4433 Return-Path: michael.a.kubacki@intel.com X-OriginatorOrg: intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Please include [edk2-platforms] in the subject in the future. Reviewed-by: Michael Kubacki > -----Original Message----- > From: Agyeman, Prince > Sent: Friday, December 6, 2019 9:32 AM > To: devel@edk2.groups.io > Cc: Desimone, Nathaniel L ; Kubacki, > Michael A > Subject: [PATCH] SimicsOpenBoardPkg: Replace CMOS Hardcoded Addresses >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2330 >=20 > Changes: > * Added CmosMap.h that defines CMOS addresses used in > SimicsOpenBoardPkg as macros >=20 > * Replaced hardcoded CMOS addresses with the macros > defined in CmosMap.h >=20 > Cc: Nate DeSimone > Cc: Michael Kubacki >=20 > Signed-off-by: Prince Agyeman > --- > .../SimicsOpenBoardPkg/Include/CmosMap.h | 35 > +++++++++++++++++++ > .../SimicsOpenBoardPkg/SimicsPei/MemDetect.c | 23 ++++++++---- > .../SmbiosPlatformDxe/SmbiosPlatformDxe.c | 24 ++++++++----- > .../SmbiosPlatformDxe/SmbiosPlatformDxe.h | 1 + > 4 files changed, 68 insertions(+), 15 deletions(-) create mode 100644 > Platform/Intel/SimicsOpenBoardPkg/Include/CmosMap.h >=20 > diff --git a/Platform/Intel/SimicsOpenBoardPkg/Include/CmosMap.h > b/Platform/Intel/SimicsOpenBoardPkg/Include/CmosMap.h > new file mode 100644 > index 0000000000..3221ce9a5b > --- /dev/null > +++ b/Platform/Intel/SimicsOpenBoardPkg/Include/CmosMap.h > @@ -0,0 +1,35 @@ > +/** @file > +Cmos address definition macros header file. > + > +Copyright (c) 2019, Intel Corporation. All rights reserved.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#ifndef _CMOS_MAP_H_ > +#define _CMOS_MAP_H_ > + > +// > +// CMOS 0x34/0x35 specifies the system memory above 16 MB. > +// * CMOS(0x35) is the high byte > +// * CMOS(0x34) is the low byte > +// * The size is specified in 64kb chunks // * Since this is memory > +above 16MB, the 16MB must be added > +// into the calculation to get the total memory size. > +// > +#define CMOS_SYSTEM_MEM_ABOVE_16MB_LOW_BYTE 0x34 > +#define CMOS_SYSTEM_MEM_ABOVE_16MB_HIGH_BYTE 0x35 > + > +// > +// CMOS 0x5b-0x5d specifies the system memory above 4GB MB. > +// * CMOS(0x5d) is the most significant size byte // * CMOS(0x5c) is > +the middle size byte // * CMOS(0x5b) is the least significant size byte > +// * The size is specified in 64kb chunks // > +#define CMOS_SYSTEM_MEM_ABOVE_4GB_LOW_BYTE 0x5b > +#define CMOS_SYSTEM_MEM_ABOVE_4GB_MIDDLE_BYTE 0x5c > +#define CMOS_SYSTEM_MEM_ABOVE_4GB_HIGH_BYTE 0x5d > + > + > +#endif // _CMOS_MAP_H_ > diff --git a/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/MemDetect.c > b/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/MemDetect.c > index e547de0045..60aa54be9e 100644 > --- a/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/MemDetect.c > +++ b/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/MemDetect.c > @@ -26,6 +26,8 @@ > #include > #include >=20 > +#include > + > #include "Platform.h" >=20 > UINT8 mPhysMemAddressWidth; > @@ -74,24 +76,33 @@ X58TsegMbytesInitialization( > return; > } >=20 > +/** > + Get the system memory size below 4GB >=20 > + @return The size of system memory below 4GB **/ > UINT32 > GetSystemMemorySizeBelow4gb ( > VOID > ) > { > + UINT32 Size; > // > // CMOS 0x34/0x35 specifies the system memory above 16 MB. > - // * CMOS(0x35) is the high byte > - // * CMOS(0x34) is the low byte > // * The size is specified in 64kb chunks > // * Since this is memory above 16MB, the 16MB must be added > // into the calculation to get the total memory size. > // > - return (UINT32) (((UINTN)CmosRead16 (0x34) << 16) + SIZE_16MB); > + Size =3D (UINT32) ((CmosRead16 > (CMOS_SYSTEM_MEM_ABOVE_16MB_LOW_BYTE) << 16) > + + SIZE_16MB); > + return Size; > } >=20 > +/** > + Get the system memory size above 4GB >=20 > + @return The size of system memory above 4GB **/ > STATIC > UINT64 > GetSystemMemorySizeAbove4gb ( > @@ -100,12 +111,10 @@ GetSystemMemorySizeAbove4gb ( > UINT32 Size; > // > // CMOS 0x5b-0x5d specifies the system memory above 4GB MB. > - // * CMOS(0x5d) is the most significant size byte > - // * CMOS(0x5c) is the middle size byte > - // * CMOS(0x5b) is the least significant size byte > // * The size is specified in 64kb chunks > // > - Size =3D (CmosRead16 (0x5c) << 8) + CmosRead8 (0x5b); > + Size =3D (CmosRead16 (CMOS_SYSTEM_MEM_ABOVE_4GB_MIDDLE_BYTE) > << 8) > + + CmosRead8 (CMOS_SYSTEM_MEM_ABOVE_4GB_LOW_BYTE); >=20 > return LShiftU64 (Size, 16); > } > diff --git > a/Platform/Intel/SimicsOpenBoardPkg/SmbiosPlatformDxe/SmbiosPlatform > Dxe.c > b/Platform/Intel/SimicsOpenBoardPkg/SmbiosPlatformDxe/SmbiosPlatform > Dxe.c > index 37c659e275..23b284d2fa 100644 > --- > a/Platform/Intel/SimicsOpenBoardPkg/SmbiosPlatformDxe/SmbiosPlatform > Dxe.c > +++ > b/Platform/Intel/SimicsOpenBoardPkg/SmbiosPlatformDxe/SmbiosPlatform > +++ Dxe.c > @@ -9,23 +9,33 @@ >=20 > #include "SmbiosPlatformDxe.h" >=20 > +/** > + Get the system memory size below 4GB >=20 > + @return The size of system memory below 4GB **/ > UINT32 > GetSystemMemorySizeBelow4gb( > VOID > ) > { > + UINT32 Size; > // > // CMOS 0x34/0x35 specifies the system memory above 16 MB. > - // * CMOS(0x35) is the high byte > - // * CMOS(0x34) is the low byte > // * The size is specified in 64kb chunks > // * Since this is memory above 16MB, the 16MB must be added > // into the calculation to get the total memory size. > // > - return (UINT32) (((UINTN) CmosRead16 (0x34) << 16) + SIZE_16MB); > + Size =3D (UINT32) ((CmosRead16 > (CMOS_SYSTEM_MEM_ABOVE_16MB_LOW_BYTE) << 16) > + + SIZE_16MB); > + return Size; > } >=20 > +/** > + Get the system memory size above 4GB > + > + @return The size of system memory above 4GB **/ > STATIC > UINT64 > GetSystemMemorySizeAbove4gb( > @@ -35,14 +45,12 @@ GetSystemMemorySizeAbove4gb( > UINT32 Size; > // > // CMOS 0x5b-0x5d specifies the system memory above 4GB MB. > - // * CMOS(0x5d) is the most significant size byte > - // * CMOS(0x5c) is the middle size byte > - // * CMOS(0x5b) is the least significant size byte > // * The size is specified in 64kb chunks > // > - Size =3D (CmosRead16 (0x5c) << 8) + CmosRead8 (0x5b); > + Size =3D (CmosRead16 (CMOS_SYSTEM_MEM_ABOVE_4GB_MIDDLE_BYTE) > << 8) > + + CmosRead8 (CMOS_SYSTEM_MEM_ABOVE_4GB_LOW_BYTE); >=20 > - return LShiftU64(Size, 16); > + return LShiftU64 (Size, 16); > } >=20 > /** > diff --git > a/Platform/Intel/SimicsOpenBoardPkg/SmbiosPlatformDxe/SmbiosPlatform > Dxe.h > b/Platform/Intel/SimicsOpenBoardPkg/SmbiosPlatformDxe/SmbiosPlatform > Dxe.h > index 0dc174421c..ccd35e2924 100644 > --- > a/Platform/Intel/SimicsOpenBoardPkg/SmbiosPlatformDxe/SmbiosPlatform > Dxe.h > +++ > b/Platform/Intel/SimicsOpenBoardPkg/SmbiosPlatformDxe/SmbiosPlatform > +++ Dxe.h > @@ -21,6 +21,7 @@ > #include #include > #include > +#include >=20 > /** > Validates the SMBIOS entry point structure > -- > 2.19.1.windows.1