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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Michael Kubacki > -----Original Message----- > From: Desimone, Nathaniel L > Sent: Thursday, November 21, 2019 12:59 AM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Kubacki, Michael A > ; Chaganty, Rangasai V > > Subject: [edk2-platforms] [PATCH V2 06/14] CoffeelakeSiliconPkg: Add > SiliconInitLib >=20 > SiliconInitLib contains Silicon Init APIs that can be reused by BoardInit= Lib. It is > expected that several implementations of BoardInitLib exist for a given S= OC, > these APIs allow the various BoardInitLib implementations to reuse common > silicon initialization code. This matches the implementation already foun= d in > KabylakeSiliconPkg. This change also adds halting the TCO watch dog timer= to > PEI, which was previously done in SEC. >=20 > Cc: Chasel Chiu > Cc: Michael Kubacki > Cc: Sai Chaganty > Signed-off-by: Nate DeSimone > --- > .../Include/Library/SiliconInitLib.h | 28 +++++ > .../PeiSiliconInitLib/PeiSiliconInitLib.inf | 46 ++++++++ > .../Library/PeiSiliconInitLib/SiliconInit.c | 19 +++ > .../PeiSiliconInitLib/SiliconInitPreMem.c | 109 ++++++++++++++++++ > 4 files changed, 202 insertions(+) > create mode 100644 > Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconInitLib.h > create mode 100644 > Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconIn= itLib.in > f > create mode 100644 > Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInit.= c > create mode 100644 > Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInitP= reMem > .c >=20 > diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconIn= itLib.h > b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconInitLib.h > new file mode 100644 > index 0000000000..a3411126a7 > --- /dev/null > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconInitLib. > +++ h > @@ -0,0 +1,28 @@ > +/** @file++Copyright (c) 2019, Intel Corporation. All rights > +reserved.
+SPDX-License-Identifier: > +BSD-2-Clause-Patent++**/++#ifndef _SILICON_INIT_LIB_H_+#define > +_SILICON_INIT_LIB_H_++#include ++VOID+EarlySiliconInit (+ > +VOID+ );++VOID+SiliconInit (+ VOID+ );++VOID+LateSiliconInit (+ > +VOID+ );++#endif > \ No newline at end of file > diff --git > a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSilicon= InitLib. > inf > b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSilicon= InitLib. > inf > new file mode 100644 > index 0000000000..1534a24dd2 > --- /dev/null > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSi > +++ liconInitLib.inf > @@ -0,0 +1,46 @@ > +### @file+#+# Copyright (c) 2019, Intel Corporation. All rights > reserved.
+#+# SPDX-License-Identifier: BSD-2-Clause- > Patent+#+###++[Defines]+ INF_VERSION =3D 0x00010017+ > BASE_NAME =3D SiliconInitLib+ FILE_GUID = =3D 82F2ACF0- > 2EBE-48C8-AC58-9D0F8BC1E16E+ VERSION_STRING =3D 1.0+ > MODULE_TYPE =3D PEIM+ LIBRARY_CLASS = =3D > SiliconInitLib|SEC PEIM+#+# The following information is for reference on= ly > and not required by the build tools.+#+# VALID_ARCHITECTURES =3D IA32 X64 > IPF EBC+#++[LibraryClasses]+ BaseLib+ BaseMemoryLib+ DebugLib+ > HobLib+ IoLib+ PcdLib+ PeiServicesLib+ PchCycleDecodingLib+ > PmcLib++[Packages]+ MdePkg/MdePkg.dec+ > CoffeelakeSiliconPkg/SiPkg.dec++[Sources]+ SiliconInit.c+ > SiliconInitPreMem.c++[Guids]+ gTcoWdtHobGuid = ## > CONSUMES++[Pcd]+ gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## > CONSUMES+ gSiPkgTokenSpaceGuid.PcdTcoBaseAddress ## > CONSUMESdiff --git > a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconIni= t.c > b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconIni= t.c > new file mode 100644 > index 0000000000..1c15e0e54e > --- /dev/null > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/Silic > +++ onInit.c > @@ -0,0 +1,19 @@ > +/** @file+ Silicon Init APIs for MinPlatform BoardInitLib > +implementations.++Copyright (c) 2019, Intel Corporation. All rights > +reserved.
+SPDX-License-Identifier: > +BSD-2-Clause-Patent++**/++#include ++/**+ Late Silicon > +Initialization+**/+VOID+LateSiliconInit (+ VOID+ )+{+}diff --git > +a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconI > +nitPreMem.c > +b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconI > +nitPreMem.c > new file mode 100644 > index 0000000000..ab98b6ccc5 > --- /dev/null > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/Silic > +++ onInitPreMem.c > @@ -0,0 +1,109 @@ > +/** @file+ Silicon Init APIs for MinPlatform BoardInitLib > implementations.++Copyright (c) 2019, Intel Corporation. All rights > reserved.
+SPDX-License-Identifier: BSD-2-Clause- > Patent++**/++#include +#include +#include > +#include +#include > +#include +#include > +#include > +#include +#include > +#include ++/**+ Early > Silicon initialization+**/+VOID+EarlySiliconInit (+ VOID+ )+{+ UINT16 > Data16;+ UINT8 Data8;+ UINT8 TcoRebootHappened;+ > TCO_WDT_HOB *TcoWdtHobPtr;+ EFI_STATUS Status;++ ///+ /// LPC I/O > Configuration+ ///+ PchLpcIoDecodeRangesSet (+ > (V_LPC_CFG_IOD_LPT_378 << N_LPC_CFG_IOD_LPT) |+ > (V_LPC_CFG_IOD_COMB_3E8 << N_LPC_CFG_IOD_COMB) |+ > (V_LPC_CFG_IOD_COMA_3F8 << N_LPC_CFG_IOD_COMA)+ );++ > PchLpcIoEnableDecodingSet (+ B_LPC_CFG_IOE_ME2 |+ > B_LPC_CFG_IOE_SE |+ B_LPC_CFG_IOE_ME1 |+ B_LPC_CFG_IOE_KE |+ > B_LPC_CFG_IOE_HGE |+ B_LPC_CFG_IOE_LGE |+ B_LPC_CFG_IOE_FDE > |+ B_LPC_CFG_IOE_PPE |+ B_LPC_CFG_IOE_CBE |+ > B_LPC_CFG_IOE_CAE+ );++ ///+ /// Halt the TCO timer+ ///+ Data16 = =3D > IoRead16 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO1_CNT);+ > Data16 |=3D B_TCO_IO_TCO1_CNT_TMR_HLT;+ IoWrite16 (PcdGet16 > (PcdTcoBaseAddress) + R_TCO_IO_TCO1_CNT, Data16);++ ///+ /// Read the > Second TO status bit+ ///+ Data8 =3D IoRead8 (PcdGet16 > (PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS);+ if ((Data8 & > B_TCO_IO_TCO2_STS_SECOND_TO) =3D=3D B_TCO_IO_TCO2_STS_SECOND_TO) > {+ TcoRebootHappened =3D 1;+ DEBUG ((DEBUG_INFO, > "PlatformInitPreMem - TCO Second TO status bit is set. This might be a TC= O > reboot\n"));+ }+ else {+ TcoRebootHappened =3D 0;+ }++ ///+ /// C= reate > HOB+ ///+ Status =3D PeiServicesCreateHob > (EFI_HOB_TYPE_GUID_EXTENSION, sizeof(TCO_WDT_HOB), (VOID > **)&TcoWdtHobPtr);+ if (!EFI_ERROR (Status)) {+ TcoWdtHobPtr- > >Header.Name =3D gTcoWdtHobGuid;+ TcoWdtHobPtr- > >TcoRebootHappened =3D TcoRebootHappened;+ }++ ///+ /// Clear the > Second TO status bit+ ///+ IoWrite8 (PcdGet16 (PcdTcoBaseAddress) + > R_TCO_IO_TCO2_STS, B_TCO_IO_TCO2_STS_SECOND_TO);+}++/**+ > Initialize the GPIO IO selection, GPIO USE selection, and GPIO signal inv= ersion > registers++**/+VOID+SiliconInit (+ VOID+ )+{+ UINT16 ABase;++ A= Base > =3D PmcGetAcpiBase ();++ ///+ /// Clear all pending SMI. On S3 clear po= wer > button enable so it will not generate an SMI.+ ///+ IoWrite16 (ABase + > R_ACPI_IO_PM1_EN, 0);+ IoWrite32 (ABase + > R_ACPI_IO_GPE0_EN_127_96, 0);+}-- > 2.24.0.windows.2