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Fri, 22 Nov 2019 06:32:41 +0000 From: "Kubacki, Michael A" To: "Desimone, Nathaniel L" , "devel@edk2.groups.io" CC: "Chiu, Chasel" , "Gao, Liming" Subject: Re: [edk2-platforms] [PATCH V2 10/14] MinPlatformPkg: FSP Dispatch Mode Support for PlatformSecLib Thread-Topic: [edk2-platforms] [PATCH V2 10/14] MinPlatformPkg: FSP Dispatch Mode Support for PlatformSecLib Thread-Index: AQHVoEoOFlWjBgAe9UOis3ozZtoTE6eWt+WQ Date: Fri, 22 Nov 2019 06:32:41 +0000 Message-ID: References: <20191121085853.2626-1-nathaniel.l.desimone@intel.com> <20191121085853.2626-11-nathaniel.l.desimone@intel.com> In-Reply-To: <20191121085853.2626-11-nathaniel.l.desimone@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows x-ctpclassification: CTP_NT x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMWExOTQ3ZTYtZjQzZi00MmY5LWFjZTktNjJmOTkwNzQyZWJhIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiXC9BOG52ZUhYaFFWemhSbks1dlEyOWJ4NEJTSFwvSUdTNmR4eGlFd1BCeU1nXC9UQXh5TmIzNGpVWEFcLzZEM2NMRGQifQ== dlp-reaction: no-action dlp-version: 11.2.0.6 authentication-results: spf=none (sender IP is ) smtp.mailfrom=michael.a.kubacki@intel.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Michael Kubacki > -----Original Message----- > From: Desimone, Nathaniel L > Sent: Thursday, November 21, 2019 12:59 AM > To: devel@edk2.groups.io > Cc: Kubacki, Michael A ; Chiu, Chasel > ; Gao, Liming > Subject: [edk2-platforms] [PATCH V2 10/14] MinPlatformPkg: FSP Dispatch > Mode Support for PlatformSecLib >=20 > Cc: Michael Kubacki > Cc: Chasel Chiu > Cc: Liming Gao > Signed-off-by: Nate DeSimone > --- > .../FspWrapperPlatformSecLib.c | 34 ++++++++++++--- > .../SecFspWrapperPlatformSecLib.inf | 7 +++- > .../SecTempRamDone.c | 42 +++++++++++++++---- > .../Intel/MinPlatformPkg/MinPlatformPkg.dec | 28 ++++++++++++- > 4 files changed, 95 insertions(+), 16 deletions(-) >=20 > diff --git > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatf > ormSecLib/FspWrapperPlatformSecLib.c > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatf > ormSecLib/FspWrapperPlatformSecLib.c > index 303f3aac40..36bdc1dee8 100644 > --- > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatf > ormSecLib/FspWrapperPlatformSecLib.c > +++ > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat > +++ formSecLib/FspWrapperPlatformSecLib.c > @@ -1,7 +1,7 @@ > /** @file Provide FSP wrapper platform sec related function. -Copyrigh= t (c) > 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 20= 19, > Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-= 2- > Clause-Patent **/@@ -12,6 +12,7 @@ SPDX-License-Identifier: BSD-2- > Clause-Patent > #include #include > #include +#include > #include #include > @@ -66,6 +67,18 @@ PEI_SEC_PERFORMANCE_PPI > mSecPerformancePpi =3D { > SecGetPerformance }; +EFI_PEI_CORE_FV_LOCATION_PPI > mPeiCoreFvLocationPpi =3D {+ (VOID *) (UINTN) FixedPcdGet32 > (PcdFspmBaseAddress)+};++EFI_PEI_PPI_DESCRIPTOR > mPeiCoreFvLocationPpiList[] =3D {+ {+ EFI_PEI_PPI_DESCRIPTOR_PPI,+ > &gEfiPeiCoreFvLocationPpiGuid,+ &mPeiCoreFvLocationPpi+ }+};+ > EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformPpi[] =3D { { > EFI_PEI_PPI_DESCRIPTOR_PPI,@@ -129,6 +142,8 @@ SecPlatformMain ( > ) { EFI_PEI_PPI_DESCRIPTOR *PpiList;+ UINT8 > TopOfTemporaryRamPpiIndex;+ UINT8 *CopyDestination= Pointer; > DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeBase - 0x%x\n", > SecCoreData->BootFirmwareVolumeBase)); DEBUG ((DEBUG_INFO, "FSP > Wrapper BootFirmwareVolumeSize - 0x%x\n", SecCoreData- > >BootFirmwareVolumeSize));@@ -150,13 +165,22 @@ SecPlatformMain ( > // Use middle of Heap as temp buffer, it will be copied by caller. /= / Do not > use Stack, because it will cause wrong calculation on stack by PeiCore = //- > PpiList =3D (VOID *)((UINTN)SecCoreData->PeiTemporaryRamBase + > (UINTN)SecCoreData->PeiTemporaryRamSize/2);- CopyMem (PpiList, > mPeiSecPlatformPpi, sizeof(mPeiSecPlatformPpi));-+ PpiList =3D (VOID > *)((UINTN) SecCoreData->PeiTemporaryRamBase + (UINTN) SecCoreData- > >PeiTemporaryRamSize/2);+ CopyDestinationPointer =3D (UINT8 *) PpiList;+ > TopOfTemporaryRamPpiIndex =3D 0;+ if ((PcdGet8 (PcdFspModeSelection) =3D= =3D > 0) && PcdGetBool (PcdFspDispatchModeUseFspPeiMain)) {+ //+ // In > Dispatch mode, wrapper should provide PeiCoreFvLocationPpi.+ //+ > CopyMem (CopyDestinationPointer, mPeiCoreFvLocationPpiList, sizeof > (mPeiCoreFvLocationPpiList));+ TopOfTemporaryRamPpiIndex =3D 1;+ > CopyDestinationPointer +=3D sizeof (mPeiCoreFvLocationPpiList);+ }+ > CopyMem (CopyDestinationPointer, mPeiSecPlatformPpi, sizeof > (mPeiSecPlatformPpi)); // // Patch TopOfTemporaryRamPpi //- > PpiList[0].Ppi =3D (VOID *)((UINTN)SecCoreData->TemporaryRamBase + > SecCoreData->TemporaryRamSize);+ > PpiList[TopOfTemporaryRamPpiIndex].Ppi =3D (VOID *)((UINTN) SecCoreData- > >TemporaryRamBase + SecCoreData->TemporaryRamSize); return PpiList; > }diff --git > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatf > ormSecLib/SecFspWrapperPlatformSecLib.inf > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatf > ormSecLib/SecFspWrapperPlatformSecLib.inf > index 3f5a63f273..02c720c73d 100644 > --- > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatf > ormSecLib/SecFspWrapperPlatformSecLib.inf > +++ > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat > +++ formSecLib/SecFspWrapperPlatformSecLib.inf > @@ -72,18 +72,20 @@ > BoardInitLib SecBoardInitLib TestPointCheckLib+ > PeiServicesTablePointerLib [Ppis] gEfiSecPlatformInformationPpiGuid = ## > CONSUMES gPeiSecPerformancePpiGuid ## CONSUMES > gTopOfTemporaryRamPpiGuid ## PRODUCES > gEfiPeiFirmwareVolumeInfoPpiGuid ## PRODUCES+ > gFspTempRamExitPpiGuid ## CONSUMES [Pcd] > gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize ## > CONSUMES gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress > ## CONSUMES gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize > ## CONSUMES- > gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable ## > CONSUMES+ > gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable ## > CONSUMES [FixedPcd] > gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress ## > CONSUMES@@ -91,3 +93,6 @@ > gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset ## > CONSUMES > gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress ## > CONSUMES gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize > ## CONSUMES+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress > ## CONSUMES+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection > ## CONSUMES+ > gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain > ## CONSUMESdiff --git > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatf > ormSecLib/SecTempRamDone.c > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatf > ormSecLib/SecTempRamDone.c > index cde8a80a4e..922e4ec204 100644 > --- > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatf > ormSecLib/SecTempRamDone.c > +++ > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat > +++ formSecLib/SecTempRamDone.c > @@ -1,7 +1,7 @@ > /** @file Provide SecTemporaryRamDone function. -Copyright (c) 2017, > Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 2019, In= tel > Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clau= se- > Patent **/@@ -9,6 +9,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > #include #include +#include > #include #include > @@ -17,6 +18,7 @@ SPDX-License-Identifier: BSD-2- > Clause-Patent #include #include > #include +#include > /** This interface disables > temporary memory in SEC Phase.@@ -29,17 +31,41 @@ > SecPlatformDisableTemporaryMemory ( > { EFI_STATUS Status; VOID *TempR= amExitParam;+ > CONST EFI_PEI_SERVICES **PeiServices;+ FSP_TEMP_RAM_EXIT_PPI > *TempRamExitPpi;++ DEBUG ((DEBUG_INFO, > "SecPlatformDisableTemporaryMemory enter\n")); - DEBUG((DEBUG_INFO, > "SecPlatformDisableTemporaryMemory enter\n"));- Status =3D > BoardInitBeforeTempRamExit (); ASSERT_EFI_ERROR (Status); - > TempRamExitParam =3D UpdateTempRamExitParam ();- Status =3D > CallTempRamExit (TempRamExitParam);- DEBUG((DEBUG_INFO, > "TempRamExit status: 0x%x\n", Status));- ASSERT_EFI_ERROR(Status);- + = if > (PcdGet8 (PcdFspModeSelection) =3D=3D 1) {+ //+ // FSP API mode+ = //+ > TempRamExitParam =3D UpdateTempRamExitParam ();+ Status =3D > CallTempRamExit (TempRamExitParam);+ DEBUG ((DEBUG_INFO, > "TempRamExit status: 0x%x\n", Status));+ ASSERT_EFI_ERROR (Status);+ = } > else {+ //+ // FSP Dispatch mode+ //+ PeiServices =3D > GetPeiServicesTablePointer ();+ Status =3D (*PeiServices)->LocatePpi (= + > PeiServices,+ &gFspTempRamExitPpiGuid,+ = 0,+ > NULL,+ (VOID **) &TempRamExitPpi+ = );+ > ASSERT_EFI_ERROR (Status);+ if (EFI_ERROR (Status)) {+ return;+ = }+ > TempRamExitPpi->TempRamExit (NULL);+ }+ Status =3D > BoardInitAfterTempRamExit (); ASSERT_EFI_ERROR (Status); diff --git > a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec > b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec > index 92bda3784f..fb069145ce 100644 > --- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec > +++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec > @@ -71,8 +71,6 @@ SetCacheMtrrLib|Include/Library/SetCacheMtrrLib.h > [PcdsFixedAtBuild, PcdsPatchableInModule] - > gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|FALSE|BOOLE > AN|0x80000008- > gMinPlatformPkgTokenSpaceGuid.PcdFspMaxUpdSize|0x00000000|UINT32| > 0x80000000 > gMinPlatformPkgTokenSpaceGuid.PcdFspReservedSizeOnStackTop|0x00000 > 040|UINT32|0x80000001 > gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0x00000000|UINT3 > 2|0x80000002@@ -274,6 +272,32 @@ > gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0|UINT32|0x90000 > 019 > # gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4|UINT8|0xF00000A0 > + ## FSP Boot Mode Selector+ # FALSE: The board is not a FSP wrapper (F= SP > binary not used)+ # TRUE: The board is a FSP wrapper (FSP binary is use= d)+ > #+ > gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|FALSE|BOOLE > AN|0x80000008++ ## FSP Dispatch Mode: Use the PEI Main Binary Included > in FSP-M+ # FALSE: The PEI Main included in FvPreMemory is used to > dispatch all PEIMs+ # (both inside FSP and outside FSP).+ # = Pros:+ # > * PEI Main is re-built from source and is always the latest version+ # = * > Platform code can link any desired LibraryClass to PEI Main+ # = (Ex: > Custom DebugLib instance, SerialPortLib, etc.)+ # Cons:+ # = * The PEI > Main being used to execute FSP PEIMs is not the PEI Main+ # t= hat the > FSP PEIMs were tested with, adding risk of breakage.+ # * Two c= opies of > PEI Main will exist in the final binary,+ # #1 in FSP-M, #2 i= n > FvPreMemory. The copy in FSP-M is never+ # executed, wasting > space.+ #+ # TRUE: The PEI Main included in FSP is used to disp= atch > all PEIMs+ # (both inside FSP and outside FSP). PEI Main will not= be > included in+ # FvPreMemory. This is the default and is the recomm= ended > choice.+ #+ > gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain|TR > UE|BOOLEAN|0xF00000A8+ [PcdsFeatureFlag] > gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit > |FALSE|BOOLEAN|0xF00000A1-- > 2.24.0.windows.2