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On Sat, 26 Feb 2022 04:43:37 +0000,
Ashish Singhal <ashishsingha@nvidia.com> wrote:
>
> Even with MMU turned off, instruction cache can speculate
> and fetch instructions. This can cause a crash if region
> being executed has been modified recently. With this patch,

Modified by what?

[Singhal, Ashish]: Modified by MMU code in terms of their memory attributes.

> we ensure that instruction cache is invalidated right after
> MMU has been enabled and any potentially stale instruction
> fetched earlier has been discarded.
>
> This is specially helpful when the memory attributes of a
> region in MMU are being changed and some instructions

Changed from what to what else? Are you concerned with the content of
the memory being changed? Or by the attribute being changed? Or both?

changed to ROE for the code section and RWnE for the data section.

> operating on the region are prefetched in the instruction
> cache.

I don't see how this fixes anything. Yes, speculation occurs. But if
your icache contains crap, how is it safe to first enable the MMU
first and then nuke the icache? You could well be executing garbage at
that point.

Worse case, and assuming that you have an aliasing VIVT icache, this
will invalidate fetches that would alias with the layout of the memory
once the MMU is on. But as far as I know, EDK2 is entirely identity
mapped. I also don't think it uses instruction patching.

Finally, if you see speculative accesses on regions that shouldn't be
accessed as such, it could well be because the code is placed too
close to such a region, as mentioned in the ARM ARM (DDI0487H_a, page
D5-4828):

<quote>
Behavior of instruction fetches when all associated stages of
translation are disabled

[...]

To ensure architectural compliance, software must ensure that both of
the following apply:

• Instructions that will be executed when all associated stages of
  address translation are disabled are located in blocks of the
  address space, of the translation granule size, that contain only
  memory that is tolerant to speculative accesses.

• Each block of the address space, of the translation granule size,
  that immediately follows a similar block that holds instructions
  that will be executed when all associated stages address translation
  are disabled, contains only memory that is tolerant to speculative
  accesses.
</quote>

[Singhal, Ashish]: I do not think this is an issue here.

Thanks,

        M

--
Without deviation from the norm, progress is not possible.