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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,gao.cheng@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: nk9GVNMgM1F2xEtU2FwEnn0rx7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=UM2anDOo; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}") Hi Hao, Thanks for the support. Best Regards, Gao -----Original Message----- From: Wu, Hao A =20 Sent: Thursday, September 28, 2023 10:07 AM To: devel@edk2.groups.io; Wu, Hao A ; Cheng, Gao Cc: Ni, Ray ; Wang, Jian J ; Gao, = Liming Subject: RE: [edk2-devel] [PATCH v2] MdeModulePkg/Xhci: Skip size round up = for TRB during address translation Patch merged via: PR - https://github.com/tianocore/edk2/pull/4875 Commit - https://github.com/tianocore/edk2/commit/f36e1ec1f0a5fd3be84913e09= 181d7813444b620 Best Regards, Hao Wu > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of Wu, Hao=20 > A > Sent: Wednesday, September 27, 2023 9:05 AM > To: Cheng, Gao ; devel@edk2.groups.io > Cc: Ni, Ray ; Wang, Jian J ;=20 > Gao, Liming > Subject: Re: [edk2-devel] [PATCH v2] MdeModulePkg/Xhci: Skip size=20 > round up for TRB during address translation >=20 > Reviewed-by: Hao A Wu >=20 > Best Regards, > Hao Wu >=20 > > -----Original Message----- > > From: Cheng, Gao > > Sent: Tuesday, September 26, 2023 4:25 PM > > To: devel@edk2.groups.io > > Cc: Cheng, Gao ; Wu, Hao A > ; > > Ni, Ray ; Wang, Jian J ;=20 > > Gao, Liming > > Subject: [PATCH v2] MdeModulePkg/Xhci: Skip size round up for TRB=20 > > during address translation > > > > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D4560 > > > > > > > > TRB Template is 16 bytes. When boundary checking is 64 bytes for=20 > > xHCI > > > > device/host memory address, it may exceed xHCI host memory pool and > > > > cause unwanted DXE_ASSERT. Introduce a new input parameter to=20 > > indicate > > > > whether to enforce 64byte size alignment and round up. For TRB case, > > > > should set it to FALSE to skip the size round up. > > > > > > > > Signed-off-by: Gao Cheng > > > > Cc: Hao A Wu > > > > Cc: Ray Ni > > > > Cc: Jian J Wang > > > > Cc: Liming Gao > > > > --- > > > > MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c | 24 ++++++++--- > > > > MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h | 8 +++- > > > > MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c | 54=20 > > +++++++++++++----------- > > > > MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.c | 24 ++++++++--- > > > > MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.h | 8 +++- > > > > MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c | 48 +++++++++++---------- > > > > 6 files changed, 103 insertions(+), 63 deletions(-) > > > > > > > > diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c > > b/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c > > > > index d0ad1582e4..b54187ec22 100644 > > > > --- a/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c > > > > +++ b/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c > > > > @@ -226,6 +226,7 @@ UsbHcAllocMemFromBlock ( > > > > @param Pool The memory pool of the host controller. > > > > @param Mem The pointer to host memory. > > > > @param Size The size of the memory region. > > > > + @param Alignment Alignment the size to USBHC_MEM_UNIT bytes. > > > > > > > > @return The pci memory address > > > > > > > > @@ -234,7 +235,8 @@ EFI_PHYSICAL_ADDRESS > > > > UsbHcGetPciAddrForHostAddr ( > > > > IN USBHC_MEM_POOL *Pool, > > > > IN VOID *Mem, > > > > - IN UINTN Size > > > > + IN UINTN Size, > > > > + IN BOOLEAN Alignment > > > > ) > > > > { > > > > USBHC_MEM_BLOCK *Head; > > > > @@ -243,8 +245,12 @@ UsbHcGetPciAddrForHostAddr ( > > > > EFI_PHYSICAL_ADDRESS PhyAddr; > > > > UINTN Offset; > > > > > > > > - Head =3D Pool->Head; > > > > - AllocSize =3D USBHC_MEM_ROUND (Size); > > > > + Head =3D Pool->Head; > > > > + if (Alignment) { > > > > + AllocSize =3D USBHC_MEM_ROUND (Size); > > > > + } else { > > > > + AllocSize =3D Size; > > > > + } > > > > > > > > if (Mem =3D=3D NULL) { > > > > return 0; > > > > @@ -275,6 +281,7 @@ UsbHcGetPciAddrForHostAddr ( > > > > @param Pool The memory pool of the host controller. > > > > @param Mem The pointer to pci memory. > > > > @param Size The size of the memory region. > > > > + @param Alignment Alignment the size to USBHC_MEM_UNIT bytes. > > > > > > > > @return The host memory address > > > > > > > > @@ -283,7 +290,8 @@ EFI_PHYSICAL_ADDRESS > > > > UsbHcGetHostAddrForPciAddr ( > > > > IN USBHC_MEM_POOL *Pool, > > > > IN VOID *Mem, > > > > - IN UINTN Size > > > > + IN UINTN Size, > > > > + IN BOOLEAN Alignment > > > > ) > > > > { > > > > USBHC_MEM_BLOCK *Head; > > > > @@ -292,8 +300,12 @@ UsbHcGetHostAddrForPciAddr ( > > > > EFI_PHYSICAL_ADDRESS HostAddr; > > > > UINTN Offset; > > > > > > > > - Head =3D Pool->Head; > > > > - AllocSize =3D USBHC_MEM_ROUND (Size); > > > > + Head =3D Pool->Head; > > > > + if (Alignment) { > > > > + AllocSize =3D USBHC_MEM_ROUND (Size); > > > > + } else { > > > > + AllocSize =3D Size; > > > > + } > > > > > > > > if (Mem =3D=3D NULL) { > > > > return 0; > > > > diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h > > b/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h > > > > index c85b0b919f..b21bf9da3e 100644 > > > > --- a/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h > > > > +++ b/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h > > > > @@ -129,6 +129,7 @@ UsbHcFreeMem ( > > > > @param Pool The memory pool of the host controller. > > > > @param Mem The pointer to host memory. > > > > @param Size The size of the memory region. > > > > + @param Alignment Alignment the size to USBHC_MEM_UNIT bytes. > > > > > > > > @return The pci memory address > > > > > > > > @@ -137,7 +138,8 @@ EFI_PHYSICAL_ADDRESS > > > > UsbHcGetPciAddrForHostAddr ( > > > > IN USBHC_MEM_POOL *Pool, > > > > IN VOID *Mem, > > > > - IN UINTN Size > > > > + IN UINTN Size, > > > > + IN BOOLEAN Alignment > > > > ); > > > > > > > > /** > > > > @@ -146,6 +148,7 @@ UsbHcGetPciAddrForHostAddr ( > > > > @param Pool The memory pool of the host controller. > > > > @param Mem The pointer to pci memory. > > > > @param Size The size of the memory region. > > > > + @param Alignment Alignment the size to USBHC_MEM_UNIT bytes. > > > > > > > > @return The host memory address > > > > > > > > @@ -154,7 +157,8 @@ EFI_PHYSICAL_ADDRESS > > > > UsbHcGetHostAddrForPciAddr ( > > > > IN USBHC_MEM_POOL *Pool, > > > > IN VOID *Mem, > > > > - IN UINTN Size > > > > + IN UINTN Size, > > > > + IN BOOLEAN Alignment > > > > ); > > > > > > > > /** > > > > diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c > > b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c > > > > index 53421e64a8..c2be171780 100644 > > > > --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c > > > > +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c > > > > @@ -588,7 +588,7 @@ XhcInitSched ( > > > > // Some 3rd party XHCI external cards don't support single=20 > > 64-bytes width register access, > > > > // So divide it to two 32-bytes width register access. > > > > // > > > > - DcbaaPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Dcbaa, > Entries); > > > > + DcbaaPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Dcbaa, > Entries, > > TRUE); > > > > XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET, XHC_LOW_32BIT > (DcbaaPhy)); > > > > XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET + 4, XHC_HIGH_32BIT=20 > > (DcbaaPhy)); > > > > > > > > @@ -607,7 +607,7 @@ XhcInitSched ( > > > > // So we set RCS as inverted PCS init value to let Command Ring=20 > > empty > > > > // > > > > CmdRing =3D (UINT64)(UINTN)Xhc->CmdRing.RingSeg0; > > > > - CmdRingPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, (VOID=20 > > *)(UINTN)CmdRing, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER); > > > > + CmdRingPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, (VOID > > *)(UINTN)CmdRing, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER,=20 > > TRUE); > > > > ASSERT ((CmdRingPhy & 0x3F) =3D=3D 0); > > > > CmdRingPhy |=3D XHC_CRCR_RCS; > > > > // > > > > @@ -809,7 +809,7 @@ CreateEventRing ( > > > > EventRing->EventRingDequeue =3D (TRB_TEMPLATE *)EventRing- > > >EventRingSeg0; > > > > EventRing->EventRingEnqueue =3D (TRB_TEMPLATE *)EventRing- > > >EventRingSeg0; > > > > > > > > - DequeuePhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf,=20 > > Size); > > > > + DequeuePhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size, > > TRUE); > > > > > > > > // > > > > // Software maintains an Event Ring Consumer Cycle State (CCS)=20 > > bit, initializing it to '1' > > > > @@ -829,7 +829,7 @@ CreateEventRing ( > > > > ERSTBase->PtrHi =3D XHC_HIGH_32BIT (DequeuePhy); > > > > ERSTBase->RingTrbSize =3D EVENT_RING_TRB_NUMBER; > > > > > > > > - ERSTPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, ERSTBase, > Size); > > > > + ERSTPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, ERSTBase, > Size, > > TRUE); > > > > > > > > // > > > > // Program the Interrupter Event Ring Segment Table Size (ERSTSZ)=20 > > register > > (5.5.2.3.1) > > > > @@ -913,7 +913,7 @@ CreateTransferRing ( > > > > // > > > > EndTrb =3D (LINK_TRB *)((UINTN)Buf + sizeof (TRB_TEMPLATE) * > (TrbNum > > - 1)); > > > > EndTrb->Type =3D TRB_TYPE_LINK; > > > > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, siz= eof > > (TRB_TEMPLATE) * TrbNum); > > > > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, siz= eof > > (TRB_TEMPLATE) * TrbNum, TRUE); > > > > EndTrb->PtrLo =3D XHC_LOW_32BIT (PhyAddr); > > > > EndTrb->PtrHi =3D XHC_HIGH_32BIT (PhyAddr); > > > > // > > > > @@ -1045,7 +1045,7 @@ IsTransferRingTrb ( > > > > if (CheckedTrb->Type =3D=3D TRB_TYPE_LINK) { > > > > LinkTrb =3D (LINK_TRB *)CheckedTrb; > > > > PhyAddr =3D (EFI_PHYSICAL_ADDRESS)(LinkTrb->PtrLo | LShiftU64 > > ((UINT64)LinkTrb->PtrHi, 32)); > > > > - CheckedTrb =3D (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr > > (Xhc->MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE)); > > > > + CheckedTrb =3D (TRB_TEMPLATE=20 > > + *)(UINTN)UsbHcGetHostAddrForPciAddr > > (Xhc->MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE),=20 > > FALSE); > > > > ASSERT (CheckedTrb =3D=3D Urb->Ring->RingSeg0); > > > > } > > > > } > > > > @@ -1154,7 +1154,7 @@ XhcCheckUrbResult ( > > > > // Need convert pci device address to host address > > > > // > > > > PhyAddr =3D (EFI_PHYSICAL_ADDRESS)(EvtTrb->TRBPtrLo | LShiftU64=20 > > ((UINT64)EvtTrb->TRBPtrHi, 32)); > > > > - TRBPtr =3D (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc= - > > >MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE)); > > > > + TRBPtr =3D (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr=20 > > + (Xhc- > > >MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE), FALSE); > > > > > > > > // > > > > // Update the status of URB including the pending URB, the URB=20 > > that is currently checked, > > > > @@ -1259,7 +1259,7 @@ EXIT: > > > > High =3D XhcReadRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4); > > > > XhcDequeue =3D (UINT64)(LShiftU64 ((UINT64)High, 32) | Low); > > > > > > > > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc- > > >EventRing.EventRingDequeue, sizeof (TRB_TEMPLATE)); > > > > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc- > > >EventRing.EventRingDequeue, sizeof (TRB_TEMPLATE), FALSE); > > > > > > > > if ((XhcDequeue & (~0x0F)) !=3D (PhyAddr & (~0x0F))) { > > > > // > > > > @@ -2280,7 +2280,8 @@ XhcInitializeDeviceSlot ( > > > > PhyAddr =3D UsbHcGetPciAddrForHostAddr ( > > > > Xhc->MemPool, > > > > ((TRANSFER_RING *)(UINTN)Xhc- > > >UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0, > > > > - sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER > > > > + sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER, > > > > + TRUE > > > > ); > > > > InputContext->EP[0].PtrLo =3D XHC_LOW_32BIT (PhyAddr) | BIT0; > > > > InputContext->EP[0].PtrHi =3D XHC_HIGH_32BIT (PhyAddr); > > > > @@ -2298,7 +2299,7 @@ XhcInitializeDeviceSlot ( > > > > // 7) Load the appropriate (Device Slot ID) entry in the Device=20 > > Context > Base > > Address Array (5.4.6) with > > > > // a pointer to the Output Device Context data structure (6.2.1). > > > > // > > > > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > OutputContext, > > sizeof (DEVICE_CONTEXT)); > > > > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > OutputContext, > > sizeof (DEVICE_CONTEXT), TRUE); > > > > // > > > > // Fill DCBAA with PCI device address > > > > // > > > > @@ -2313,7 +2314,7 @@ XhcInitializeDeviceSlot ( > > > > // > > > > gBS->Stall (XHC_RESET_RECOVERY_DELAY); > > > > ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr)); > > > > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xh= c- > > >UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT)); > > > > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xh= c- > > >UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT), TRUE); > > > > CmdTrbAddr.PtrLo =3D XHC_LOW_32BIT (PhyAddr); > > > > CmdTrbAddr.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); > > > > CmdTrbAddr.CycleBit =3D 1; > > > > @@ -2496,7 +2497,8 @@ XhcInitializeDeviceSlot64 ( > > > > PhyAddr =3D UsbHcGetPciAddrForHostAddr ( > > > > Xhc->MemPool, > > > > ((TRANSFER_RING *)(UINTN)Xhc- > > >UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0, > > > > - sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER > > > > + sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER, > > > > + TRUE > > > > ); > > > > InputContext->EP[0].PtrLo =3D XHC_LOW_32BIT (PhyAddr) | BIT0; > > > > InputContext->EP[0].PtrHi =3D XHC_HIGH_32BIT (PhyAddr); > > > > @@ -2514,7 +2516,7 @@ XhcInitializeDeviceSlot64 ( > > > > // 7) Load the appropriate (Device Slot ID) entry in the Device=20 > > Context > Base > > Address Array (5.4.6) with > > > > // a pointer to the Output Device Context data structure (6.2.1). > > > > // > > > > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > OutputContext, > > sizeof (DEVICE_CONTEXT_64)); > > > > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > OutputContext, > > sizeof (DEVICE_CONTEXT_64), TRUE); > > > > // > > > > // Fill DCBAA with PCI device address > > > > // > > > > @@ -2529,7 +2531,7 @@ XhcInitializeDeviceSlot64 ( > > > > // > > > > gBS->Stall (XHC_RESET_RECOVERY_DELAY); > > > > ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr)); > > > > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xh= c- > > >UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64)); > > > > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xh= c- > > >UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64),=20 > > >TRUE); > > > > CmdTrbAddr.PtrLo =3D XHC_LOW_32BIT (PhyAddr); > > > > CmdTrbAddr.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); > > > > CmdTrbAddr.CycleBit =3D 1; > > > > @@ -2964,7 +2966,8 @@ XhcInitializeEndpointContext ( > > > > PhyAddr =3D UsbHcGetPciAddrForHostAddr ( > > > > Xhc->MemPool, > > > > ((TRANSFER_RING *)(UINTN)Xhc- > > >UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0, > > > > - sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER > > > > + sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER, > > > > + TRUE > > > > ); > > > > PhyAddr &=3D ~((EFI_PHYSICAL_ADDRESS)0x0F); > > > > PhyAddr |=3D (EFI_PHYSICAL_ADDRESS)((TRANSFER= _RING > > *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])- > > >RingPCS; > > > > @@ -3166,7 +3169,8 @@ XhcInitializeEndpointContext64 ( > > > > PhyAddr =3D UsbHcGetPciAddrForHostAddr ( > > > > Xhc->MemPool, > > > > ((TRANSFER_RING *)(UINTN)Xhc- > > >UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0, > > > > - sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER > > > > + sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER, > > > > + TRUE > > > > ); > > > > PhyAddr &=3D ~((EFI_PHYSICAL_ADDRESS)0x0F); > > > > PhyAddr |=3D (EFI_PHYSICAL_ADDRESS)((TRANSFER= _RING > > *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])- > > >RingPCS; > > > > @@ -3248,7 +3252,7 @@ XhcSetConfigCmd ( > > > > // configure endpoint > > > > // > > > > ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); > > > > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > > InputContext, sizeof (INPUT_CONTEXT)); > > > > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > > InputContext, sizeof (INPUT_CONTEXT), TRUE); > > > > CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr); > > > > CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); > > > > CmdTrbCfgEP.CycleBit =3D 1; > > > > @@ -3339,7 +3343,7 @@ XhcSetConfigCmd64 ( > > > > // configure endpoint > > > > // > > > > ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); > > > > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > > InputContext, sizeof (INPUT_CONTEXT_64)); > > > > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > > InputContext, sizeof (INPUT_CONTEXT_64), TRUE); > > > > CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr); > > > > CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); > > > > CmdTrbCfgEP.CycleBit =3D 1; > > > > @@ -3513,7 +3517,7 @@ XhcSetTrDequeuePointer ( > > > > // Send stop endpoint command to transit Endpoint from running to=20 > > stop state > > > > // > > > > ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq)); > > > > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, U= rb- > > >Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER)); > > > > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, U= rb- > > >Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER), TRUE); > > > > CmdSetTRDeq.PtrLo =3D XHC_LOW_32BIT (PhyAddr) | Urb->Ring- > >RingPCS; > > > > CmdSetTRDeq.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); > > > > CmdSetTRDeq.CycleBit =3D 1; > > > > @@ -3713,7 +3717,7 @@ XhcSetInterface ( > > > > // 5) Issue and successfully complete a Configure Endpoint Command= . > > > > // > > > > ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); > > > > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > > InputContext, sizeof (INPUT_CONTEXT)); > > > > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > > InputContext, sizeof (INPUT_CONTEXT), TRUE); > > > > CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr); > > > > CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); > > > > CmdTrbCfgEP.CycleBit =3D 1; > > > > @@ -3919,7 +3923,7 @@ XhcSetInterface64 ( > > > > // 5) Issue and successfully complete a Configure Endpoint Command= . > > > > // > > > > ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); > > > > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > > InputContext, sizeof (INPUT_CONTEXT_64)); > > > > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > > InputContext, sizeof (INPUT_CONTEXT_64), TRUE); > > > > CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr); > > > > CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); > > > > CmdTrbCfgEP.CycleBit =3D 1; > > > > @@ -3986,7 +3990,7 @@ XhcEvaluateContext ( > > > > InputContext->EP[0].EPState =3D 0; > > > > > > > > ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu)); > > > > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > > InputContext, sizeof (INPUT_CONTEXT)); > > > > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > > InputContext, sizeof (INPUT_CONTEXT), TRUE); > > > > CmdTrbEvalu.PtrLo =3D XHC_LOW_32BIT (PhyAddr); > > > > CmdTrbEvalu.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); > > > > CmdTrbEvalu.CycleBit =3D 1; > > > > @@ -4047,7 +4051,7 @@ XhcEvaluateContext64 ( > > > > InputContext->EP[0].EPState =3D 0; > > > > > > > > ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu)); > > > > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > > InputContext, sizeof (INPUT_CONTEXT_64)); > > > > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > > InputContext, sizeof (INPUT_CONTEXT_64), TRUE); > > > > CmdTrbEvalu.PtrLo =3D XHC_LOW_32BIT (PhyAddr); > > > > CmdTrbEvalu.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); > > > > CmdTrbEvalu.CycleBit =3D 1; > > > > @@ -4116,7 +4120,7 @@ XhcConfigHubContext ( > > > > InputContext->Slot.MTT =3D MTT; > > > > > > > > ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); > > > > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > > InputContext, sizeof (INPUT_CONTEXT)); > > > > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > > InputContext, sizeof (INPUT_CONTEXT), TRUE); > > > > CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr); > > > > CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); > > > > CmdTrbCfgEP.CycleBit =3D 1; > > > > @@ -4185,7 +4189,7 @@ XhcConfigHubContext64 ( > > > > InputContext->Slot.MTT =3D MTT; > > > > > > > > ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); > > > > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > > InputContext, sizeof (INPUT_CONTEXT_64)); > > > > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > > InputContext, sizeof (INPUT_CONTEXT_64), TRUE); > > > > CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr); > > > > CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); > > > > CmdTrbCfgEP.CycleBit =3D 1; > > > > diff --git a/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.c > > b/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.c > > > > index e779a31138..88db5fe46e 100644 > > > > --- a/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.c > > > > +++ b/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.c > > > > @@ -190,6 +190,7 @@ UsbHcAllocMemFromBlock ( > > > > @param Pool The memory pool of the host controller. > > > > @param Mem The pointer to host memory. > > > > @param Size The size of the memory region. > > > > + @param Alignment Alignment the size to USBHC_MEM_UNIT bytes. > > > > > > > > @return The pci memory address > > > > > > > > @@ -198,7 +199,8 @@ EFI_PHYSICAL_ADDRESS > > > > UsbHcGetPciAddrForHostAddr ( > > > > IN USBHC_MEM_POOL *Pool, > > > > IN VOID *Mem, > > > > - IN UINTN Size > > > > + IN UINTN Size, > > > > + IN BOOLEAN Alignment > > > > ) > > > > { > > > > USBHC_MEM_BLOCK *Head; > > > > @@ -207,8 +209,12 @@ UsbHcGetPciAddrForHostAddr ( > > > > EFI_PHYSICAL_ADDRESS PhyAddr; > > > > UINTN Offset; > > > > > > > > - Head =3D Pool->Head; > > > > - AllocSize =3D USBHC_MEM_ROUND (Size); > > > > + Head =3D Pool->Head; > > > > + if (Alignment) { > > > > + AllocSize =3D USBHC_MEM_ROUND (Size); > > > > + } else { > > > > + AllocSize =3D Size; > > > > + } > > > > > > > > if (Mem =3D=3D NULL) { > > > > return 0; > > > > @@ -239,6 +245,7 @@ UsbHcGetPciAddrForHostAddr ( > > > > @param Pool The memory pool of the host controller. > > > > @param Mem The pointer to pci memory. > > > > @param Size The size of the memory region. > > > > + @param Alignment Alignment the size to USBHC_MEM_UNIT bytes. > > > > > > > > @return The host memory address > > > > > > > > @@ -247,7 +254,8 @@ EFI_PHYSICAL_ADDRESS > > > > UsbHcGetHostAddrForPciAddr ( > > > > IN USBHC_MEM_POOL *Pool, > > > > IN VOID *Mem, > > > > - IN UINTN Size > > > > + IN UINTN Size, > > > > + IN BOOLEAN Alignment > > > > ) > > > > { > > > > USBHC_MEM_BLOCK *Head; > > > > @@ -256,8 +264,12 @@ UsbHcGetHostAddrForPciAddr ( > > > > EFI_PHYSICAL_ADDRESS HostAddr; > > > > UINTN Offset; > > > > > > > > - Head =3D Pool->Head; > > > > - AllocSize =3D USBHC_MEM_ROUND (Size); > > > > + Head =3D Pool->Head; > > > > + if (Alignment) { > > > > + AllocSize =3D USBHC_MEM_ROUND (Size); > > > > + } else { > > > > + AllocSize =3D Size; > > > > + } > > > > > > > > if (Mem =3D=3D NULL) { > > > > return 0; > > > > diff --git a/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.h > > b/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.h > > > > index 2b4c8b19fc..8f760e084e 100644 > > > > --- a/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.h > > > > +++ b/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.h > > > > @@ -68,6 +68,7 @@ typedef struct _USBHC_MEM_POOL { > > > > @param Pool The memory pool of the host controller. > > > > @param Mem The pointer to host memory. > > > > @param Size The size of the memory region. > > > > + @param Alignment Alignment the size to USBHC_MEM_UNIT bytes. > > > > > > > > @return The pci memory address > > > > > > > > @@ -76,7 +77,8 @@ EFI_PHYSICAL_ADDRESS > > > > UsbHcGetPciAddrForHostAddr ( > > > > IN USBHC_MEM_POOL *Pool, > > > > IN VOID *Mem, > > > > - IN UINTN Size > > > > + IN UINTN Size, > > > > + IN BOOLEAN Alignment > > > > ); > > > > > > > > /** > > > > @@ -85,6 +87,7 @@ UsbHcGetPciAddrForHostAddr ( > > > > @param Pool The memory pool of the host controller. > > > > @param Mem The pointer to pci memory. > > > > @param Size The size of the memory region. > > > > + @param Alignment Alignment the size to USBHC_MEM_UNIT bytes. > > > > > > > > @return The host memory address > > > > > > > > @@ -93,7 +96,8 @@ EFI_PHYSICAL_ADDRESS > > > > UsbHcGetHostAddrForPciAddr ( > > > > IN USBHC_MEM_POOL *Pool, > > > > IN VOID *Mem, > > > > - IN UINTN Size > > > > + IN UINTN Size, > > > > + IN BOOLEAN Alignment > > > > ); > > > > > > > > /** > > > > diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c > > b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c > > > > index 8400c90f7a..53272f62dd 100644 > > > > --- a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c > > > > +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c > > > > @@ -675,7 +675,7 @@ XhcPeiCheckUrbResult ( > > > > // Need convert pci device address to host address > > > > // > > > > PhyAddr =3D (EFI_PHYSICAL_ADDRESS)(EvtTrb->TRBPtrLo | LShiftU64=20 > > ((UINT64)EvtTrb->TRBPtrHi, 32)); > > > > - TRBPtr =3D (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc= - > > >MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE)); > > > > + TRBPtr =3D (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr=20 > > + (Xhc- > > >MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE), FALSE); > > > > > > > > // > > > > // Update the status of Urb according to the finished event=20 > > regardless of whether > > > > @@ -766,7 +766,7 @@ EXIT: > > > > High =3D XhcPeiReadRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4); > > > > XhcDequeue =3D (UINT64)(LShiftU64 ((UINT64)High, 32) | Low); > > > > > > > > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc- > > >EventRing.EventRingDequeue, sizeof (TRB_TEMPLATE)); > > > > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc- > > >EventRing.EventRingDequeue, sizeof (TRB_TEMPLATE), FALSE); > > > > > > > > if ((XhcDequeue & (~0x0F)) !=3D (PhyAddr & (~0x0F))) { > > > > // > > > > @@ -1213,7 +1213,8 @@ XhcPeiInitializeDeviceSlot ( > > > > PhyAddr =3D UsbHcGetPciAddrForHostAddr ( > > > > Xhc->MemPool, > > > > ((TRANSFER_RING *)(UINTN)Xhc- > > >UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0, > > > > - sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER > > > > + sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER, > > > > + TRUE > > > > ); > > > > InputContext->EP[0].PtrLo =3D XHC_LOW_32BIT (PhyAddr) | BIT0; > > > > InputContext->EP[0].PtrHi =3D XHC_HIGH_32BIT (PhyAddr); > > > > @@ -1231,7 +1232,7 @@ XhcPeiInitializeDeviceSlot ( > > > > // 7) Load the appropriate (Device Slot ID) entry in the Device=20 > > Context > Base > > Address Array (5.4.6) with > > > > // a pointer to the Output Device Context data structure (6.2.1). > > > > // > > > > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > OutputContext, > > sizeof (DEVICE_CONTEXT)); > > > > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > OutputContext, > > sizeof (DEVICE_CONTEXT), TRUE); > > > > // > > > > // Fill DCBAA with PCI device address > > > > // > > > > @@ -1246,7 +1247,7 @@ XhcPeiInitializeDeviceSlot ( > > > > // > > > > MicroSecondDelay (XHC_RESET_RECOVERY_DELAY); > > > > ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr)); > > > > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xh= c- > > >UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT)); > > > > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xh= c- > > >UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT), TRUE); > > > > CmdTrbAddr.PtrLo =3D XHC_LOW_32BIT (PhyAddr); > > > > CmdTrbAddr.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); > > > > CmdTrbAddr.CycleBit =3D 1; > > > > @@ -1427,7 +1428,8 @@ XhcPeiInitializeDeviceSlot64 ( > > > > PhyAddr =3D UsbHcGetPciAddrForHostAddr ( > > > > Xhc->MemPool, > > > > ((TRANSFER_RING *)(UINTN)Xhc- > > >UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0, > > > > - sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER > > > > + sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER, > > > > + TRUE > > > > ); > > > > InputContext->EP[0].PtrLo =3D XHC_LOW_32BIT (PhyAddr) | BIT0; > > > > InputContext->EP[0].PtrHi =3D XHC_HIGH_32BIT (PhyAddr); > > > > @@ -1445,7 +1447,7 @@ XhcPeiInitializeDeviceSlot64 ( > > > > // 7) Load the appropriate (Device Slot ID) entry in the Device=20 > > Context > Base > > Address Array (5.4.6) with > > > > // a pointer to the Output Device Context data structure (6.2.1). > > > > // > > > > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > OutputContext, > > sizeof (DEVICE_CONTEXT_64)); > > > > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > OutputContext, > > sizeof (DEVICE_CONTEXT_64), TRUE); > > > > // > > > > // Fill DCBAA with PCI device address > > > > // > > > > @@ -1460,7 +1462,7 @@ XhcPeiInitializeDeviceSlot64 ( > > > > // > > > > MicroSecondDelay (XHC_RESET_RECOVERY_DELAY); > > > > ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr)); > > > > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xh= c- > > >UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64)); > > > > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xh= c- > > >UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64),=20 > > >TRUE); > > > > CmdTrbAddr.PtrLo =3D XHC_LOW_32BIT (PhyAddr); > > > > CmdTrbAddr.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); > > > > CmdTrbAddr.CycleBit =3D 1; > > > > @@ -1882,7 +1884,8 @@ XhcPeiSetConfigCmd ( > > > > PhyAddr =3D UsbHcGetPciAddrForHostAddr ( > > > > Xhc->MemPool, > > > > ((TRANSFER_RING *)(UINTN)Xhc- > > >UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0, > > > > - sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER > > > > + sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER, > > > > + TRUE > > > > ); > > > > PhyAddr &=3D ~((EFI_PHYSICAL_ADDRESS)0x0F); > > > > PhyAddr |=3D (EFI_PHYSICAL_ADDRESS)((TRANSF= ER_RING > > *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])- > > >RingPCS; > > > > @@ -1901,7 +1904,7 @@ XhcPeiSetConfigCmd ( > > > > // configure endpoint > > > > // > > > > ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); > > > > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > > InputContext, sizeof (INPUT_CONTEXT)); > > > > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > > InputContext, sizeof (INPUT_CONTEXT), TRUE); > > > > CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr); > > > > CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); > > > > CmdTrbCfgEP.CycleBit =3D 1; > > > > @@ -2108,7 +2111,8 @@ XhcPeiSetConfigCmd64 ( > > > > PhyAddr =3D UsbHcGetPciAddrForHostAddr ( > > > > Xhc->MemPool, > > > > ((TRANSFER_RING *)(UINTN)Xhc- > > >UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0, > > > > - sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER > > > > + sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER, > > > > + TRUE > > > > ); > > > > > > > > PhyAddr &=3D ~((EFI_PHYSICAL_ADDRESS)0x0F); > > > > @@ -2129,7 +2133,7 @@ XhcPeiSetConfigCmd64 ( > > > > // configure endpoint > > > > // > > > > ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); > > > > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > > InputContext, sizeof (INPUT_CONTEXT_64)); > > > > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > > InputContext, sizeof (INPUT_CONTEXT_64), TRUE); > > > > CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr); > > > > CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); > > > > CmdTrbCfgEP.CycleBit =3D 1; > > > > @@ -2184,7 +2188,7 @@ XhcPeiEvaluateContext ( > > > > InputContext->EP[0].MaxPacketSize =3D MaxPacketSize; > > > > > > > > ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu)); > > > > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > > InputContext, sizeof (INPUT_CONTEXT)); > > > > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > > InputContext, sizeof (INPUT_CONTEXT), TRUE); > > > > CmdTrbEvalu.PtrLo =3D XHC_LOW_32BIT (PhyAddr); > > > > CmdTrbEvalu.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); > > > > CmdTrbEvalu.CycleBit =3D 1; > > > > @@ -2239,7 +2243,7 @@ XhcPeiEvaluateContext64 ( > > > > InputContext->EP[0].MaxPacketSize =3D MaxPacketSize; > > > > > > > > ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu)); > > > > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > > InputContext, sizeof (INPUT_CONTEXT_64)); > > > > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > > InputContext, sizeof (INPUT_CONTEXT_64), TRUE); > > > > CmdTrbEvalu.PtrLo =3D XHC_LOW_32BIT (PhyAddr); > > > > CmdTrbEvalu.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); > > > > CmdTrbEvalu.CycleBit =3D 1; > > > > @@ -2308,7 +2312,7 @@ XhcPeiConfigHubContext ( > > > > InputContext->Slot.MTT =3D MTT; > > > > > > > > ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); > > > > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > > InputContext, sizeof (INPUT_CONTEXT)); > > > > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > > InputContext, sizeof (INPUT_CONTEXT), TRUE); > > > > CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr); > > > > CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); > > > > CmdTrbCfgEP.CycleBit =3D 1; > > > > @@ -2377,7 +2381,7 @@ XhcPeiConfigHubContext64 ( > > > > InputContext->Slot.MTT =3D MTT; > > > > > > > > ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); > > > > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > > InputContext, sizeof (INPUT_CONTEXT_64)); > > > > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > > InputContext, sizeof (INPUT_CONTEXT_64), TRUE); > > > > CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr); > > > > CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); > > > > CmdTrbCfgEP.CycleBit =3D 1; > > > > @@ -2522,7 +2526,7 @@ XhcPeiSetTrDequeuePointer ( > > > > // Send stop endpoint command to transit Endpoint from running to=20 > > stop state > > > > // > > > > ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq)); > > > > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, U= rb- > > >Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER)); > > > > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, U= rb- > > >Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER), TRUE); > > > > CmdSetTRDeq.PtrLo =3D XHC_LOW_32BIT (PhyAddr) | Urb->Ring- > >RingPCS; > > > > CmdSetTRDeq.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); > > > > CmdSetTRDeq.CycleBit =3D 1; > > > > @@ -2682,7 +2686,7 @@ XhcPeiCreateEventRing ( > > > > ASSERT (((UINTN)Buf & 0x3F) =3D=3D 0); > > > > ZeroMem (Buf, Size); > > > > > > > > - DequeuePhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf,=20 > > Size); > > > > + DequeuePhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size, > > TRUE); > > > > > > > > EventRing->EventRingSeg0 =3D Buf; > > > > EventRing->TrbNumber =3D EVENT_RING_TRB_NUMBER; > > > > @@ -2707,7 +2711,7 @@ XhcPeiCreateEventRing ( > > > > ERSTBase->PtrHi =3D XHC_HIGH_32BIT (DequeuePhy); > > > > ERSTBase->RingTrbSize =3D EVENT_RING_TRB_NUMBER; > > > > > > > > - ERSTPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size); > > > > + ERSTPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size, > TRUE); > > > > > > > > // > > > > // Program the Interrupter Event Ring Segment Table Size (ERSTSZ)=20 > > register > > (5.5.2.3.1) > > > > @@ -2855,7 +2859,7 @@ XhcPeiCreateTransferRing ( > > > > // > > > > EndTrb =3D (LINK_TRB *)((UINTN)Buf + sizeof (TRB_TEMPLATE) * > (TrbNum > > - 1)); > > > > EndTrb->Type =3D TRB_TYPE_LINK; > > > > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, siz= eof > > (TRB_TEMPLATE) * TrbNum); > > > > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, siz= eof > > (TRB_TEMPLATE) * TrbNum, TRUE); > > > > EndTrb->PtrLo =3D XHC_LOW_32BIT (PhyAddr); > > > > EndTrb->PtrHi =3D XHC_HIGH_32BIT (PhyAddr); > > > > // > > > > @@ -2988,7 +2992,7 @@ XhcPeiInitSched ( > > > > // Some 3rd party XHCI external cards don't support single=20 > > 64-bytes width register access, > > > > // So divide it to two 32-bytes width register access. > > > > // > > > > - DcbaaPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Dcbaa,=20 > > Size); > > > > + DcbaaPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Dcbaa, Size, > > TRUE); > > > > XhcPeiWriteOpReg (Xhc, XHC_DCBAAP_OFFSET, XHC_LOW_32BIT=20 > > (DcbaaPhy)); > > > > XhcPeiWriteOpReg (Xhc, XHC_DCBAAP_OFFSET + 4, XHC_HIGH_32BIT=20 > > (DcbaaPhy)); > > > > > > > > @@ -3006,7 +3010,7 @@ XhcPeiInitSched ( > > > > // Transfer Ring it checks for a Cycle bit transition. If a=20 > > transition detected, the ring is empty. > > > > // So we set RCS as inverted PCS init value to let Command Ring=20 > > empty > > > > // > > > > - CmdRingPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc- > > >CmdRing.RingSeg0, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER); > > > > + CmdRingPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc- > > >CmdRing.RingSeg0, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER, > > TRUE); > > > > ASSERT ((CmdRingPhy & 0x3F) =3D=3D 0); > > > > CmdRingPhy |=3D XHC_CRCR_RCS; > > > > // > > > > -- > > > > 2.42.0.windows.2 > > > > >=20 >=20 >=20 >=20 >=20 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#109134): https://edk2.groups.io/g/devel/message/109134 Mute This Topic: https://groups.io/mt/101591675/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-