From: "De Leon Vasquez, Lorena R" <lorena.r.de.leon.vasquez@intel.com>
To: "Gao, Liming" <liming.gao@intel.com>,
"devel@edk2.groups.io" <devel@edk2.groups.io>,
"Lohr, Paul A" <paul.a.lohr@intel.com>,
"Yao, Jiewen" <jiewen.yao@intel.com>
Cc: "Kinney, Michael D" <michael.d.kinney@intel.com>
Subject: Re: [edk2-devel] [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU generic bug fix
Date: Tue, 4 Aug 2020 15:15:33 +0000 [thread overview]
Message-ID: <BYAPR11MB2982C7ABE46892C335E89E64D04A0@BYAPR11MB2982.namprd11.prod.outlook.com> (raw)
In-Reply-To: <CY4PR11MB152657C7F01463C864F8055B804E0@CY4PR11MB1526.namprd11.prod.outlook.com>
[-- Attachment #1.1: Type: text/plain, Size: 8339 bytes --]
Hi Liming,
I’ve update the name
Thanks,
Lorena
From: Gao, Liming <liming.gao@intel.com>
Sent: Friday, July 31, 2020 2:30 AM
To: De Leon Vasquez, Lorena R <lorena.r.de.leon.vasquez@intel.com>; devel@edk2.groups.io; Lohr, Paul A <paul.a.lohr@intel.com>; Yao, Jiewen <jiewen.yao@intel.com>
Cc: Kinney, Michael D <michael.d.kinney@intel.com>
Subject: RE: [edk2-devel] [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU generic bug fix
Lorena:
Thanks for your update. Can you correct name style as Star Zeng <star.zeng@intel.com<mailto:star.zeng@intel.com>> for below message?
Suggested-by: Star Zeng star.zeng@intel.com<mailto:star.zeng@intel.com>
Signed-off-by: lorena.r.de.leon.vazquez@intel.com<mailto:lorena.r.de.leon.vazquez@intel.com>
Thanks
Liming
From: De Leon Vasquez, Lorena R <lorena.r.de.leon.vasquez@intel.com<mailto:lorena.r.de.leon.vasquez@intel.com>>
Sent: 2020年7月29日 23:23
To: Gao, Liming <liming.gao@intel.com<mailto:liming.gao@intel.com>>; devel@edk2.groups.io<mailto:devel@edk2.groups.io>; Lohr, Paul A <paul.a.lohr@intel.com<mailto:paul.a.lohr@intel.com>>; Yao, Jiewen <jiewen.yao@intel.com<mailto:jiewen.yao@intel.com>>
Cc: Kinney, Michael D <michael.d.kinney@intel.com<mailto:michael.d.kinney@intel.com>>
Subject: RE: [edk2-devel] [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU generic bug fix
I’ve attached patch with modifications suggested
From: Gao, Liming <liming.gao@intel.com<mailto:liming.gao@intel.com>>
Sent: Thursday, July 9, 2020 7:45 AM
To: De Leon Vazquez, Lorena R <lorena.r.de.leon.vazquez@intel.com<mailto:lorena.r.de.leon.vazquez@intel.com>>; devel@edk2.groups.io<mailto:devel@edk2.groups.io>; Lohr, Paul A <paul.a.lohr@intel.com<mailto:paul.a.lohr@intel.com>>; Yao, Jiewen <jiewen.yao@intel.com<mailto:jiewen.yao@intel.com>>
Cc: Kinney, Michael D <michael.d.kinney@intel.com<mailto:michael.d.kinney@intel.com>>
Subject: RE: [edk2-devel] [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU generic bug fix
Lorena:
I have one minor comment on this patch. The error return status should be EFI_UNSUPPORTED.
+ return error;
==>
return EFI_UNSUPPORTED;
Thanks
Liming
From: De Leon Vazquez, Lorena R <lorena.r.de.leon.vazquez@intel.com<mailto:lorena.r.de.leon.vazquez@intel.com>>
Sent: Tuesday, July 7, 2020 1:24 AM
To: Gao, Liming <liming.gao@intel.com<mailto:liming.gao@intel.com>>; devel@edk2.groups.io<mailto:devel@edk2.groups.io>; Lohr, Paul A <paul.a.lohr@intel.com<mailto:paul.a.lohr@intel.com>>; Yao, Jiewen <jiewen.yao@intel.com<mailto:jiewen.yao@intel.com>>
Cc: Kinney, Michael D <michael.d.kinney@intel.com<mailto:michael.d.kinney@intel.com>>
Subject: RE: [edk2-devel] [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU generic bug fix
Hi Liming,
I’ve attached the patch
Thanks,
Lorena
From: Gao, Liming <liming.gao@intel.com<mailto:liming.gao@intel.com>>
Sent: Thursday, July 2, 2020 8:54 PM
To: devel@edk2.groups.io<mailto:devel@edk2.groups.io>; Lohr, Paul A <paul.a.lohr@intel.com<mailto:paul.a.lohr@intel.com>>; Yao, Jiewen <jiewen.yao@intel.com<mailto:jiewen.yao@intel.com>>; De Leon Vazquez, Lorena R <lorena.r.de.leon.vazquez@intel.com<mailto:lorena.r.de.leon.vazquez@intel.com>>
Cc: Kinney, Michael D <michael.d.kinney@intel.com<mailto:michael.d.kinney@intel.com>>
Subject: RE: [edk2-devel] [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU generic bug fix
Paul:
This patch is missing to be merged.
Lorena:
I can’t extract the patch from the mail. Can you send the patch to me? I can help merge it.
Thanks
Liming
From: devel@edk2.groups.io<mailto:devel@edk2.groups.io> <devel@edk2.groups.io<mailto:devel@edk2.groups.io>> On Behalf Of Lohr, Paul A
Sent: Thursday, July 2, 2020 9:56 PM
To: devel@edk2.groups.io<mailto:devel@edk2.groups.io>; Yao, Jiewen <jiewen.yao@intel.com<mailto:jiewen.yao@intel.com>>; De Leon Vazquez, Lorena R <lorena.r.de.leon.vazquez@intel.com<mailto:lorena.r.de.leon.vazquez@intel.com>>
Cc: Kinney, Michael D <michael.d.kinney@intel.com<mailto:michael.d.kinney@intel.com>>
Subject: Re: [edk2-devel] [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU generic bug fix
Hello,
It seems this did not get checked in. Is there something wrong with the patch itself? Or was this simply submitted incorrectly? I don’t see a Bugzilla associated with it is why I ask.
Paul A. Lohr - Server Firmware Enabling
512.239.9073 (cell)
512.794.5044 (work)
From: devel@edk2.groups.io<mailto:devel@edk2.groups.io> <devel@edk2.groups.io<mailto:devel@edk2.groups.io>> On Behalf Of Yao, Jiewen
Sent: Monday, March 2, 2020 5:46 PM
To: De Leon Vazquez, Lorena R <lorena.r.de.leon.vazquez@intel.com<mailto:lorena.r.de.leon.vazquez@intel.com>>; devel@edk2.groups.io<mailto:devel@edk2.groups.io>
Cc: Kinney, Michael D <michael.d.kinney@intel.com<mailto:michael.d.kinney@intel.com>>
Subject: Re: [edk2-devel] [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU generic bug fix
Reviewed-by: jiewen.yao@intel.com<mailto:jiewen.yao@intel.com>
From: De Leon Vazquez, Lorena R <lorena.r.de.leon.vazquez@intel.com<mailto:lorena.r.de.leon.vazquez@intel.com>>
Sent: Tuesday, March 3, 2020 7:04 AM
To: devel@edk2.groups.io<mailto:devel@edk2.groups.io>
Cc: Yao, Jiewen <jiewen.yao@intel.com<mailto:jiewen.yao@intel.com>>; Kinney, Michael D <michael.d.kinney@intel.com<mailto:michael.d.kinney@intel.com>>
Subject: [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU generic bug fix
Looks like Addresswidth is BIT wise values. Right now these values are not used any
Suggested-by: Star Zeng star.zeng@intel.com<mailto:star.zeng@intel.com>
Signed-off-by: lorena.r.de.leon.vazquez@intel.com<mailto:lorena.r.de.leon.vazquez@intel.com>
--
.../Feature/VTd/IntelVTdDxe/TranslationTable.c | 11 ++++-------
.../Feature/VTd/IntelVTdDxe/TranslationTableEx.c | 11 ++++-------
2 files changed, 8 insertions(+), 14 deletions(-)
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
index cc970c0..61fbb4a 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
@@ -128,14 +128,11 @@ CreateContextEntry (
DEBUG ((DEBUG_INFO,"Source: S%04x B%02x D%02x F%02x\n", mVtdUnitInformation[VtdIndex].Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function));
- switch (mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW) {
- case BIT1:
- ContextEntry->Bits.AddressWidth = 0x1;
- break;
- case BIT2:
- ContextEntry->Bits.AddressWidth = 0x2;
- break;
+ if ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) == 0) {
+ DEBUG((DEBUG_ERROR, "!!!! 4-level page-table is not supported on VTD %d !!!!\n", VtdIndex));
+ return error;
}
+ ContextEntry->Bits.AddressWidth = 0x2;
}
FlushPageTableMemory (VtdIndex, (UINTN)mVtdUnitInformation[VtdIndex].RootEntryTable, EFI_PAGES_TO_SIZE(EntryTablePages));
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c
index 0da1611..6bd31b7 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c
@@ -78,14 +78,11 @@ CreateExtContextEntry (
DEBUG ((DEBUG_INFO,"DOMAIN: S%04x, B%02x D%02x F%02x\n", mVtdUnitInformation[VtdIndex].Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function));
- switch (mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW) {
- case BIT1:
- ExtContextEntry->Bits.AddressWidth = 0x1;
- break;
- case BIT2:
- ExtContextEntry->Bits.AddressWidth = 0x2;
- break;
+ if ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) == 0) {
+ DEBUG((DEBUG_ERROR, "!!!! 4-level page-table is not supported on VTD %d !!!!\n", VtdIndex));
+ return error;
}
+ ContextEntry->Bits.AddressWidth = 0x2;
}
FlushPageTableMemory (VtdIndex, (UINTN)mVtdUnitInformation[VtdIndex].ExtRootEntryTable, EFI_PAGES_TO_SIZE(EntryTablePages));
--
2.21.0.windows.1
[-- Attachment #1.2: Type: text/html, Size: 26188 bytes --]
[-- Attachment #2: 0001-IntelSiliconPkg-IOMMU-generic-bug-fix.patch --]
[-- Type: application/octet-stream, Size: 3087 bytes --]
From 1326deb9c1d035b9b815f11aa052f7d4a5066585 Mon Sep 17 00:00:00 2001
From: lorena de leon <lorena.r.de.leon.vazquez@intel.com>
Date: Tue, 4 Aug 2020 10:05:02 -0500
Subject: [Patch V3] IntelSiliconPkg: IOMMU generic bug fix
Looks like Addresswidth is BIT wise values. Right now these values are not used any
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2401
Suggested-by: Star Zeng <star.zeng@intel.com>
Signed-off-by: lorena.r.de.leon.vazquez@intel.com
---
.../Feature/VTd/IntelVTdDxe/TranslationTable.c | 11 ++++-------
.../Feature/VTd/IntelVTdDxe/TranslationTableEx.c | 11 ++++-------
2 files changed, 8 insertions(+), 14 deletions(-)
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
index fcff0925b8..201d663d8f 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
@@ -128,14 +128,11 @@ CreateContextEntry (
DEBUG ((DEBUG_INFO,"Source: S%04x B%02x D%02x F%02x\n", mVtdUnitInformation[VtdIndex].Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function));
- switch (mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW) {
- case BIT1:
- ContextEntry->Bits.AddressWidth = 0x1;
- break;
- case BIT2:
- ContextEntry->Bits.AddressWidth = 0x2;
- break;
+ if ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) == 0) {
+ DEBUG((DEBUG_ERROR, "!!!! 4-level page-table is not supported on VTD %d !!!!\n", VtdIndex));
+ return EFI_UNSUPPORTED;
}
+ ContextEntry->Bits.AddressWidth = 0x2;
}
FlushPageTableMemory (VtdIndex, (UINTN)mVtdUnitInformation[VtdIndex].RootEntryTable, EFI_PAGES_TO_SIZE(EntryTablePages));
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c
index ee8c9e3ad2..f1be73885a 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c
@@ -78,14 +78,11 @@ CreateExtContextEntry (
DEBUG ((DEBUG_INFO,"DOMAIN: S%04x, B%02x D%02x F%02x\n", mVtdUnitInformation[VtdIndex].Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function));
- switch (mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW) {
- case BIT1:
- ExtContextEntry->Bits.AddressWidth = 0x1;
- break;
- case BIT2:
- ExtContextEntry->Bits.AddressWidth = 0x2;
- break;
+ if ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) == 0) {
+ DEBUG((DEBUG_ERROR, "!!!! 4-level page-table is not supported on VTD %d !!!!\n", VtdIndex));
+ return EFI_UNSUPPORTED;
}
+ ContextEntry->Bits.AddressWidth = 0x2;
}
FlushPageTableMemory (VtdIndex, (UINTN)mVtdUnitInformation[VtdIndex].ExtRootEntryTable, EFI_PAGES_TO_SIZE(EntryTablePages));
--
2.21.0.windows.1
prev parent reply other threads:[~2020-08-04 15:16 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-02 23:04 [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU generic bug fix lorena.r.de.leon.vazquez
2020-03-02 23:45 ` Yao, Jiewen
2020-07-02 13:55 ` [edk2-devel] " Lohr, Paul A
2020-07-03 1:54 ` Liming Gao
2020-07-06 17:24 ` De Leon Vazquez, Lorena R
2020-07-09 12:44 ` Liming Gao
2020-07-29 15:22 ` De Leon Vasquez, Lorena R
2020-07-31 7:29 ` Liming Gao
2020-08-04 15:15 ` De Leon Vasquez, Lorena R [this message]
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