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Tue, 4 Aug 2020 15:15:34 +0000 From: "De Leon Vasquez, Lorena R" To: "Gao, Liming" , "devel@edk2.groups.io" , "Lohr, Paul A" , "Yao, Jiewen" CC: "Kinney, Michael D" Subject: Re: [edk2-devel] [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU generic bug fix Thread-Topic: [edk2-devel] [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU generic bug fix Thread-Index: AdXw5cIqcI9g1CYLQByg/sbQxnIlIgABtlAQF+LrE7AAGPt4IAC3aFwgAI0ZORAD82aOoABUGsvQANlrO0A= Date: Tue, 4 Aug 2020 15:15:33 +0000 Message-ID: References: <74D8A39837DF1E4DA445A8C0B3885C503F96301F@shsmsx102.ccr.corp.intel.com> In-Reply-To: Accept-Language: en-US X-MS-Has-Attach: yes X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.5.1.3 dlp-product: dlpe-windows authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [189.163.162.78] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 41537632-ad4e-4b7f-3adc-08d838893bf1 x-ms-traffictypediagnostic: BYAPR11MB3655: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:9508; 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boundary="_004_BYAPR11MB2982C7ABE46892C335E89E64D04A0BYAPR11MB2982namp_" --_004_BYAPR11MB2982C7ABE46892C335E89E64D04A0BYAPR11MB2982namp_ Content-Type: multipart/alternative; boundary="_000_BYAPR11MB2982C7ABE46892C335E89E64D04A0BYAPR11MB2982namp_" --_000_BYAPR11MB2982C7ABE46892C335E89E64D04A0BYAPR11MB2982namp_ Content-Type: text/plain; charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable Hi Liming, I=1B$B!G=1B(Bve update the name Thanks, Lorena From: Gao, Liming Sent: Friday, July 31, 2020 2:30 AM To: De Leon Vasquez, Lorena R ; devel@= edk2.groups.io; Lohr, Paul A ; Yao, Jiewen Cc: Kinney, Michael D Subject: RE: [edk2-devel] [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU = generic bug fix Lorena: Thanks for your update. Can you correct name style as Star Zeng > for below message? Suggested-by: Star Zeng star.zeng@intel.com Signed-off-by: lorena.r.de.leon.vazquez@intel.com Thanks Liming From: De Leon Vasquez, Lorena R > Sent: 2020=1B$BG/=1B(B7=1B$B7n=1B(B29=1B$BF|=1B(B 23:23 To: Gao, Liming >; devel= @edk2.groups.io; Lohr, Paul A >; Yao, Jiewen > Cc: Kinney, Michael D > Subject: RE: [edk2-devel] [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU = generic bug fix I=1B$B!G=1B(Bve attached patch with modifications suggested From: Gao, Liming > Sent: Thursday, July 9, 2020 7:45 AM To: De Leon Vazquez, Lorena R >; devel@edk2.groups.io; Lohr, Paul A >; Yao, Jiewen > Cc: Kinney, Michael D > Subject: RE: [edk2-devel] [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU = generic bug fix Lorena: I have one minor comment on this patch. The error return status should b= e EFI_UNSUPPORTED. + return error; =3D=3D> return EFI_UNSUPPORTED; Thanks Liming From: De Leon Vazquez, Lorena R > Sent: Tuesday, July 7, 2020 1:24 AM To: Gao, Liming >; devel= @edk2.groups.io; Lohr, Paul A >; Yao, Jiewen > Cc: Kinney, Michael D > Subject: RE: [edk2-devel] [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU = generic bug fix Hi Liming, I=1B$B!G=1B(Bve attached the patch Thanks, Lorena From: Gao, Liming > Sent: Thursday, July 2, 2020 8:54 PM To: devel@edk2.groups.io; Lohr, Paul A >; Yao, Jiewen >; De Leon Vazquez, Lorena R > Cc: Kinney, Michael D > Subject: RE: [edk2-devel] [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU = generic bug fix Paul: This patch is missing to be merged. Lorena: I can=1B$B!G=1B(Bt extract the patch from the mail. Can you send the pat= ch to me? I can help merge it. Thanks Liming From: devel@edk2.groups.io > On Behalf Of Lohr, Paul A Sent: Thursday, July 2, 2020 9:56 PM To: devel@edk2.groups.io; Yao, Jiewen >; De Leon Vazquez, Lorena R = > Cc: Kinney, Michael D > Subject: Re: [edk2-devel] [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU = generic bug fix Hello, It seems this did not get checked in. Is there something wrong with the p= atch itself? Or was this simply submitted incorrectly? I don=1B$B!G=1B(Bt= see a Bugzilla associated with it is why I ask. Paul A. Lohr - Server Firmware Enabling 512.239.9073 (cell) 512.794.5044 (work) From: devel@edk2.groups.io > On Behalf Of Yao, Jiewen Sent: Monday, March 2, 2020 5:46 PM To: De Leon Vazquez, Lorena R >; devel@edk2.groups.io Cc: Kinney, Michael D > Subject: Re: [edk2-devel] [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU = generic bug fix Reviewed-by: jiewen.yao@intel.com From: De Leon Vazquez, Lorena R > Sent: Tuesday, March 3, 2020 7:04 AM To: devel@edk2.groups.io Cc: Yao, Jiewen >; Kinne= y, Michael D = > Subject: [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU generic bug fix Looks like Addresswidth is BIT wise values. Right now these values are not= used any Suggested-by: Star Zeng star.zeng@intel.com Signed-off-by: lorena.r.de.leon.vazquez@intel.com -- .../Feature/VTd/IntelVTdDxe/TranslationTable.c | 11 ++++------- .../Feature/VTd/IntelVTdDxe/TranslationTableEx.c | 11 ++++------- 2 files changed, 8 insertions(+), 14 deletions(-) diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/Transla= tionTable.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/Transla= tionTable.c index cc970c0..61fbb4a 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTab= le.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTab= le.c @@ -128,14 +128,11 @@ CreateContextEntry ( DEBUG ((DEBUG_INFO,"Source: S%04x B%02x D%02x F%02x\n", mVtdUnitInfor= mation[VtdIndex].Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId= .Bits.Function)); - switch (mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW) { - case BIT1: - ContextEntry->Bits.AddressWidth =3D 0x1; - break; - case BIT2: - ContextEntry->Bits.AddressWidth =3D 0x2; - break; + if ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) =3D=3D 0= ) { + DEBUG((DEBUG_ERROR, "!!!! 4-level page-table is not supported on VT= D %d !!!!\n", VtdIndex)); + return error; } + ContextEntry->Bits.AddressWidth =3D 0x2; } FlushPageTableMemory (VtdIndex, (UINTN)mVtdUnitInformation[VtdIndex].Ro= otEntryTable, EFI_PAGES_TO_SIZE(EntryTablePages)); diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/Transla= tionTableEx.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/Trans= lationTableEx.c index 0da1611..6bd31b7 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTab= leEx.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTab= leEx.c @@ -78,14 +78,11 @@ CreateExtContextEntry ( DEBUG ((DEBUG_INFO,"DOMAIN: S%04x, B%02x D%02x F%02x\n", mVtdUnitInfo= rmation[VtdIndex].Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceI= d.Bits.Function)); - switch (mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW) { - case BIT1: - ExtContextEntry->Bits.AddressWidth =3D 0x1; - break; - case BIT2: - ExtContextEntry->Bits.AddressWidth =3D 0x2; - break; + if ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) =3D=3D 0= ) { + DEBUG((DEBUG_ERROR, "!!!! 4-level page-table is not supported on VT= D %d !!!!\n", VtdIndex)); + return error; } + ContextEntry->Bits.AddressWidth =3D 0x2; } FlushPageTableMemory (VtdIndex, (UINTN)mVtdUnitInformation[VtdIndex].Ex= tRootEntryTable, EFI_PAGES_TO_SIZE(EntryTablePages)); -- 2.21.0.windows.1 --_000_BYAPR11MB2982C7ABE46892C335E89E64D04A0BYAPR11MB2982namp_ Content-Type: text/html; charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable

Hi Limin= g,

I=1B$B!G= = =1B(Bve update the name

Thanks, =

Lorena

&nb= sp;

From: Gao, Liming <liming.gao@intel.com&g= t;
Sent: Friday, July 31, 2020 2:30 AM
To: De Leon Vasquez, Lorena R <lorena.r.de.leon.vasquez@intel.co= m>; devel@edk2.groups.io; Lohr, Paul A <paul.a.lohr@intel.com>; Ya= o, Jiewen <jiewen.yao@intel.com>
Cc: Kinney, Michael D <michael.d.kinney@intel.com>
Subject: RE: [edk2-devel] [edk2-platforms] [PATCH] IntelSiliconPkg:= IOMMU generic bug fix

 

Lorena:

  Thanks for your update. Can= you correct name style as Star Zeng <star.zeng@intel.com> for below message?

 

Suggested-by: Star Zeng star.zeng@intel.com<= /span>

Signed-off-by: lorena.r.de.leon.vazquez@in= tel.com

 

Thanks

Liming

From:= De Leon Vasquez, Lor= ena R <lorena.r.de= .leon.vasquez@intel.com>
Sent: 2020=1B$BG/=1B(B7=1B$B7n=1B(B= 29=1B$BF|=1B(B 23:23
To: Gao, Liming <liming.= gao@intel.com>; devel@edk2.groups.io; Lohr, Pa= ul A <paul.a.lohr@intel.com= >; Yao, Jiewen <jiewen.yao@in= tel.com>
Cc: Kinney, Michael D <michael.d.kinney@intel.com>
Subject: RE: [edk2-devel] [edk2-platforms] [PATCH] IntelSiliconPkg:= IOMMU generic bug fix

&nb= sp;

I=1B$B!G= = =1B(Bve attached patch with modifications suggested  

&nb= sp;

From:= Gao, Liming <liming.gao@intel.com>
Sent: Thursday, July 9, 2020 7:45 AM
To: De Leon Vazquez, Lorena R <lorena.r.de.leon.vazquez@intel.com>; devel@edk2.groups.io; Lohr, Pa= ul A <paul.a.lohr@intel.com= >; Yao, Jiewen <jiewen.yao@in= tel.com>
Cc: Kinney, Michael D <michael.d.kinney@intel.com>
Subject: RE: [edk2-devel] [edk2-platforms] [PATCH] IntelSiliconPkg:= IOMMU generic bug fix

&nb= sp;

Lorena:<= o:p>

  I= have one minor comment on this patch. The error return status should be EF= I_UNSUPPORTED.

&nb= sp;

+ &= nbsp;    return error;

è

return E= FI_UNSUPPORTED;

&nb= sp;

Thanks

Liming

From:= De Leon Vazquez, Lor= ena R <lorena.r.de= .leon.vazquez@intel.com>
Sent: Tuesday, July 7, 2020 1:24 AM
To: Gao, Liming <liming.= gao@intel.com>; devel@edk2.groups.io; Lohr, Pa= ul A <paul.a.lohr@intel.com= >; Yao, Jiewen <jiewen.yao@in= tel.com>
Cc: Kinney, Michael D <michael.d.kinney@intel.com>
Subject: RE: [edk2-devel] [edk2-platforms] [PATCH] IntelSiliconPkg:= IOMMU generic bug fix

&nb= sp;

Hi Limin= g,

I=1B$B!G= = =1B(Bve attached the patch

&nb= sp;

Thanks, =

Lorena

&nb= sp;

From:= Gao, Liming <liming.gao@intel.com>
Sent: Thursday, July 2, 2020 8:54 PM
To: devel@edk2.groups.io; Lohr, Paul A <paul.a.lohr@in= tel.com>; Yao, Jiewen <ji= ewen.yao@intel.com>; De Leon Vazquez, Lorena R <lorena.r.de.l= eon.vazquez@intel.com>
Cc: Kinney, Michael D <michael.d.kinney@intel.com>
Subject: RE: [edk2-devel] [edk2-platforms] [PATCH] IntelSiliconPkg:= IOMMU generic bug fix

&nb= sp;

Paul:

 &n= bsp;This patch is missing to be merged.

&nb= sp;

Lorena: =

 &n= bsp;I can=1B$B!G=1B(Bt extract the patch from the mail. Can you send the pa= tch to me? I can help merge it.

&nb= sp;

Thanks

Liming

From:= devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Lohr, Paul A
Sent: Thursday, July 2, 2020 9:56 PM
To: devel@edk2.groups.io; Yao, Jiewen <jiewen.yao@intel= .com>; De Leon Vazquez, Lorena R <lorena.r.de.leon.vazquez@intel.com>
Cc: Kinney, Michael D <michael.d.kinney@intel.com>
Subject: Re: [edk2-devel] [edk2-platforms] [PATCH] IntelSiliconPkg:= IOMMU generic bug fix

&nb= sp;

Hello,

&nb= sp;

It seems= this did not get checked in.  Is there something wrong with the patch= itself?  Or was this simply submitted incorrectly?  I don=1B$B!G= = =1B(Bt see a Bugzilla associated with it is why I ask.

&nb= sp;

Paul A. Lohr – Server Firmware Enabling

512.239.9073 (cell)

512.794.5044 (work)

&nb= sp;

From:= devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Yao, Jiewen
Sent: Monday, March 2, 2020 5:46 PM
To: De Leon Vazquez, Lorena R <lorena.r.de.leon.vazquez@intel.com>; devel@edk2.groups.io
Cc: Kinney, Michael D <michael.d.kinney@intel.com>
Subject: Re: [edk2-devel] [edk2-platforms] [PATCH] IntelSiliconPkg:= IOMMU generic bug fix

&nb= sp;

Reviewed= -by: jiewen.yao@intel.com

&nb= sp;

From:= De Leon Vazquez, Lor= ena R <lorena.r.de= .leon.vazquez@intel.com>
Sent: Tuesday, March 3, 2020 7:04 AM
To: devel@edk2.groups.io
Cc: Yao, Jiewen <jiewen.= yao@intel.com>; Kinney, Michael D <michael.d.kinney@intel.com>
Subject: [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU generic bu= g fix

&nb= sp;

Looks li= ke Addresswidth is BIT wise values. Right now these values are not used any=

&nb= sp;

Suggested-by: Star Zeng star.zeng@intel.com<= /span>

Signed-off-by: lorena.r.de.leon.vazquez@in= tel.com

&nb= sp;

--<= /o:p>

.../Feat= ure/VTd/IntelVTdDxe/TranslationTable.c      &= nbsp; | 11 ++++-------

.../Feat= ure/VTd/IntelVTdDxe/TranslationTableEx.c      | 11= ++++-------

2 files = changed, 8 insertions(+), 14 deletions(-)

&nb= sp;

diff --g= it a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable= .c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable= .c

index cc= 970c0..61fbb4a 100644

--- a/Si= licon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c=

+++ b/Si= licon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c=

@@ -128,= 14 +128,11 @@ CreateContextEntry (

&nb= sp;

 &n= bsp;   DEBUG ((DEBUG_INFO,"Source: S%04x B%02x D%02x F%= 02x\n", mVtdUnitInformation[VtdIndex].Segment, SourceId.Bits.Bus, Sour= ceId.Bits.Device, SourceId.Bits.Function));

&nb= sp;

- &= nbsp;  switch (mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW) {=

- &= nbsp;  case BIT1:

- &= nbsp;    ContextEntry->Bits.AddressWidth =3D 0x1;

- &= nbsp;    break;

- &= nbsp;  case BIT2:

- &= nbsp;    ContextEntry->Bits.AddressWidth =3D 0x2;

- &= nbsp;    break;

+ &= nbsp;  if ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2= ) =3D=3D 0) {

+ &= nbsp;    DEBUG((DEBUG_ERROR, "!!!! 4-level page-table i= s not supported on VTD %d !!!!\n", VtdIndex));

+ &= nbsp;    return error;

 &n= bsp;   }

+ &= nbsp;  ContextEntry->Bits.AddressWidth =3D 0x2;

 &n= bsp; }

&nb= sp;

 &n= bsp; FlushPageTableMemory (VtdIndex, (UINTN)mVtdUnitInformation[VtdInd= ex].RootEntryTable, EFI_PAGES_TO_SIZE(EntryTablePages));<= /p>

diff --g= it a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable= Ex.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTab= leEx.c

index 0d= a1611..6bd31b7 100644

--- a/Si= licon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c

+++ b/Si= licon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c

@@ -78,1= 4 +78,11 @@ CreateExtContextEntry (

&nb= sp;

 &n= bsp;   DEBUG ((DEBUG_INFO,"DOMAIN: S%04x, B%02x D%02x F= %02x\n", mVtdUnitInformation[VtdIndex].Segment, SourceId.Bits.Bus, Sou= rceId.Bits.Device, SourceId.Bits.Function));

&nb= sp;

- &= nbsp;  switch (mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW) {=

- &= nbsp;  case BIT1:

- &= nbsp;    ExtContextEntry->Bits.AddressWidth =3D 0x1;=

- &= nbsp;    break;

- &= nbsp;  case BIT2:

- &= nbsp;    ExtContextEntry->Bits.AddressWidth =3D 0x2;=

- &= nbsp;    break;

+ &= nbsp;  if ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2= ) =3D=3D 0) {

+ &= nbsp;    DEBUG((DEBUG_ERROR, "!!!! 4-level page-table i= s not supported on VTD %d !!!!\n", VtdIndex));

+ &= nbsp;    return error;

 &n= bsp;   }

+ &= nbsp;  ContextEntry->Bits.AddressWidth =3D 0x2;

 &n= bsp; }

&nb= sp;

 &n= bsp; FlushPageTableMemory (VtdIndex, (UINTN)mVtdUnitInformation[VtdInd= ex].ExtRootEntryTable, EFI_PAGES_TO_SIZE(EntryTablePages));

-- =

2.21.0.w= indows.1

&nb= sp;

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