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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Guo Dong -----Original Message----- From: Ni, Ray =20 Sent: Friday, August 6, 2021 1:16 AM To: devel@edk2.groups.io Cc: Dong, Guo ; Ma, Maurice ; You= , Benjamin Subject: [PATCH] UefiPayloadPkg/PayloadEntry: Inherit 4/5-level paging from= bootloader The patch removes the dep on PcdUse5LevelPageTable. Now the payload inherits the 5-level paging setting from bootloader in IA-3= 2e mode and uses 4-level paging in legacy protected mode. This fix the potential issue when bootloader enables 5-level paging but 64b= it payload sets 4-level page table to CR3 resulting CPU exception because P= cdUse5LevelPageTable is FALSE. Signed-off-by: Ray Ni Cc: Guo Dong Cc: Ray Ni Cc: Maurice Ma Cc: Benjamin You --- .../UefiPayloadEntry/UefiPayloadEntry.inf | 1 - .../UniversalPayloadEntry.inf | 1 - .../UefiPayloadEntry/X64/VirtualMemory.c | 38 ++++++++----------- 3 files changed, 16 insertions(+), 24 deletions(-) diff --git a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf b/UefiPay= loadPkg/UefiPayloadEntry/UefiPayloadEntry.inf index 8d42925fcd..9b6fab66a1 100644 --- a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf +++ b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf @@ -80,7 +80,6 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask ##= CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask = ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard = ## CONSUMES- gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPa= geTable ## SOMETIMES_CONSUMES gEfiMdeModulePkgTokenSpace= Guid.PcdGhcbBase ## CONSUMES gEfiMdeModulePkgT= okenSpaceGuid.PcdGhcbSize ## CONSUMES diff --git= a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf b/UefiPayloadP= kg/UefiPayloadEntry/UniversalPayloadEntry.inf index 416a620598..aae62126e9 100644 --- a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf +++ b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf @@ -85,7 +85,6 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask ##= CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask = ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard = ## CONSUMES- gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPa= geTable ## SOMETIMES_CONSUMES gEfiMdeModulePkgTokenSpace= Guid.PcdGhcbBase ## CONSUMES gEfiMdeModulePkgT= okenSpaceGuid.PcdGhcbSize ## CONSUMES diff --git= a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c b/UefiPayloadPkg/Uef= iPayloadEntry/X64/VirtualMemory.c index a1c4ad6ff4..9daa46c12c 100644 --- a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c +++ b/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c @@ -15,7 +15,7 @@ 2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:In= struction Set Reference, Intel 3) IA-32 Intel(R) Architecture Software = Developer's Manual Volume 3:System Programmer's Guide, Intel -Copyright (c)= 2006 - 2020, Intel Corporation. All rights reserved.
+Copyright (c) 200= 6 - 2021, Intel Corporation. All rights reserved.
Copyright (c) 2017, A= MD Incorporated. All rights reserved.
SPDX-License-Identifier: BSD-2-C= lause-Patent@@ -668,7 +668,6 @@ CreateIdentityMappingPageTables ( ) { UINT32 RegEax;- CPUID_STRU= CTURED_EXTENDED_FEATURE_FLAGS_ECX EcxFlags; UINT32 = RegEdx; UINT8 = PhysicalAddressBits; EFI_PHYSICAL_ADDRESS PageAd= dress;@@ -687,7 +686,7 @@ CreateIdentityMappingPageTables ( UINTN TotalPagesNum; UINTN = BigPageAddress; VOID = *Hob;- BOOLEAN = Page5LevelSupport;+ BOOLEAN Ena= ble5LevelPaging; BOOLEAN Page1GSupp= ort; PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry;= UINT64 AddressEncMask;@@ -730,18 = +729,16 @@ CreateIdentityMappingPageTables ( } } - Page5LevelSupport =3D FALSE;- if (PcdGetBool (PcdUse5LevelPa= geTable)) {- AsmCpuidEx (- CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,= CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, NULL,- &EcxFla= gs.Uint32, NULL, NULL- );- if (EcxFlags.Bits.FiveLevelPage !=3D 0) = {- Page5LevelSupport =3D TRUE;- }- }+ //+ // Check CR4.LA57[bit1= 2] to determin whether 5-Level Paging is enabled.+ // Because this code ru= ns at both IA-32e (64bit) mode and legacy protected (32bit) mode,+ // belo= w logic inherits the 5-level paging setting from bootloader in IA-32e mode+= // and uses 4-level paging in legacy protected mode.+ //+ Cr4.UintN =3D= AsmReadCr4 ();+ Enable5LevelPaging =3D (BOOLEAN) (Cr4.Bits.LA57 =3D=3D 1)= ; - DEBUG ((DEBUG_INFO, "AddressBits=3D%u 5LevelPaging=3D%u 1GPage=3D%u\n"= , PhysicalAddressBits, Page5LevelSupport, Page1GSupport));+ DEBUG ((DEBUG_= INFO, "PayloadEntry: AddressBits=3D%u 5LevelPaging=3D%u 1GPage=3D%u\n", Phy= sicalAddressBits, Enable5LevelPaging, Page1GSupport)); // // IA-32e pa= ging translates 48-bit linear addresses to 52-bit physical addresses@@ -749= ,7 +746,7 @@ CreateIdentityMappingPageTables ( // due to either unsupported by HW, or disabled by PCD. // ASSERT (= PhysicalAddressBits <=3D 52);- if (!Page5LevelSupport && PhysicalAddressBi= ts > 48) {+ if (!Enable5LevelPaging && PhysicalAddressBits > 48) { Phy= sicalAddressBits =3D 48; } @@ -784,7 +781,7 @@ CreateIdentityMappingPageT= ables ( // // Substract the one page occupied by PML5 entries if 5-Level Pagin= g is disabled. //- if (!Page5LevelSupport) {+ if (!Enable5LevelPaging) = { TotalPagesNum--; } @@ -799,7 +796,7 @@ CreateIdentityMappingPageTab= les ( // By architecture only one PageMapLevel4 exists - so lets allocate stor= age for it. // PageMap =3D (VOID *) BigPageAddress;- if (Page5= LevelSupport) {+ if (Enable5LevelPaging) { // // By architecture o= nly one PageMapLevel5 exists - so lets allocate storage for it. //@@ -8= 19,7 +816,7 @@ CreateIdentityMappingPageTables ( PageMapLevel4Entry =3D (VOID *) BigPageAddress; BigPageAddress = +=3D SIZE_4KB; - if (Page5LevelSupport) {+ if (Enable5LevelPaging) { = // // Make a PML5 Entry //@@ -911,10 +908,7 @@ CreateIden= tityMappingPageTables ( ZeroMem (PageMapLevel4Entry, (512 - IndexOfPml4Entries) * sizeof (PAGE= _MAP_AND_DIRECTORY_POINTER)); } - if (Page5LevelSupport) {- Cr4.UintN= =3D AsmReadCr4 ();- Cr4.Bits.LA57 =3D 1;- AsmWriteCr4 (Cr4.UintN);+ = if (Enable5LevelPaging) { // // For the PML5 entries we are not us= ing fill in a null entry. //--=20 2.32.0.windows.1