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X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR11MB3543 Return-Path: guo.dong@intel.com X-OriginatorOrg: intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Bauer, Please check latest code, Ray just checked in a patch to remove hardcoded P= CIe base address as below. commit 3900a63e3a1b9ba9a4105bedead7b986188cec2c Author: Ray Ni Date: Wed Jun 17 16:34:29 2020 +0800 UefiPayloadPkg/Pci: Use the PCIE Base Addr stored in AcpiBoardInfo HOB Thanks, Guo > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of > Marcello Sylvester Bauer > Sent: Wednesday, June 24, 2020 3:26 AM > To: devel@edk2.groups.io > Cc: Patrick Rudolph ; Christian Walter > ; Ma, Maurice ; > Desimone, Nathaniel L ; Zeng, Star > > Subject: [edk2-devel] [PATCH v1 2/2] UefiPayloadPkg: Runtime MMCONF >=20 > From: Patrick Rudolph >=20 > * Don't hardcode PCIE_BASE at build time > * Support arbitrary platforms with different or even no MMCONF space > * Fix buffer overflow accessing MMCONF where less than 256 buses are > exposed > * Use PciCfg8 for PCI access in PEI, which is only used for debugging >=20 > Signed-off-by: Patrick Rudolph > Signed-off-by: Marcello Sylvester Bauer > Cc: Patrick Rudolph > Cc: Christian Walter > Cc: Maurice Ma > Cc: Nate DeSimone > Cc: Star Zeng > --- > UefiPayloadPkg/UefiPayloadPkgIa32.dsc | = 16 +- > UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc | = 16 +- > UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLib.inf | = 46 + > UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf | = 42 > + > UefiPayloadPkg/Library/BasePciExpressLib/PciExpressLib.c | 1= 455 > ++++++++++++++++++++ > UefiPayloadPkg/Library/BasePciLibPciExpress/PciLib.c | 1= 302 > ++++++++++++++++++ > UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLib.uni | = 17 + > UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.uni | = 17 > + > 8 files changed, 2885 insertions(+), 26 deletions(-) >=20 > diff --git a/UefiPayloadPkg/UefiPayloadPkgIa32.dsc > b/UefiPayloadPkg/UefiPayloadPkgIa32.dsc > index c6c47833871b..48b03af6f223 100644 > --- a/UefiPayloadPkg/UefiPayloadPkgIa32.dsc > +++ b/UefiPayloadPkg/UefiPayloadPkgIa32.dsc > @@ -37,11 +37,6 @@ [Defines] > # >=20 > DEFINE MAX_LOGICAL_PROCESSORS =3D 64 >=20 >=20 >=20 > - # >=20 > - # PCI options >=20 > - # >=20 > - DEFINE PCIE_BASE =3D 0xE0000000 >=20 > - >=20 > # >=20 > # Serial port set up >=20 > # >=20 > @@ -121,13 +116,9 @@ [LibraryClasses] > PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf >=20 > CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf >=20 > IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf >=20 > -!if $(PCIE_BASE) =3D=3D 0 >=20 > - PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf >=20 > PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf >=20 > -!else >=20 > - PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf >=20 > - PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf >=20 > -!endif >=20 > + > PciLib|UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.i= nf >=20 > + > PciExpressLib|UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLib.= i > nf >=20 >=20 > PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibP > ci.inf >=20 > PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf >=20 >=20 > PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/Base > PeCoffGetEntryPointLib.inf >=20 > @@ -216,6 +207,7 @@ [LibraryClasses.IA32.SEC] > [LibraryClasses.IA32.PEI_CORE, LibraryClasses.IA32.PEIM] >=20 > PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf >=20 > HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf >=20 > + PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf >=20 >=20 > MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemory > AllocationLib.inf >=20 >=20 > ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiR > eportStatusCodeLib.inf >=20 >=20 > ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiEx > tractGuidedSectionLib.inf >=20 > @@ -286,8 +278,6 @@ [PcdsFixedAtBuild] > gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE >=20 > gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, > 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0= x66, > 0x23, 0x31 } >=20 >=20 >=20 > - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|$(PCIE_BASE) >=20 > - >=20 > !if $(SOURCE_DEBUG_ENABLE) >=20 >=20 > gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x > 2 >=20 > !endif >=20 > diff --git a/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc > b/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc > index 5559b1258521..af951ee5aec0 100644 > --- a/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc > +++ b/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc > @@ -38,11 +38,6 @@ [Defines] > # >=20 > DEFINE MAX_LOGICAL_PROCESSORS =3D 64 >=20 >=20 >=20 > - # >=20 > - # PCI options >=20 > - # >=20 > - DEFINE PCIE_BASE =3D 0xE0000000 >=20 > - >=20 > # >=20 > # Serial port set up >=20 > # >=20 > @@ -122,13 +117,9 @@ [LibraryClasses] > PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf >=20 > CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf >=20 > IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf >=20 > -!if $(PCIE_BASE) =3D=3D 0 >=20 > - PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf >=20 > PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf >=20 > -!else >=20 > - PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf >=20 > - PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf >=20 > -!endif >=20 > + > PciLib|UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.i= nf >=20 > + > PciExpressLib|UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLib.= i > nf >=20 >=20 > PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibP > ci.inf >=20 > PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf >=20 >=20 > PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/Base > PeCoffGetEntryPointLib.inf >=20 > @@ -217,6 +208,7 @@ [LibraryClasses.IA32.SEC] > [LibraryClasses.IA32.PEI_CORE, LibraryClasses.IA32.PEIM] >=20 > PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf >=20 > HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf >=20 > + PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf >=20 >=20 > MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemory > AllocationLib.inf >=20 >=20 > ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiR > eportStatusCodeLib.inf >=20 >=20 > ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiEx > tractGuidedSectionLib.inf >=20 > @@ -288,8 +280,6 @@ [PcdsFixedAtBuild] > gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|TRUE >=20 > gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, > 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0= x66, > 0x23, 0x31 } >=20 >=20 >=20 > - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|$(PCIE_BASE) >=20 > - >=20 > !if $(SOURCE_DEBUG_ENABLE) >=20 >=20 > gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x > 2 >=20 > !endif >=20 > diff --git a/UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLib.i= nf > b/UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLib.inf > new file mode 100644 > index 000000000000..9f052c0a2e65 > --- /dev/null > +++ b/UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLib.inf > @@ -0,0 +1,46 @@ > +## @file >=20 > +# Instance of PCI Express Library using the 256 MB PCI Express MMIO > window. >=20 > +# >=20 > +# PCI Express Library that uses the 256 MB PCI Express MMIO window to > perform >=20 > +# PCI Configuration cycles. Layers on top of an I/O Library instance. >=20 > +# >=20 > +# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved. >=20 > +# >=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +# >=20 > +## >=20 > + >=20 > +[Defines] >=20 > + INF_VERSION =3D 0x00010005 >=20 > + BASE_NAME =3D BasePciExpressLib >=20 > + MODULE_UNI_FILE =3D BasePciExpressLib.uni >=20 > + FILE_GUID =3D 287e50f4-a188-4699-b907-3e4080ca568= 8 >=20 > + MODULE_TYPE =3D BASE >=20 > + VERSION_STRING =3D 1.0 >=20 > + LIBRARY_CLASS =3D PciExpressLib >=20 > + CONSTRUCTOR =3D PciExpressLibInitialize >=20 > + >=20 > +# >=20 > +# VALID_ARCHITECTURES =3D IA32 X64 EBC >=20 > +# >=20 > + >=20 > +[Sources] >=20 > + PciExpressLib.c >=20 > + >=20 > +[Packages] >=20 > + MdePkg/MdePkg.dec >=20 > + UefiPayloadPkg/UefiPayloadPkg.dec >=20 > + >=20 > +[LibraryClasses] >=20 > + BaseLib >=20 > + DebugLib >=20 > + HobLib >=20 > + IoLib >=20 > + >=20 > +[Guids] >=20 > + gUefiAcpiBoardInfoGuid >=20 > + >=20 > +[Pcd] >=20 > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES >=20 > + >=20 > diff --git > a/UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf > b/UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf > new file mode 100644 > index 000000000000..0858e49a47ae > --- /dev/null > +++ b/UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.in= f > @@ -0,0 +1,42 @@ > +## @file >=20 > +# Instance of PCI Library based on PCI Express Library. >=20 > +# >=20 > +# PCI Library that uses the 256 MB PCI Express MMIO window to perform > PCI >=20 > +# Configuration cycles. Layers on one PCI Express Library instance. >=20 > +# >=20 > +# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved. >=20 > +# >=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +# >=20 > +## >=20 > + >=20 > +[Defines] >=20 > + INF_VERSION =3D 0x00010005 >=20 > + BASE_NAME =3D BasePciLibPciExpress >=20 > + MODULE_UNI_FILE =3D BasePciLibPciExpress.uni >=20 > + FILE_GUID =3D 8987081e-daeb-44a9-8bef-a195b22d941= 7 >=20 > + MODULE_TYPE =3D BASE >=20 > + VERSION_STRING =3D 1.0 >=20 > + LIBRARY_CLASS =3D PciLib >=20 > + CONSTRUCTOR =3D PciLibInitialize >=20 > + >=20 > +# >=20 > +# VALID_ARCHITECTURES =3D IA32 X64 >=20 > +# >=20 > + >=20 > +[Sources] >=20 > + PciLib.c >=20 > + >=20 > +[Packages] >=20 > + MdePkg/MdePkg.dec >=20 > + UefiPayloadPkg/UefiPayloadPkg.dec >=20 > + >=20 > +[Guids] >=20 > + gUefiAcpiBoardInfoGuid >=20 > + >=20 > +[LibraryClasses] >=20 > + PciExpressLib >=20 > + PciCf8Lib >=20 > + BaseLib >=20 > + HobLib >=20 > diff --git a/UefiPayloadPkg/Library/BasePciExpressLib/PciExpressLib.c > b/UefiPayloadPkg/Library/BasePciExpressLib/PciExpressLib.c > new file mode 100644 > index 000000000000..f3b4582d3c47 > --- /dev/null > +++ b/UefiPayloadPkg/Library/BasePciExpressLib/PciExpressLib.c > @@ -0,0 +1,1455 @@ > +/** @file >=20 > + Functions in this library instance make use of MMIO functions in IoLib= to >=20 > + access memory mapped PCI configuration space. >=20 > + >=20 > + All assertions for I/O operations are handled in MMIO functions in the= IoLib >=20 > + Library. >=20 > + >=20 > + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > + >=20 > +#include >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#include >=20 > +#include >=20 > + >=20 > +STATIC ACPI_BOARD_INFO mBoardInfo; >=20 > +/** >=20 > + Assert the validity of a PCI address. >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + >=20 > + Return 0xff on transaction outside of the MMCONF space. >=20 > + >=20 > + @param A The address to validate. >=20 > + >=20 > +**/ >=20 > +#define ASSERT_INVALID_PCI_ADDRESS(A) \ >=20 > + ASSERT (((A) & ~0xfffffff) =3D=3D 0); \ >=20 > + if ((A) >=3D mBoardInfo.PcieBaseSize) { \ >=20 > + return ~0; \ >=20 > + } >=20 > + >=20 > +/** >=20 > + Registers a PCI device so PCI configuration registers may be accessed = after >=20 > + SetVirtualAddressMap(). >=20 > + >=20 > + Registers the PCI device specified by Address so all the PCI configura= tion >=20 > + registers associated with that PCI device may be accessed after > SetVirtualAddressMap() >=20 > + is called. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + >=20 > + @param Address The address that encodes the PCI Bus, Device, Function > and >=20 > + Register. >=20 > + >=20 > + @retval RETURN_SUCCESS The PCI device was registered for run= time > access. >=20 > + @retval RETURN_UNSUPPORTED An attempt was made to call this > function >=20 > + after ExitBootServices(). >=20 > + @retval RETURN_UNSUPPORTED The resources required to access the > PCI device >=20 > + at runtime could not be mapped. >=20 > + @retval RETURN_OUT_OF_RESOURCES There are not enough resources > available to >=20 > + complete the registration. >=20 > + >=20 > +**/ >=20 > +RETURN_STATUS >=20 > +EFIAPI >=20 > +PciExpressRegisterForRuntimeAccess ( >=20 > + IN UINTN Address >=20 > + ) >=20 > +{ >=20 > + ASSERT_INVALID_PCI_ADDRESS (Address); >=20 > + return RETURN_UNSUPPORTED; >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs platform specific initialization required for the CPU to acce= ss >=20 > + the MMCONF space. This function does not initialize the MMCONF itself= . >=20 > + >=20 > + @retval RETURN_SUCCESS The platform specific initialization succ= eeded. >=20 > + @retval RETURN_DEVICE_ERROR The platform specific initialization coul= d > not be completed. >=20 > + >=20 > +**/ >=20 > +RETURN_STATUS >=20 > +EFIAPI >=20 > +PciExpressLibInitialize ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + EFI_HOB_GUID_TYPE *GuidHob; >=20 > + >=20 > + // >=20 > + // Find the acpi board information guid hob >=20 > + // >=20 > + GuidHob =3D GetFirstGuidHob (&gUefiAcpiBoardInfoGuid); >=20 > + ASSERT (GuidHob !=3D NULL); >=20 > + if (GuidHob =3D=3D NULL) { >=20 > + return EFI_UNSUPPORTED; >=20 > + } >=20 > + >=20 > + CopyMem (&mBoardInfo, GET_GUID_HOB_DATA (GuidHob), > sizeof(mBoardInfo)); >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Gets the base address of PCI Express. >=20 > + >=20 > + This internal functions retrieves PCI Express Base Address via a PCD e= ntry >=20 > + PcdPciExpressBaseAddress. >=20 > + >=20 > + @return The base address of PCI Express. >=20 > + >=20 > +**/ >=20 > +VOID* >=20 > +GetPciExpressBaseAddress ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return (VOID*)(UINTN) mBoardInfo.PcieBaseAddress; >=20 > +} >=20 > + >=20 > +/** >=20 > + Reads an 8-bit PCI configuration register. >=20 > + >=20 > + Reads and returns the 8-bit PCI configuration register specified by Ad= dress. >=20 > + This function must guarantee that all PCI read and write operations ar= e >=20 > + serialized. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + >=20 > + @param Address The address that encodes the PCI Bus, Device, Function > and >=20 > + Register. >=20 > + >=20 > + @return The read value from the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +EFIAPI >=20 > +PciExpressRead8 ( >=20 > + IN UINTN Address >=20 > + ) >=20 > +{ >=20 > + ASSERT_INVALID_PCI_ADDRESS (Address); >=20 > + return MmioRead8 ((UINTN) GetPciExpressBaseAddress () + Address); >=20 > +} >=20 > + >=20 > +/** >=20 > + Writes an 8-bit PCI configuration register. >=20 > + >=20 > + Writes the 8-bit PCI configuration register specified by Address with = the >=20 > + value specified by Value. Value is returned. This function must guaran= tee >=20 > + that all PCI read and write operations are serialized. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + >=20 > + @param Address The address that encodes the PCI Bus, Device, Function > and >=20 > + Register. >=20 > + @param Value The value to write. >=20 > + >=20 > + @return The value written to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +EFIAPI >=20 > +PciExpressWrite8 ( >=20 > + IN UINTN Address, >=20 > + IN UINT8 Value >=20 > + ) >=20 > +{ >=20 > + ASSERT_INVALID_PCI_ADDRESS (Address); >=20 > + return MmioWrite8 ((UINTN) GetPciExpressBaseAddress () + Address, > Value); >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs a bitwise OR of an 8-bit PCI configuration register with >=20 > + an 8-bit value. >=20 > + >=20 > + Reads the 8-bit PCI configuration register specified by Address, perfo= rms a >=20 > + bitwise OR between the read result and the value specified by >=20 > + OrData, and writes the result to the 8-bit PCI configuration register >=20 > + specified by Address. The value written to the PCI configuration regis= ter is >=20 > + returned. This function must guarantee that all PCI read and write > operations >=20 > + are serialized. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + >=20 > + @param Address The address that encodes the PCI Bus, Device, Function > and >=20 > + Register. >=20 > + @param OrData The value to OR with the PCI configuration register. >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +EFIAPI >=20 > +PciExpressOr8 ( >=20 > + IN UINTN Address, >=20 > + IN UINT8 OrData >=20 > + ) >=20 > +{ >=20 > + ASSERT_INVALID_PCI_ADDRESS (Address); >=20 > + return MmioOr8 ((UINTN) GetPciExpressBaseAddress () + Address, > OrData); >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs a bitwise AND of an 8-bit PCI configuration register with an = 8-bit >=20 > + value. >=20 > + >=20 > + Reads the 8-bit PCI configuration register specified by Address, perfo= rms a >=20 > + bitwise AND between the read result and the value specified by AndData= , > and >=20 > + writes the result to the 8-bit PCI configuration register specified by >=20 > + Address. The value written to the PCI configuration register is return= ed. >=20 > + This function must guarantee that all PCI read and write operations ar= e >=20 > + serialized. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + >=20 > + @param Address The address that encodes the PCI Bus, Device, Function > and >=20 > + Register. >=20 > + @param AndData The value to AND with the PCI configuration register. >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +EFIAPI >=20 > +PciExpressAnd8 ( >=20 > + IN UINTN Address, >=20 > + IN UINT8 AndData >=20 > + ) >=20 > +{ >=20 > + ASSERT_INVALID_PCI_ADDRESS (Address); >=20 > + return MmioAnd8 ((UINTN) GetPciExpressBaseAddress () + Address, > AndData); >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs a bitwise AND of an 8-bit PCI configuration register with an = 8-bit >=20 > + value, followed a bitwise OR with another 8-bit value. >=20 > + >=20 > + Reads the 8-bit PCI configuration register specified by Address, perfo= rms a >=20 > + bitwise AND between the read result and the value specified by AndData= , >=20 > + performs a bitwise OR between the result of the AND operation and >=20 > + the value specified by OrData, and writes the result to the 8-bit PCI >=20 > + configuration register specified by Address. The value written to the = PCI >=20 > + configuration register is returned. This function must guarantee that = all PCI >=20 > + read and write operations are serialized. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + >=20 > + @param Address The address that encodes the PCI Bus, Device, Function > and >=20 > + Register. >=20 > + @param AndData The value to AND with the PCI configuration register. >=20 > + @param OrData The value to OR with the result of the AND operation. >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +EFIAPI >=20 > +PciExpressAndThenOr8 ( >=20 > + IN UINTN Address, >=20 > + IN UINT8 AndData, >=20 > + IN UINT8 OrData >=20 > + ) >=20 > +{ >=20 > + ASSERT_INVALID_PCI_ADDRESS (Address); >=20 > + return MmioAndThenOr8 ( >=20 > + (UINTN) GetPciExpressBaseAddress () + Address, >=20 > + AndData, >=20 > + OrData >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Reads a bit field of a PCI configuration register. >=20 > + >=20 > + Reads the bit field in an 8-bit PCI configuration register. The bit fi= eld is >=20 > + specified by the StartBit and the EndBit. The value of the bit field i= s >=20 > + returned. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If StartBit is greater than 7, then ASSERT(). >=20 > + If EndBit is greater than 7, then ASSERT(). >=20 > + If EndBit is less than StartBit, then ASSERT(). >=20 > + >=20 > + @param Address The PCI configuration register to read. >=20 > + @param StartBit The ordinal of the least significant bit in the bit = field. >=20 > + Range 0..7. >=20 > + @param EndBit The ordinal of the most significant bit in the bit f= ield. >=20 > + Range 0..7. >=20 > + >=20 > + @return The value of the bit field read from the PCI configuration reg= ister. >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +EFIAPI >=20 > +PciExpressBitFieldRead8 ( >=20 > + IN UINTN Address, >=20 > + IN UINTN StartBit, >=20 > + IN UINTN EndBit >=20 > + ) >=20 > +{ >=20 > + ASSERT_INVALID_PCI_ADDRESS (Address); >=20 > + return MmioBitFieldRead8 ( >=20 > + (UINTN) GetPciExpressBaseAddress () + Address, >=20 > + StartBit, >=20 > + EndBit >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Writes a bit field to a PCI configuration register. >=20 > + >=20 > + Writes Value to the bit field of the PCI configuration register. The b= it >=20 > + field is specified by the StartBit and the EndBit. All other bits in t= he >=20 > + destination PCI configuration register are preserved. The new value of= the >=20 > + 8-bit register is returned. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If StartBit is greater than 7, then ASSERT(). >=20 > + If EndBit is greater than 7, then ASSERT(). >=20 > + If EndBit is less than StartBit, then ASSERT(). >=20 > + If Value is larger than the bitmask value range specified by StartBit = and > EndBit, then ASSERT(). >=20 > + >=20 > + @param Address The PCI configuration register to write. >=20 > + @param StartBit The ordinal of the least significant bit in the bit = field. >=20 > + Range 0..7. >=20 > + @param EndBit The ordinal of the most significant bit in the bit f= ield. >=20 > + Range 0..7. >=20 > + @param Value The new value of the bit field. >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +EFIAPI >=20 > +PciExpressBitFieldWrite8 ( >=20 > + IN UINTN Address, >=20 > + IN UINTN StartBit, >=20 > + IN UINTN EndBit, >=20 > + IN UINT8 Value >=20 > + ) >=20 > +{ >=20 > + ASSERT_INVALID_PCI_ADDRESS (Address); >=20 > + return MmioBitFieldWrite8 ( >=20 > + (UINTN) GetPciExpressBaseAddress () + Address, >=20 > + StartBit, >=20 > + EndBit, >=20 > + Value >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR= , and >=20 > + writes the result back to the bit field in the 8-bit port. >=20 > + >=20 > + Reads the 8-bit PCI configuration register specified by Address, perfo= rms a >=20 > + bitwise OR between the read result and the value specified by >=20 > + OrData, and writes the result to the 8-bit PCI configuration register >=20 > + specified by Address. The value written to the PCI configuration regis= ter is >=20 > + returned. This function must guarantee that all PCI read and write > operations >=20 > + are serialized. Extra left bits in OrData are stripped. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If StartBit is greater than 7, then ASSERT(). >=20 > + If EndBit is greater than 7, then ASSERT(). >=20 > + If EndBit is less than StartBit, then ASSERT(). >=20 > + If OrData is larger than the bitmask value range specified by StartBit= and > EndBit, then ASSERT(). >=20 > + >=20 > + @param Address The PCI configuration register to write. >=20 > + @param StartBit The ordinal of the least significant bit in the bit = field. >=20 > + Range 0..7. >=20 > + @param EndBit The ordinal of the most significant bit in the bit f= ield. >=20 > + Range 0..7. >=20 > + @param OrData The value to OR with the PCI configuration register. >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +EFIAPI >=20 > +PciExpressBitFieldOr8 ( >=20 > + IN UINTN Address, >=20 > + IN UINTN StartBit, >=20 > + IN UINTN EndBit, >=20 > + IN UINT8 OrData >=20 > + ) >=20 > +{ >=20 > + ASSERT_INVALID_PCI_ADDRESS (Address); >=20 > + return MmioBitFieldOr8 ( >=20 > + (UINTN) GetPciExpressBaseAddress () + Address, >=20 > + StartBit, >=20 > + EndBit, >=20 > + OrData >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Reads a bit field in an 8-bit PCI configuration register, performs a b= itwise >=20 > + AND, and writes the result back to the bit field in the 8-bit register= . >=20 > + >=20 > + Reads the 8-bit PCI configuration register specified by Address, perfo= rms a >=20 > + bitwise AND between the read result and the value specified by AndData= , > and >=20 > + writes the result to the 8-bit PCI configuration register specified by >=20 > + Address. The value written to the PCI configuration register is return= ed. >=20 > + This function must guarantee that all PCI read and write operations ar= e >=20 > + serialized. Extra left bits in AndData are stripped. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If StartBit is greater than 7, then ASSERT(). >=20 > + If EndBit is greater than 7, then ASSERT(). >=20 > + If EndBit is less than StartBit, then ASSERT(). >=20 > + If AndData is larger than the bitmask value range specified by StartBi= t and > EndBit, then ASSERT(). >=20 > + >=20 > + @param Address The PCI configuration register to write. >=20 > + @param StartBit The ordinal of the least significant bit in the bit = field. >=20 > + Range 0..7. >=20 > + @param EndBit The ordinal of the most significant bit in the bit f= ield. >=20 > + Range 0..7. >=20 > + @param AndData The value to AND with the PCI configuration register= . >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +EFIAPI >=20 > +PciExpressBitFieldAnd8 ( >=20 > + IN UINTN Address, >=20 > + IN UINTN StartBit, >=20 > + IN UINTN EndBit, >=20 > + IN UINT8 AndData >=20 > + ) >=20 > +{ >=20 > + ASSERT_INVALID_PCI_ADDRESS (Address); >=20 > + return MmioBitFieldAnd8 ( >=20 > + (UINTN) GetPciExpressBaseAddress () + Address, >=20 > + StartBit, >=20 > + EndBit, >=20 > + AndData >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Reads a bit field in an 8-bit port, performs a bitwise AND followed by= a >=20 > + bitwise OR, and writes the result back to the bit field in the >=20 > + 8-bit port. >=20 > + >=20 > + Reads the 8-bit PCI configuration register specified by Address, perfo= rms a >=20 > + bitwise AND followed by a bitwise OR between the read result and >=20 > + the value specified by AndData, and writes the result to the 8-bit PCI >=20 > + configuration register specified by Address. The value written to the = PCI >=20 > + configuration register is returned. This function must guarantee that = all PCI >=20 > + read and write operations are serialized. Extra left bits in both AndD= ata and >=20 > + OrData are stripped. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If StartBit is greater than 7, then ASSERT(). >=20 > + If EndBit is greater than 7, then ASSERT(). >=20 > + If EndBit is less than StartBit, then ASSERT(). >=20 > + If AndData is larger than the bitmask value range specified by StartBi= t and > EndBit, then ASSERT(). >=20 > + If OrData is larger than the bitmask value range specified by StartBit= and > EndBit, then ASSERT(). >=20 > + >=20 > + @param Address The PCI configuration register to write. >=20 > + @param StartBit The ordinal of the least significant bit in the bit = field. >=20 > + Range 0..7. >=20 > + @param EndBit The ordinal of the most significant bit in the bit f= ield. >=20 > + Range 0..7. >=20 > + @param AndData The value to AND with the PCI configuration register= . >=20 > + @param OrData The value to OR with the result of the AND operation= . >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +EFIAPI >=20 > +PciExpressBitFieldAndThenOr8 ( >=20 > + IN UINTN Address, >=20 > + IN UINTN StartBit, >=20 > + IN UINTN EndBit, >=20 > + IN UINT8 AndData, >=20 > + IN UINT8 OrData >=20 > + ) >=20 > +{ >=20 > + ASSERT_INVALID_PCI_ADDRESS (Address); >=20 > + return MmioBitFieldAndThenOr8 ( >=20 > + (UINTN) GetPciExpressBaseAddress () + Address, >=20 > + StartBit, >=20 > + EndBit, >=20 > + AndData, >=20 > + OrData >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Reads a 16-bit PCI configuration register. >=20 > + >=20 > + Reads and returns the 16-bit PCI configuration register specified by > Address. >=20 > + This function must guarantee that all PCI read and write operations ar= e >=20 > + serialized. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 16-bit boundary, then ASSERT(). >=20 > + >=20 > + @param Address The address that encodes the PCI Bus, Device, Function > and >=20 > + Register. >=20 > + >=20 > + @return The read value from the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT16 >=20 > +EFIAPI >=20 > +PciExpressRead16 ( >=20 > + IN UINTN Address >=20 > + ) >=20 > +{ >=20 > + ASSERT_INVALID_PCI_ADDRESS (Address); >=20 > + return MmioRead16 ((UINTN) GetPciExpressBaseAddress () + Address); >=20 > +} >=20 > + >=20 > +/** >=20 > + Writes a 16-bit PCI configuration register. >=20 > + >=20 > + Writes the 16-bit PCI configuration register specified by Address with= the >=20 > + value specified by Value. Value is returned. This function must guaran= tee >=20 > + that all PCI read and write operations are serialized. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 16-bit boundary, then ASSERT(). >=20 > + >=20 > + @param Address The address that encodes the PCI Bus, Device, Function > and >=20 > + Register. >=20 > + @param Value The value to write. >=20 > + >=20 > + @return The value written to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT16 >=20 > +EFIAPI >=20 > +PciExpressWrite16 ( >=20 > + IN UINTN Address, >=20 > + IN UINT16 Value >=20 > + ) >=20 > +{ >=20 > + ASSERT_INVALID_PCI_ADDRESS (Address); >=20 > + return MmioWrite16 ((UINTN) GetPciExpressBaseAddress () + Address, > Value); >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs a bitwise OR of a 16-bit PCI configuration register with >=20 > + a 16-bit value. >=20 > + >=20 > + Reads the 16-bit PCI configuration register specified by Address, perf= orms > a >=20 > + bitwise OR between the read result and the value specified by >=20 > + OrData, and writes the result to the 16-bit PCI configuration register >=20 > + specified by Address. The value written to the PCI configuration regis= ter is >=20 > + returned. This function must guarantee that all PCI read and write > operations >=20 > + are serialized. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 16-bit boundary, then ASSERT(). >=20 > + >=20 > + @param Address The address that encodes the PCI Bus, Device, Function > and >=20 > + Register. >=20 > + @param OrData The value to OR with the PCI configuration register. >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT16 >=20 > +EFIAPI >=20 > +PciExpressOr16 ( >=20 > + IN UINTN Address, >=20 > + IN UINT16 OrData >=20 > + ) >=20 > +{ >=20 > + ASSERT_INVALID_PCI_ADDRESS (Address); >=20 > + return MmioOr16 ((UINTN) GetPciExpressBaseAddress () + Address, > OrData); >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs a bitwise AND of a 16-bit PCI configuration register with a 1= 6-bit >=20 > + value. >=20 > + >=20 > + Reads the 16-bit PCI configuration register specified by Address, perf= orms > a >=20 > + bitwise AND between the read result and the value specified by AndData= , > and >=20 > + writes the result to the 16-bit PCI configuration register specified b= y >=20 > + Address. The value written to the PCI configuration register is return= ed. >=20 > + This function must guarantee that all PCI read and write operations ar= e >=20 > + serialized. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 16-bit boundary, then ASSERT(). >=20 > + >=20 > + @param Address The address that encodes the PCI Bus, Device, Function > and >=20 > + Register. >=20 > + @param AndData The value to AND with the PCI configuration register. >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT16 >=20 > +EFIAPI >=20 > +PciExpressAnd16 ( >=20 > + IN UINTN Address, >=20 > + IN UINT16 AndData >=20 > + ) >=20 > +{ >=20 > + ASSERT_INVALID_PCI_ADDRESS (Address); >=20 > + return MmioAnd16 ((UINTN) GetPciExpressBaseAddress () + Address, > AndData); >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs a bitwise AND of a 16-bit PCI configuration register with a 1= 6-bit >=20 > + value, followed a bitwise OR with another 16-bit value. >=20 > + >=20 > + Reads the 16-bit PCI configuration register specified by Address, perf= orms > a >=20 > + bitwise AND between the read result and the value specified by AndData= , >=20 > + performs a bitwise OR between the result of the AND operation and >=20 > + the value specified by OrData, and writes the result to the 16-bit PCI >=20 > + configuration register specified by Address. The value written to the = PCI >=20 > + configuration register is returned. This function must guarantee that = all PCI >=20 > + read and write operations are serialized. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 16-bit boundary, then ASSERT(). >=20 > + >=20 > + @param Address The address that encodes the PCI Bus, Device, Function > and >=20 > + Register. >=20 > + @param AndData The value to AND with the PCI configuration register. >=20 > + @param OrData The value to OR with the result of the AND operation. >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT16 >=20 > +EFIAPI >=20 > +PciExpressAndThenOr16 ( >=20 > + IN UINTN Address, >=20 > + IN UINT16 AndData, >=20 > + IN UINT16 OrData >=20 > + ) >=20 > +{ >=20 > + ASSERT_INVALID_PCI_ADDRESS (Address); >=20 > + return MmioAndThenOr16 ( >=20 > + (UINTN) GetPciExpressBaseAddress () + Address, >=20 > + AndData, >=20 > + OrData >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Reads a bit field of a PCI configuration register. >=20 > + >=20 > + Reads the bit field in a 16-bit PCI configuration register. The bit fi= eld is >=20 > + specified by the StartBit and the EndBit. The value of the bit field i= s >=20 > + returned. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 16-bit boundary, then ASSERT(). >=20 > + If StartBit is greater than 15, then ASSERT(). >=20 > + If EndBit is greater than 15, then ASSERT(). >=20 > + If EndBit is less than StartBit, then ASSERT(). >=20 > + >=20 > + @param Address The PCI configuration register to read. >=20 > + @param StartBit The ordinal of the least significant bit in the bit = field. >=20 > + Range 0..15. >=20 > + @param EndBit The ordinal of the most significant bit in the bit f= ield. >=20 > + Range 0..15. >=20 > + >=20 > + @return The value of the bit field read from the PCI configuration reg= ister. >=20 > + >=20 > +**/ >=20 > +UINT16 >=20 > +EFIAPI >=20 > +PciExpressBitFieldRead16 ( >=20 > + IN UINTN Address, >=20 > + IN UINTN StartBit, >=20 > + IN UINTN EndBit >=20 > + ) >=20 > +{ >=20 > + ASSERT_INVALID_PCI_ADDRESS (Address); >=20 > + return MmioBitFieldRead16 ( >=20 > + (UINTN) GetPciExpressBaseAddress () + Address, >=20 > + StartBit, >=20 > + EndBit >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Writes a bit field to a PCI configuration register. >=20 > + >=20 > + Writes Value to the bit field of the PCI configuration register. The b= it >=20 > + field is specified by the StartBit and the EndBit. All other bits in t= he >=20 > + destination PCI configuration register are preserved. The new value of= the >=20 > + 16-bit register is returned. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 16-bit boundary, then ASSERT(). >=20 > + If StartBit is greater than 15, then ASSERT(). >=20 > + If EndBit is greater than 15, then ASSERT(). >=20 > + If EndBit is less than StartBit, then ASSERT(). >=20 > + If Value is larger than the bitmask value range specified by StartBit = and > EndBit, then ASSERT(). >=20 > + >=20 > + @param Address The PCI configuration register to write. >=20 > + @param StartBit The ordinal of the least significant bit in the bit = field. >=20 > + Range 0..15. >=20 > + @param EndBit The ordinal of the most significant bit in the bit f= ield. >=20 > + Range 0..15. >=20 > + @param Value The new value of the bit field. >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT16 >=20 > +EFIAPI >=20 > +PciExpressBitFieldWrite16 ( >=20 > + IN UINTN Address, >=20 > + IN UINTN StartBit, >=20 > + IN UINTN EndBit, >=20 > + IN UINT16 Value >=20 > + ) >=20 > +{ >=20 > + ASSERT_INVALID_PCI_ADDRESS (Address); >=20 > + return MmioBitFieldWrite16 ( >=20 > + (UINTN) GetPciExpressBaseAddress () + Address, >=20 > + StartBit, >=20 > + EndBit, >=20 > + Value >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR= , and >=20 > + writes the result back to the bit field in the 16-bit port. >=20 > + >=20 > + Reads the 16-bit PCI configuration register specified by Address, perf= orms > a >=20 > + bitwise OR between the read result and the value specified by >=20 > + OrData, and writes the result to the 16-bit PCI configuration register >=20 > + specified by Address. The value written to the PCI configuration regis= ter is >=20 > + returned. This function must guarantee that all PCI read and write > operations >=20 > + are serialized. Extra left bits in OrData are stripped. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 16-bit boundary, then ASSERT(). >=20 > + If StartBit is greater than 15, then ASSERT(). >=20 > + If EndBit is greater than 15, then ASSERT(). >=20 > + If EndBit is less than StartBit, then ASSERT(). >=20 > + If OrData is larger than the bitmask value range specified by StartBit= and > EndBit, then ASSERT(). >=20 > + >=20 > + @param Address The PCI configuration register to write. >=20 > + @param StartBit The ordinal of the least significant bit in the bit = field. >=20 > + Range 0..15. >=20 > + @param EndBit The ordinal of the most significant bit in the bit f= ield. >=20 > + Range 0..15. >=20 > + @param OrData The value to OR with the PCI configuration register. >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT16 >=20 > +EFIAPI >=20 > +PciExpressBitFieldOr16 ( >=20 > + IN UINTN Address, >=20 > + IN UINTN StartBit, >=20 > + IN UINTN EndBit, >=20 > + IN UINT16 OrData >=20 > + ) >=20 > +{ >=20 > + ASSERT_INVALID_PCI_ADDRESS (Address); >=20 > + return MmioBitFieldOr16 ( >=20 > + (UINTN) GetPciExpressBaseAddress () + Address, >=20 > + StartBit, >=20 > + EndBit, >=20 > + OrData >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Reads a bit field in a 16-bit PCI configuration register, performs a b= itwise >=20 > + AND, and writes the result back to the bit field in the 16-bit registe= r. >=20 > + >=20 > + Reads the 16-bit PCI configuration register specified by Address, perf= orms > a >=20 > + bitwise AND between the read result and the value specified by AndData= , > and >=20 > + writes the result to the 16-bit PCI configuration register specified b= y >=20 > + Address. The value written to the PCI configuration register is return= ed. >=20 > + This function must guarantee that all PCI read and write operations ar= e >=20 > + serialized. Extra left bits in AndData are stripped. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 16-bit boundary, then ASSERT(). >=20 > + If StartBit is greater than 15, then ASSERT(). >=20 > + If EndBit is greater than 15, then ASSERT(). >=20 > + If EndBit is less than StartBit, then ASSERT(). >=20 > + If AndData is larger than the bitmask value range specified by StartBi= t and > EndBit, then ASSERT(). >=20 > + >=20 > + @param Address The PCI configuration register to write. >=20 > + @param StartBit The ordinal of the least significant bit in the bit = field. >=20 > + Range 0..15. >=20 > + @param EndBit The ordinal of the most significant bit in the bit f= ield. >=20 > + Range 0..15. >=20 > + @param AndData The value to AND with the PCI configuration register= . >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT16 >=20 > +EFIAPI >=20 > +PciExpressBitFieldAnd16 ( >=20 > + IN UINTN Address, >=20 > + IN UINTN StartBit, >=20 > + IN UINTN EndBit, >=20 > + IN UINT16 AndData >=20 > + ) >=20 > +{ >=20 > + ASSERT_INVALID_PCI_ADDRESS (Address); >=20 > + return MmioBitFieldAnd16 ( >=20 > + (UINTN) GetPciExpressBaseAddress () + Address, >=20 > + StartBit, >=20 > + EndBit, >=20 > + AndData >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Reads a bit field in a 16-bit port, performs a bitwise AND followed by= a >=20 > + bitwise OR, and writes the result back to the bit field in the >=20 > + 16-bit port. >=20 > + >=20 > + Reads the 16-bit PCI configuration register specified by Address, perf= orms > a >=20 > + bitwise AND followed by a bitwise OR between the read result and >=20 > + the value specified by AndData, and writes the result to the 16-bit PC= I >=20 > + configuration register specified by Address. The value written to the = PCI >=20 > + configuration register is returned. This function must guarantee that = all PCI >=20 > + read and write operations are serialized. Extra left bits in both AndD= ata and >=20 > + OrData are stripped. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 16-bit boundary, then ASSERT(). >=20 > + If StartBit is greater than 15, then ASSERT(). >=20 > + If EndBit is greater than 15, then ASSERT(). >=20 > + If EndBit is less than StartBit, then ASSERT(). >=20 > + If AndData is larger than the bitmask value range specified by StartBi= t and > EndBit, then ASSERT(). >=20 > + If OrData is larger than the bitmask value range specified by StartBit= and > EndBit, then ASSERT(). >=20 > + >=20 > + @param Address The PCI configuration register to write. >=20 > + @param StartBit The ordinal of the least significant bit in the bit = field. >=20 > + Range 0..15. >=20 > + @param EndBit The ordinal of the most significant bit in the bit f= ield. >=20 > + Range 0..15. >=20 > + @param AndData The value to AND with the PCI configuration register= . >=20 > + @param OrData The value to OR with the result of the AND operation= . >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT16 >=20 > +EFIAPI >=20 > +PciExpressBitFieldAndThenOr16 ( >=20 > + IN UINTN Address, >=20 > + IN UINTN StartBit, >=20 > + IN UINTN EndBit, >=20 > + IN UINT16 AndData, >=20 > + IN UINT16 OrData >=20 > + ) >=20 > +{ >=20 > + ASSERT_INVALID_PCI_ADDRESS (Address); >=20 > + return MmioBitFieldAndThenOr16 ( >=20 > + (UINTN) GetPciExpressBaseAddress () + Address, >=20 > + StartBit, >=20 > + EndBit, >=20 > + AndData, >=20 > + OrData >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Reads a 32-bit PCI configuration register. >=20 > + >=20 > + Reads and returns the 32-bit PCI configuration register specified by > Address. >=20 > + This function must guarantee that all PCI read and write operations ar= e >=20 > + serialized. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 32-bit boundary, then ASSERT(). >=20 > + >=20 > + @param Address The address that encodes the PCI Bus, Device, Function > and >=20 > + Register. >=20 > + >=20 > + @return The read value from the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT32 >=20 > +EFIAPI >=20 > +PciExpressRead32 ( >=20 > + IN UINTN Address >=20 > + ) >=20 > +{ >=20 > + ASSERT_INVALID_PCI_ADDRESS (Address); >=20 > + return MmioRead32 ((UINTN) GetPciExpressBaseAddress () + Address); >=20 > +} >=20 > + >=20 > +/** >=20 > + Writes a 32-bit PCI configuration register. >=20 > + >=20 > + Writes the 32-bit PCI configuration register specified by Address with= the >=20 > + value specified by Value. Value is returned. This function must guaran= tee >=20 > + that all PCI read and write operations are serialized. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 32-bit boundary, then ASSERT(). >=20 > + >=20 > + @param Address The address that encodes the PCI Bus, Device, Function > and >=20 > + Register. >=20 > + @param Value The value to write. >=20 > + >=20 > + @return The value written to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT32 >=20 > +EFIAPI >=20 > +PciExpressWrite32 ( >=20 > + IN UINTN Address, >=20 > + IN UINT32 Value >=20 > + ) >=20 > +{ >=20 > + ASSERT_INVALID_PCI_ADDRESS (Address); >=20 > + return MmioWrite32 ((UINTN) GetPciExpressBaseAddress () + Address, > Value); >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs a bitwise OR of a 32-bit PCI configuration register with >=20 > + a 32-bit value. >=20 > + >=20 > + Reads the 32-bit PCI configuration register specified by Address, perf= orms > a >=20 > + bitwise OR between the read result and the value specified by >=20 > + OrData, and writes the result to the 32-bit PCI configuration register >=20 > + specified by Address. The value written to the PCI configuration regis= ter is >=20 > + returned. This function must guarantee that all PCI read and write > operations >=20 > + are serialized. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 32-bit boundary, then ASSERT(). >=20 > + >=20 > + @param Address The address that encodes the PCI Bus, Device, Function > and >=20 > + Register. >=20 > + @param OrData The value to OR with the PCI configuration register. >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT32 >=20 > +EFIAPI >=20 > +PciExpressOr32 ( >=20 > + IN UINTN Address, >=20 > + IN UINT32 OrData >=20 > + ) >=20 > +{ >=20 > + ASSERT_INVALID_PCI_ADDRESS (Address); >=20 > + return MmioOr32 ((UINTN) GetPciExpressBaseAddress () + Address, > OrData); >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs a bitwise AND of a 32-bit PCI configuration register with a 3= 2-bit >=20 > + value. >=20 > + >=20 > + Reads the 32-bit PCI configuration register specified by Address, perf= orms > a >=20 > + bitwise AND between the read result and the value specified by AndData= , > and >=20 > + writes the result to the 32-bit PCI configuration register specified b= y >=20 > + Address. The value written to the PCI configuration register is return= ed. >=20 > + This function must guarantee that all PCI read and write operations ar= e >=20 > + serialized. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 32-bit boundary, then ASSERT(). >=20 > + >=20 > + @param Address The address that encodes the PCI Bus, Device, Function > and >=20 > + Register. >=20 > + @param AndData The value to AND with the PCI configuration register. >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT32 >=20 > +EFIAPI >=20 > +PciExpressAnd32 ( >=20 > + IN UINTN Address, >=20 > + IN UINT32 AndData >=20 > + ) >=20 > +{ >=20 > + ASSERT_INVALID_PCI_ADDRESS (Address); >=20 > + return MmioAnd32 ((UINTN) GetPciExpressBaseAddress () + Address, > AndData); >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs a bitwise AND of a 32-bit PCI configuration register with a 3= 2-bit >=20 > + value, followed a bitwise OR with another 32-bit value. >=20 > + >=20 > + Reads the 32-bit PCI configuration register specified by Address, perf= orms > a >=20 > + bitwise AND between the read result and the value specified by AndData= , >=20 > + performs a bitwise OR between the result of the AND operation and >=20 > + the value specified by OrData, and writes the result to the 32-bit PCI >=20 > + configuration register specified by Address. The value written to the = PCI >=20 > + configuration register is returned. This function must guarantee that = all PCI >=20 > + read and write operations are serialized. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 32-bit boundary, then ASSERT(). >=20 > + >=20 > + @param Address The address that encodes the PCI Bus, Device, Function > and >=20 > + Register. >=20 > + @param AndData The value to AND with the PCI configuration register. >=20 > + @param OrData The value to OR with the result of the AND operation. >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT32 >=20 > +EFIAPI >=20 > +PciExpressAndThenOr32 ( >=20 > + IN UINTN Address, >=20 > + IN UINT32 AndData, >=20 > + IN UINT32 OrData >=20 > + ) >=20 > +{ >=20 > + ASSERT_INVALID_PCI_ADDRESS (Address); >=20 > + return MmioAndThenOr32 ( >=20 > + (UINTN) GetPciExpressBaseAddress () + Address, >=20 > + AndData, >=20 > + OrData >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Reads a bit field of a PCI configuration register. >=20 > + >=20 > + Reads the bit field in a 32-bit PCI configuration register. The bit fi= eld is >=20 > + specified by the StartBit and the EndBit. The value of the bit field i= s >=20 > + returned. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 32-bit boundary, then ASSERT(). >=20 > + If StartBit is greater than 31, then ASSERT(). >=20 > + If EndBit is greater than 31, then ASSERT(). >=20 > + If EndBit is less than StartBit, then ASSERT(). >=20 > + >=20 > + @param Address The PCI configuration register to read. >=20 > + @param StartBit The ordinal of the least significant bit in the bit = field. >=20 > + Range 0..31. >=20 > + @param EndBit The ordinal of the most significant bit in the bit f= ield. >=20 > + Range 0..31. >=20 > + >=20 > + @return The value of the bit field read from the PCI configuration reg= ister. >=20 > + >=20 > +**/ >=20 > +UINT32 >=20 > +EFIAPI >=20 > +PciExpressBitFieldRead32 ( >=20 > + IN UINTN Address, >=20 > + IN UINTN StartBit, >=20 > + IN UINTN EndBit >=20 > + ) >=20 > +{ >=20 > + ASSERT_INVALID_PCI_ADDRESS (Address); >=20 > + return MmioBitFieldRead32 ( >=20 > + (UINTN) GetPciExpressBaseAddress () + Address, >=20 > + StartBit, >=20 > + EndBit >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Writes a bit field to a PCI configuration register. >=20 > + >=20 > + Writes Value to the bit field of the PCI configuration register. The b= it >=20 > + field is specified by the StartBit and the EndBit. All other bits in t= he >=20 > + destination PCI configuration register are preserved. The new value of= the >=20 > + 32-bit register is returned. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 32-bit boundary, then ASSERT(). >=20 > + If StartBit is greater than 31, then ASSERT(). >=20 > + If EndBit is greater than 31, then ASSERT(). >=20 > + If EndBit is less than StartBit, then ASSERT(). >=20 > + If Value is larger than the bitmask value range specified by StartBit = and > EndBit, then ASSERT(). >=20 > + >=20 > + @param Address The PCI configuration register to write. >=20 > + @param StartBit The ordinal of the least significant bit in the bit = field. >=20 > + Range 0..31. >=20 > + @param EndBit The ordinal of the most significant bit in the bit f= ield. >=20 > + Range 0..31. >=20 > + @param Value The new value of the bit field. >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT32 >=20 > +EFIAPI >=20 > +PciExpressBitFieldWrite32 ( >=20 > + IN UINTN Address, >=20 > + IN UINTN StartBit, >=20 > + IN UINTN EndBit, >=20 > + IN UINT32 Value >=20 > + ) >=20 > +{ >=20 > + ASSERT_INVALID_PCI_ADDRESS (Address); >=20 > + return MmioBitFieldWrite32 ( >=20 > + (UINTN) GetPciExpressBaseAddress () + Address, >=20 > + StartBit, >=20 > + EndBit, >=20 > + Value >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR= , and >=20 > + writes the result back to the bit field in the 32-bit port. >=20 > + >=20 > + Reads the 32-bit PCI configuration register specified by Address, perf= orms > a >=20 > + bitwise OR between the read result and the value specified by >=20 > + OrData, and writes the result to the 32-bit PCI configuration register >=20 > + specified by Address. The value written to the PCI configuration regis= ter is >=20 > + returned. This function must guarantee that all PCI read and write > operations >=20 > + are serialized. Extra left bits in OrData are stripped. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 32-bit boundary, then ASSERT(). >=20 > + If StartBit is greater than 31, then ASSERT(). >=20 > + If EndBit is greater than 31, then ASSERT(). >=20 > + If EndBit is less than StartBit, then ASSERT(). >=20 > + If OrData is larger than the bitmask value range specified by StartBit= and > EndBit, then ASSERT(). >=20 > + >=20 > + @param Address The PCI configuration register to write. >=20 > + @param StartBit The ordinal of the least significant bit in the bit = field. >=20 > + Range 0..31. >=20 > + @param EndBit The ordinal of the most significant bit in the bit f= ield. >=20 > + Range 0..31. >=20 > + @param OrData The value to OR with the PCI configuration register. >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT32 >=20 > +EFIAPI >=20 > +PciExpressBitFieldOr32 ( >=20 > + IN UINTN Address, >=20 > + IN UINTN StartBit, >=20 > + IN UINTN EndBit, >=20 > + IN UINT32 OrData >=20 > + ) >=20 > +{ >=20 > + ASSERT_INVALID_PCI_ADDRESS (Address); >=20 > + return MmioBitFieldOr32 ( >=20 > + (UINTN) GetPciExpressBaseAddress () + Address, >=20 > + StartBit, >=20 > + EndBit, >=20 > + OrData >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Reads a bit field in a 32-bit PCI configuration register, performs a b= itwise >=20 > + AND, and writes the result back to the bit field in the 32-bit registe= r. >=20 > + >=20 > + Reads the 32-bit PCI configuration register specified by Address, perf= orms > a >=20 > + bitwise AND between the read result and the value specified by AndData= , > and >=20 > + writes the result to the 32-bit PCI configuration register specified b= y >=20 > + Address. The value written to the PCI configuration register is return= ed. >=20 > + This function must guarantee that all PCI read and write operations ar= e >=20 > + serialized. Extra left bits in AndData are stripped. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 32-bit boundary, then ASSERT(). >=20 > + If StartBit is greater than 31, then ASSERT(). >=20 > + If EndBit is greater than 31, then ASSERT(). >=20 > + If EndBit is less than StartBit, then ASSERT(). >=20 > + If AndData is larger than the bitmask value range specified by StartBi= t and > EndBit, then ASSERT(). >=20 > + >=20 > + @param Address The PCI configuration register to write. >=20 > + @param StartBit The ordinal of the least significant bit in the bit = field. >=20 > + Range 0..31. >=20 > + @param EndBit The ordinal of the most significant bit in the bit f= ield. >=20 > + Range 0..31. >=20 > + @param AndData The value to AND with the PCI configuration register= . >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT32 >=20 > +EFIAPI >=20 > +PciExpressBitFieldAnd32 ( >=20 > + IN UINTN Address, >=20 > + IN UINTN StartBit, >=20 > + IN UINTN EndBit, >=20 > + IN UINT32 AndData >=20 > + ) >=20 > +{ >=20 > + ASSERT_INVALID_PCI_ADDRESS (Address); >=20 > + return MmioBitFieldAnd32 ( >=20 > + (UINTN) GetPciExpressBaseAddress () + Address, >=20 > + StartBit, >=20 > + EndBit, >=20 > + AndData >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Reads a bit field in a 32-bit port, performs a bitwise AND followed by= a >=20 > + bitwise OR, and writes the result back to the bit field in the >=20 > + 32-bit port. >=20 > + >=20 > + Reads the 32-bit PCI configuration register specified by Address, perf= orms > a >=20 > + bitwise AND followed by a bitwise OR between the read result and >=20 > + the value specified by AndData, and writes the result to the 32-bit PC= I >=20 > + configuration register specified by Address. The value written to the = PCI >=20 > + configuration register is returned. This function must guarantee that = all PCI >=20 > + read and write operations are serialized. Extra left bits in both AndD= ata and >=20 > + OrData are stripped. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 32-bit boundary, then ASSERT(). >=20 > + If StartBit is greater than 31, then ASSERT(). >=20 > + If EndBit is greater than 31, then ASSERT(). >=20 > + If EndBit is less than StartBit, then ASSERT(). >=20 > + If AndData is larger than the bitmask value range specified by StartBi= t and > EndBit, then ASSERT(). >=20 > + If OrData is larger than the bitmask value range specified by StartBit= and > EndBit, then ASSERT(). >=20 > + >=20 > + @param Address The PCI configuration register to write. >=20 > + @param StartBit The ordinal of the least significant bit in the bit = field. >=20 > + Range 0..31. >=20 > + @param EndBit The ordinal of the most significant bit in the bit f= ield. >=20 > + Range 0..31. >=20 > + @param AndData The value to AND with the PCI configuration register= . >=20 > + @param OrData The value to OR with the result of the AND operation= . >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT32 >=20 > +EFIAPI >=20 > +PciExpressBitFieldAndThenOr32 ( >=20 > + IN UINTN Address, >=20 > + IN UINTN StartBit, >=20 > + IN UINTN EndBit, >=20 > + IN UINT32 AndData, >=20 > + IN UINT32 OrData >=20 > + ) >=20 > +{ >=20 > + ASSERT_INVALID_PCI_ADDRESS (Address); >=20 > + return MmioBitFieldAndThenOr32 ( >=20 > + (UINTN) GetPciExpressBaseAddress () + Address, >=20 > + StartBit, >=20 > + EndBit, >=20 > + AndData, >=20 > + OrData >=20 > + ); >=20 > +} >=20 > + >=20 > +/** >=20 > + Reads a range of PCI configuration registers into a caller supplied bu= ffer. >=20 > + >=20 > + Reads the range of PCI configuration registers specified by StartAddre= ss > and >=20 > + Size into the buffer specified by Buffer. This function only allows th= e PCI >=20 > + configuration registers from a single PCI function to be read. Size is >=20 > + returned. When possible 32-bit PCI configuration read cycles are used = to > read >=20 > + from StartAdress to StartAddress + Size. Due to alignment restrictions= , 8- > bit >=20 > + and 16-bit PCI configuration read cycles may be used at the beginning = and > the >=20 > + end of the range. >=20 > + >=20 > + If StartAddress > 0x0FFFFFFF, then ASSERT(). >=20 > + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). >=20 > + If Size > 0 and Buffer is NULL, then ASSERT(). >=20 > + >=20 > + @param StartAddress The starting address that encodes the PCI Bus, > Device, >=20 > + Function and Register. >=20 > + @param Size The size in bytes of the transfer. >=20 > + @param Buffer The pointer to a buffer receiving the data read. >=20 > + >=20 > + @return Size read data from StartAddress. >=20 > + >=20 > +**/ >=20 > +UINTN >=20 > +EFIAPI >=20 > +PciExpressReadBuffer ( >=20 > + IN UINTN StartAddress, >=20 > + IN UINTN Size, >=20 > + OUT VOID *Buffer >=20 > + ) >=20 > +{ >=20 > + UINTN ReturnValue; >=20 > + >=20 > + ASSERT_INVALID_PCI_ADDRESS (StartAddress); >=20 > + ASSERT (((StartAddress & 0xFFF) + Size) <=3D 0x1000); >=20 > + >=20 > + if (Size =3D=3D 0) { >=20 > + return Size; >=20 > + } >=20 > + >=20 > + ASSERT (Buffer !=3D NULL); >=20 > + >=20 > + // >=20 > + // Save Size for return >=20 > + // >=20 > + ReturnValue =3D Size; >=20 > + >=20 > + if ((StartAddress & 1) !=3D 0) { >=20 > + // >=20 > + // Read a byte if StartAddress is byte aligned >=20 > + // >=20 > + *(volatile UINT8 *)Buffer =3D PciExpressRead8 (StartAddress); >=20 > + StartAddress +=3D sizeof (UINT8); >=20 > + Size -=3D sizeof (UINT8); >=20 > + Buffer =3D (UINT8*)Buffer + 1; >=20 > + } >=20 > + >=20 > + if (Size >=3D sizeof (UINT16) && (StartAddress & 2) !=3D 0) { >=20 > + // >=20 > + // Read a word if StartAddress is word aligned >=20 > + // >=20 > + WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 > (StartAddress)); >=20 > + >=20 > + StartAddress +=3D sizeof (UINT16); >=20 > + Size -=3D sizeof (UINT16); >=20 > + Buffer =3D (UINT16*)Buffer + 1; >=20 > + } >=20 > + >=20 > + while (Size >=3D sizeof (UINT32)) { >=20 > + // >=20 > + // Read as many double words as possible >=20 > + // >=20 > + WriteUnaligned32 ((UINT32 *) Buffer, (UINT32) PciExpressRead32 > (StartAddress)); >=20 > + >=20 > + StartAddress +=3D sizeof (UINT32); >=20 > + Size -=3D sizeof (UINT32); >=20 > + Buffer =3D (UINT32*)Buffer + 1; >=20 > + } >=20 > + >=20 > + if (Size >=3D sizeof (UINT16)) { >=20 > + // >=20 > + // Read the last remaining word if exist >=20 > + // >=20 > + WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 > (StartAddress)); >=20 > + StartAddress +=3D sizeof (UINT16); >=20 > + Size -=3D sizeof (UINT16); >=20 > + Buffer =3D (UINT16*)Buffer + 1; >=20 > + } >=20 > + >=20 > + if (Size >=3D sizeof (UINT8)) { >=20 > + // >=20 > + // Read the last remaining byte if exist >=20 > + // >=20 > + *(volatile UINT8 *)Buffer =3D PciExpressRead8 (StartAddress); >=20 > + } >=20 > + >=20 > + return ReturnValue; >=20 > +} >=20 > + >=20 > +/** >=20 > + Copies the data in a caller supplied buffer to a specified range of PC= I >=20 > + configuration space. >=20 > + >=20 > + Writes the range of PCI configuration registers specified by StartAddr= ess > and >=20 > + Size from the buffer specified by Buffer. This function only allows th= e PCI >=20 > + configuration registers from a single PCI function to be written. Size= is >=20 > + returned. When possible 32-bit PCI configuration write cycles are used= to >=20 > + write from StartAdress to StartAddress + Size. Due to alignment > restrictions, >=20 > + 8-bit and 16-bit PCI configuration write cycles may be used at the beg= inning >=20 > + and the end of the range. >=20 > + >=20 > + If StartAddress > 0x0FFFFFFF, then ASSERT(). >=20 > + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). >=20 > + If Size > 0 and Buffer is NULL, then ASSERT(). >=20 > + >=20 > + @param StartAddress The starting address that encodes the PCI Bus, > Device, >=20 > + Function and Register. >=20 > + @param Size The size in bytes of the transfer. >=20 > + @param Buffer The pointer to a buffer containing the data to w= rite. >=20 > + >=20 > + @return Size written to StartAddress. >=20 > + >=20 > +**/ >=20 > +UINTN >=20 > +EFIAPI >=20 > +PciExpressWriteBuffer ( >=20 > + IN UINTN StartAddress, >=20 > + IN UINTN Size, >=20 > + IN VOID *Buffer >=20 > + ) >=20 > +{ >=20 > + UINTN ReturnValue; >=20 > + >=20 > + ASSERT_INVALID_PCI_ADDRESS (StartAddress); >=20 > + ASSERT (((StartAddress & 0xFFF) + Size) <=3D 0x1000); >=20 > + >=20 > + if (Size =3D=3D 0) { >=20 > + return 0; >=20 > + } >=20 > + >=20 > + ASSERT (Buffer !=3D NULL); >=20 > + >=20 > + // >=20 > + // Save Size for return >=20 > + // >=20 > + ReturnValue =3D Size; >=20 > + >=20 > + if ((StartAddress & 1) !=3D 0) { >=20 > + // >=20 > + // Write a byte if StartAddress is byte aligned >=20 > + // >=20 > + PciExpressWrite8 (StartAddress, *(UINT8*)Buffer); >=20 > + StartAddress +=3D sizeof (UINT8); >=20 > + Size -=3D sizeof (UINT8); >=20 > + Buffer =3D (UINT8*)Buffer + 1; >=20 > + } >=20 > + >=20 > + if (Size >=3D sizeof (UINT16) && (StartAddress & 2) !=3D 0) { >=20 > + // >=20 > + // Write a word if StartAddress is word aligned >=20 > + // >=20 > + PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer)); >=20 > + StartAddress +=3D sizeof (UINT16); >=20 > + Size -=3D sizeof (UINT16); >=20 > + Buffer =3D (UINT16*)Buffer + 1; >=20 > + } >=20 > + >=20 > + while (Size >=3D sizeof (UINT32)) { >=20 > + // >=20 > + // Write as many double words as possible >=20 > + // >=20 > + PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32*)Buffer)); >=20 > + StartAddress +=3D sizeof (UINT32); >=20 > + Size -=3D sizeof (UINT32); >=20 > + Buffer =3D (UINT32*)Buffer + 1; >=20 > + } >=20 > + >=20 > + if (Size >=3D sizeof (UINT16)) { >=20 > + // >=20 > + // Write the last remaining word if exist >=20 > + // >=20 > + PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer)); >=20 > + StartAddress +=3D sizeof (UINT16); >=20 > + Size -=3D sizeof (UINT16); >=20 > + Buffer =3D (UINT16*)Buffer + 1; >=20 > + } >=20 > + >=20 > + if (Size >=3D sizeof (UINT8)) { >=20 > + // >=20 > + // Write the last remaining byte if exist >=20 > + // >=20 > + PciExpressWrite8 (StartAddress, *(UINT8*)Buffer); >=20 > + } >=20 > + >=20 > + return ReturnValue; >=20 > +} >=20 > diff --git a/UefiPayloadPkg/Library/BasePciLibPciExpress/PciLib.c > b/UefiPayloadPkg/Library/BasePciLibPciExpress/PciLib.c > new file mode 100644 > index 000000000000..fba5914462c8 > --- /dev/null > +++ b/UefiPayloadPkg/Library/BasePciLibPciExpress/PciLib.c > @@ -0,0 +1,1302 @@ > +/** @file >=20 > + PCI Library functions that use the 256 MB PCI Express MMIO window to > perform PCI >=20 > + Configuration cycles. Layers on PCI Express Library. >=20 > + >=20 > + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > + >=20 > +#include >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#include >=20 > +#include >=20 > + >=20 > +STATIC BOOLEAN mMMCONFEnabled; >=20 > + >=20 > +/** >=20 > + Registers a PCI device so PCI configuration registers may be accessed = after >=20 > + SetVirtualAddressMap(). >=20 > + >=20 > + Registers the PCI device specified by Address so all the PCI configura= tion > registers >=20 > + associated with that PCI device may be accessed after > SetVirtualAddressMap() is called. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + >=20 > + @param Address The address that encodes the PCI Bus, Device, Function > and >=20 > + Register. >=20 > + >=20 > + @retval RETURN_SUCCESS The PCI device was registered for run= time > access. >=20 > + @retval RETURN_UNSUPPORTED An attempt was made to call this > function >=20 > + after ExitBootServices(). >=20 > + @retval RETURN_UNSUPPORTED The resources required to access the > PCI device >=20 > + at runtime could not be mapped. >=20 > + @retval RETURN_OUT_OF_RESOURCES There are not enough resources > available to >=20 > + complete the registration. >=20 > + >=20 > +**/ >=20 > +RETURN_STATUS >=20 > +EFIAPI >=20 > +PciRegisterForRuntimeAccess ( >=20 > + IN UINTN Address >=20 > + ) >=20 > +{ >=20 > + return PciExpressRegisterForRuntimeAccess (Address); >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs platform specific initialization required for the CPU to acce= ss >=20 > + the MMCONF space. This function does not initialize the MMCONF itself= . >=20 > + >=20 > + @retval RETURN_SUCCESS The platform specific initialization succ= eeded. >=20 > + @retval RETURN_DEVICE_ERROR The platform specific initialization coul= d > not be completed. >=20 > + >=20 > +**/ >=20 > +RETURN_STATUS >=20 > +EFIAPI >=20 > +PciLibInitialize ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + EFI_HOB_GUID_TYPE *GuidHob; >=20 > + ACPI_BOARD_INFO *AcpiBoardInfoPtr; >=20 > + >=20 > + // >=20 > + // Find the acpi board information guid hob >=20 > + // >=20 > + GuidHob =3D GetFirstGuidHob (&gUefiAcpiBoardInfoGuid); >=20 > + if (GuidHob =3D=3D NULL) { >=20 > + return EFI_SUCCESS; >=20 > + } >=20 > + AcpiBoardInfoPtr =3D (ACPI_BOARD_INFO *)GET_GUID_HOB_DATA > (GuidHob); >=20 > + >=20 > + mMMCONFEnabled =3D AcpiBoardInfoPtr->PcieBaseAddress !=3D 0 && >=20 > + AcpiBoardInfoPtr->PcieBaseSize !=3D 0; >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Reads an 8-bit PCI configuration register. >=20 > + >=20 > + Reads and returns the 8-bit PCI configuration register specified by Ad= dress. >=20 > + This function must guarantee that all PCI read and write operations ar= e >=20 > + serialized. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + >=20 > + @param Address The address that encodes the PCI Bus, Device, Function > and >=20 > + Register. >=20 > + >=20 > + @return The read value from the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +EFIAPI >=20 > +PciRead8 ( >=20 > + IN UINTN Address >=20 > + ) >=20 > +{ >=20 > + if (mMMCONFEnabled) { >=20 > + return PciExpressRead8 (Address); >=20 > + } else { >=20 > + return PciCf8Read8 (Address); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Writes an 8-bit PCI configuration register. >=20 > + >=20 > + Writes the 8-bit PCI configuration register specified by Address with = the >=20 > + value specified by Value. Value is returned. This function must guaran= tee >=20 > + that all PCI read and write operations are serialized. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + >=20 > + @param Address The address that encodes the PCI Bus, Device, Function > and >=20 > + Register. >=20 > + @param Value The value to write. >=20 > + >=20 > + @return The value written to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +EFIAPI >=20 > +PciWrite8 ( >=20 > + IN UINTN Address, >=20 > + IN UINT8 Value >=20 > + ) >=20 > +{ >=20 > + if (mMMCONFEnabled) { >=20 > + return PciExpressWrite8 (Address, Value); >=20 > + } else { >=20 > + return PciCf8Write8 (Address, Value); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs a bitwise OR of an 8-bit PCI configuration register with >=20 > + an 8-bit value. >=20 > + >=20 > + Reads the 8-bit PCI configuration register specified by Address, perfo= rms a >=20 > + bitwise OR between the read result and the value specified by >=20 > + OrData, and writes the result to the 8-bit PCI configuration register >=20 > + specified by Address. The value written to the PCI configuration regis= ter is >=20 > + returned. This function must guarantee that all PCI read and write > operations >=20 > + are serialized. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + >=20 > + @param Address The address that encodes the PCI Bus, Device, Function > and >=20 > + Register. >=20 > + @param OrData The value to OR with the PCI configuration register. >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +EFIAPI >=20 > +PciOr8 ( >=20 > + IN UINTN Address, >=20 > + IN UINT8 OrData >=20 > + ) >=20 > +{ >=20 > + if (mMMCONFEnabled) { >=20 > + return PciExpressOr8 (Address, OrData); >=20 > + } else { >=20 > + return PciCf8Or8 (Address, OrData); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs a bitwise AND of an 8-bit PCI configuration register with an = 8-bit >=20 > + value. >=20 > + >=20 > + Reads the 8-bit PCI configuration register specified by Address, perfo= rms a >=20 > + bitwise AND between the read result and the value specified by AndData= , > and >=20 > + writes the result to the 8-bit PCI configuration register specified by >=20 > + Address. The value written to the PCI configuration register is return= ed. >=20 > + This function must guarantee that all PCI read and write operations ar= e >=20 > + serialized. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + >=20 > + @param Address The address that encodes the PCI Bus, Device, Function > and >=20 > + Register. >=20 > + @param AndData The value to AND with the PCI configuration register. >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +EFIAPI >=20 > +PciAnd8 ( >=20 > + IN UINTN Address, >=20 > + IN UINT8 AndData >=20 > + ) >=20 > +{ >=20 > + if (mMMCONFEnabled) { >=20 > + return PciExpressAnd8 (Address, AndData); >=20 > + } else { >=20 > + return PciCf8And8 (Address, AndData); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs a bitwise AND of an 8-bit PCI configuration register with an = 8-bit >=20 > + value, followed a bitwise OR with another 8-bit value. >=20 > + >=20 > + Reads the 8-bit PCI configuration register specified by Address, perfo= rms a >=20 > + bitwise AND between the read result and the value specified by AndData= , >=20 > + performs a bitwise OR between the result of the AND operation and >=20 > + the value specified by OrData, and writes the result to the 8-bit PCI >=20 > + configuration register specified by Address. The value written to the = PCI >=20 > + configuration register is returned. This function must guarantee that = all PCI >=20 > + read and write operations are serialized. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + >=20 > + @param Address The address that encodes the PCI Bus, Device, Function > and >=20 > + Register. >=20 > + @param AndData The value to AND with the PCI configuration register. >=20 > + @param OrData The value to OR with the result of the AND operation. >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +EFIAPI >=20 > +PciAndThenOr8 ( >=20 > + IN UINTN Address, >=20 > + IN UINT8 AndData, >=20 > + IN UINT8 OrData >=20 > + ) >=20 > +{ >=20 > + if (mMMCONFEnabled) { >=20 > + return PciExpressAndThenOr8 (Address, AndData, OrData); >=20 > + } else { >=20 > + return PciCf8AndThenOr8 (Address, AndData, OrData); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Reads a bit field of a PCI configuration register. >=20 > + >=20 > + Reads the bit field in an 8-bit PCI configuration register. The bit fi= eld is >=20 > + specified by the StartBit and the EndBit. The value of the bit field i= s >=20 > + returned. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If StartBit is greater than 7, then ASSERT(). >=20 > + If EndBit is greater than 7, then ASSERT(). >=20 > + If EndBit is less than StartBit, then ASSERT(). >=20 > + >=20 > + @param Address The PCI configuration register to read. >=20 > + @param StartBit The ordinal of the least significant bit in the bit = field. >=20 > + Range 0..7. >=20 > + @param EndBit The ordinal of the most significant bit in the bit f= ield. >=20 > + Range 0..7. >=20 > + >=20 > + @return The value of the bit field read from the PCI configuration reg= ister. >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +EFIAPI >=20 > +PciBitFieldRead8 ( >=20 > + IN UINTN Address, >=20 > + IN UINTN StartBit, >=20 > + IN UINTN EndBit >=20 > + ) >=20 > +{ >=20 > + if (mMMCONFEnabled) { >=20 > + return PciExpressBitFieldRead8 (Address, StartBit, EndBit); >=20 > + } else { >=20 > + return PciCf8BitFieldRead8 (Address, StartBit, EndBit); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Writes a bit field to a PCI configuration register. >=20 > + >=20 > + Writes Value to the bit field of the PCI configuration register. The b= it >=20 > + field is specified by the StartBit and the EndBit. All other bits in t= he >=20 > + destination PCI configuration register are preserved. The new value of= the >=20 > + 8-bit register is returned. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If StartBit is greater than 7, then ASSERT(). >=20 > + If EndBit is greater than 7, then ASSERT(). >=20 > + If EndBit is less than StartBit, then ASSERT(). >=20 > + If Value is larger than the bitmask value range specified by StartBit = and > EndBit, then ASSERT(). >=20 > + >=20 > + @param Address The PCI configuration register to write. >=20 > + @param StartBit The ordinal of the least significant bit in the bit = field. >=20 > + Range 0..7. >=20 > + @param EndBit The ordinal of the most significant bit in the bit f= ield. >=20 > + Range 0..7. >=20 > + @param Value The new value of the bit field. >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +EFIAPI >=20 > +PciBitFieldWrite8 ( >=20 > + IN UINTN Address, >=20 > + IN UINTN StartBit, >=20 > + IN UINTN EndBit, >=20 > + IN UINT8 Value >=20 > + ) >=20 > +{ >=20 > + if (mMMCONFEnabled) { >=20 > + return PciExpressBitFieldWrite8 (Address, StartBit, EndBit, Value); >=20 > + } else { >=20 > + return PciCf8BitFieldWrite8 (Address, StartBit, EndBit, Value); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR= , and >=20 > + writes the result back to the bit field in the 8-bit port. >=20 > + >=20 > + Reads the 8-bit PCI configuration register specified by Address, perfo= rms a >=20 > + bitwise OR between the read result and the value specified by >=20 > + OrData, and writes the result to the 8-bit PCI configuration register >=20 > + specified by Address. The value written to the PCI configuration regis= ter is >=20 > + returned. This function must guarantee that all PCI read and write > operations >=20 > + are serialized. Extra left bits in OrData are stripped. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If StartBit is greater than 7, then ASSERT(). >=20 > + If EndBit is greater than 7, then ASSERT(). >=20 > + If EndBit is less than StartBit, then ASSERT(). >=20 > + If OrData is larger than the bitmask value range specified by StartBit= and > EndBit, then ASSERT(). >=20 > + >=20 > + @param Address The PCI configuration register to write. >=20 > + @param StartBit The ordinal of the least significant bit in the bit = field. >=20 > + Range 0..7. >=20 > + @param EndBit The ordinal of the most significant bit in the bit f= ield. >=20 > + Range 0..7. >=20 > + @param OrData The value to OR with the PCI configuration register. >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +EFIAPI >=20 > +PciBitFieldOr8 ( >=20 > + IN UINTN Address, >=20 > + IN UINTN StartBit, >=20 > + IN UINTN EndBit, >=20 > + IN UINT8 OrData >=20 > + ) >=20 > +{ >=20 > + if (mMMCONFEnabled) { >=20 > + return PciExpressBitFieldOr8 (Address, StartBit, EndBit, OrData); >=20 > + } else { >=20 > + return PciCf8BitFieldOr8 (Address, StartBit, EndBit, OrData); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Reads a bit field in an 8-bit PCI configuration register, performs a b= itwise >=20 > + AND, and writes the result back to the bit field in the 8-bit register= . >=20 > + >=20 > + Reads the 8-bit PCI configuration register specified by Address, perfo= rms a >=20 > + bitwise AND between the read result and the value specified by AndData= , > and >=20 > + writes the result to the 8-bit PCI configuration register specified by >=20 > + Address. The value written to the PCI configuration register is return= ed. >=20 > + This function must guarantee that all PCI read and write operations ar= e >=20 > + serialized. Extra left bits in AndData are stripped. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If StartBit is greater than 7, then ASSERT(). >=20 > + If EndBit is greater than 7, then ASSERT(). >=20 > + If EndBit is less than StartBit, then ASSERT(). >=20 > + If AndData is larger than the bitmask value range specified by StartBi= t and > EndBit, then ASSERT(). >=20 > + >=20 > + @param Address The PCI configuration register to write. >=20 > + @param StartBit The ordinal of the least significant bit in the bit = field. >=20 > + Range 0..7. >=20 > + @param EndBit The ordinal of the most significant bit in the bit f= ield. >=20 > + Range 0..7. >=20 > + @param AndData The value to AND with the PCI configuration register= . >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +EFIAPI >=20 > +PciBitFieldAnd8 ( >=20 > + IN UINTN Address, >=20 > + IN UINTN StartBit, >=20 > + IN UINTN EndBit, >=20 > + IN UINT8 AndData >=20 > + ) >=20 > +{ >=20 > + if (mMMCONFEnabled) { >=20 > + return PciExpressBitFieldAnd8 (Address, StartBit, EndBit, AndData); >=20 > + } else { >=20 > + return PciCf8BitFieldAnd8 (Address, StartBit, EndBit, AndData); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Reads a bit field in an 8-bit port, performs a bitwise AND followed by= a >=20 > + bitwise OR, and writes the result back to the bit field in the >=20 > + 8-bit port. >=20 > + >=20 > + Reads the 8-bit PCI configuration register specified by Address, perfo= rms a >=20 > + bitwise AND followed by a bitwise OR between the read result and >=20 > + the value specified by AndData, and writes the result to the 8-bit PCI >=20 > + configuration register specified by Address. The value written to the = PCI >=20 > + configuration register is returned. This function must guarantee that = all PCI >=20 > + read and write operations are serialized. Extra left bits in both AndD= ata and >=20 > + OrData are stripped. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If StartBit is greater than 7, then ASSERT(). >=20 > + If EndBit is greater than 7, then ASSERT(). >=20 > + If EndBit is less than StartBit, then ASSERT(). >=20 > + If AndData is larger than the bitmask value range specified by StartBi= t and > EndBit, then ASSERT(). >=20 > + If OrData is larger than the bitmask value range specified by StartBit= and > EndBit, then ASSERT(). >=20 > + >=20 > + @param Address The PCI configuration register to write. >=20 > + @param StartBit The ordinal of the least significant bit in the bit = field. >=20 > + Range 0..7. >=20 > + @param EndBit The ordinal of the most significant bit in the bit f= ield. >=20 > + Range 0..7. >=20 > + @param AndData The value to AND with the PCI configuration register= . >=20 > + @param OrData The value to OR with the result of the AND operation= . >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT8 >=20 > +EFIAPI >=20 > +PciBitFieldAndThenOr8 ( >=20 > + IN UINTN Address, >=20 > + IN UINTN StartBit, >=20 > + IN UINTN EndBit, >=20 > + IN UINT8 AndData, >=20 > + IN UINT8 OrData >=20 > + ) >=20 > +{ >=20 > + if (mMMCONFEnabled) { >=20 > + return PciExpressBitFieldAndThenOr8 (Address, StartBit, EndBit, AndD= ata, > OrData); >=20 > + } else { >=20 > + return PciCf8BitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, > OrData); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Reads a 16-bit PCI configuration register. >=20 > + >=20 > + Reads and returns the 16-bit PCI configuration register specified by > Address. >=20 > + This function must guarantee that all PCI read and write operations ar= e >=20 > + serialized. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 16-bit boundary, then ASSERT(). >=20 > + >=20 > + @param Address The address that encodes the PCI Bus, Device, Function > and >=20 > + Register. >=20 > + >=20 > + @return The read value from the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT16 >=20 > +EFIAPI >=20 > +PciRead16 ( >=20 > + IN UINTN Address >=20 > + ) >=20 > +{ >=20 > + if (mMMCONFEnabled) { >=20 > + return PciExpressRead16 (Address); >=20 > + } else { >=20 > + return PciCf8Read16 (Address); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Writes a 16-bit PCI configuration register. >=20 > + >=20 > + Writes the 16-bit PCI configuration register specified by Address with= the >=20 > + value specified by Value. Value is returned. This function must guaran= tee >=20 > + that all PCI read and write operations are serialized. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 16-bit boundary, then ASSERT(). >=20 > + >=20 > + @param Address The address that encodes the PCI Bus, Device, Function > and >=20 > + Register. >=20 > + @param Value The value to write. >=20 > + >=20 > + @return The value written to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT16 >=20 > +EFIAPI >=20 > +PciWrite16 ( >=20 > + IN UINTN Address, >=20 > + IN UINT16 Value >=20 > + ) >=20 > +{ >=20 > + if (mMMCONFEnabled) { >=20 > + return PciExpressWrite16 (Address, Value); >=20 > + } else { >=20 > + return PciCf8Write16 (Address, Value); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs a bitwise OR of a 16-bit PCI configuration register with >=20 > + a 16-bit value. >=20 > + >=20 > + Reads the 16-bit PCI configuration register specified by Address, perf= orms > a >=20 > + bitwise OR between the read result and the value specified by >=20 > + OrData, and writes the result to the 16-bit PCI configuration register >=20 > + specified by Address. The value written to the PCI configuration regis= ter is >=20 > + returned. This function must guarantee that all PCI read and write > operations >=20 > + are serialized. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 16-bit boundary, then ASSERT(). >=20 > + >=20 > + @param Address The address that encodes the PCI Bus, Device, Function > and >=20 > + Register. >=20 > + @param OrData The value to OR with the PCI configuration register. >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT16 >=20 > +EFIAPI >=20 > +PciOr16 ( >=20 > + IN UINTN Address, >=20 > + IN UINT16 OrData >=20 > + ) >=20 > +{ >=20 > + if (mMMCONFEnabled) { >=20 > + return PciExpressOr16 (Address, OrData); >=20 > + } else { >=20 > + return PciCf8Or16 (Address, OrData); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs a bitwise AND of a 16-bit PCI configuration register with a 1= 6-bit >=20 > + value. >=20 > + >=20 > + Reads the 16-bit PCI configuration register specified by Address, perf= orms > a >=20 > + bitwise AND between the read result and the value specified by AndData= , > and >=20 > + writes the result to the 16-bit PCI configuration register specified b= y >=20 > + Address. The value written to the PCI configuration register is return= ed. >=20 > + This function must guarantee that all PCI read and write operations ar= e >=20 > + serialized. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 16-bit boundary, then ASSERT(). >=20 > + >=20 > + @param Address The address that encodes the PCI Bus, Device, Function > and >=20 > + Register. >=20 > + @param AndData The value to AND with the PCI configuration register. >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT16 >=20 > +EFIAPI >=20 > +PciAnd16 ( >=20 > + IN UINTN Address, >=20 > + IN UINT16 AndData >=20 > + ) >=20 > +{ >=20 > + if (mMMCONFEnabled) { >=20 > + return PciExpressAnd16 (Address, AndData); >=20 > + } else { >=20 > + return PciCf8And16 (Address, AndData); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs a bitwise AND of a 16-bit PCI configuration register with a 1= 6-bit >=20 > + value, followed a bitwise OR with another 16-bit value. >=20 > + >=20 > + Reads the 16-bit PCI configuration register specified by Address, perf= orms > a >=20 > + bitwise AND between the read result and the value specified by AndData= , >=20 > + performs a bitwise OR between the result of the AND operation and >=20 > + the value specified by OrData, and writes the result to the 16-bit PCI >=20 > + configuration register specified by Address. The value written to the = PCI >=20 > + configuration register is returned. This function must guarantee that = all PCI >=20 > + read and write operations are serialized. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 16-bit boundary, then ASSERT(). >=20 > + >=20 > + @param Address The address that encodes the PCI Bus, Device, Function > and >=20 > + Register. >=20 > + @param AndData The value to AND with the PCI configuration register. >=20 > + @param OrData The value to OR with the result of the AND operation. >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT16 >=20 > +EFIAPI >=20 > +PciAndThenOr16 ( >=20 > + IN UINTN Address, >=20 > + IN UINT16 AndData, >=20 > + IN UINT16 OrData >=20 > + ) >=20 > +{ >=20 > + if (mMMCONFEnabled) { >=20 > + return PciExpressAndThenOr16 (Address, AndData, OrData); >=20 > + } else { >=20 > + return PciCf8AndThenOr16 (Address, AndData, OrData); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Reads a bit field of a PCI configuration register. >=20 > + >=20 > + Reads the bit field in a 16-bit PCI configuration register. The bit fi= eld is >=20 > + specified by the StartBit and the EndBit. The value of the bit field i= s >=20 > + returned. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 16-bit boundary, then ASSERT(). >=20 > + If StartBit is greater than 15, then ASSERT(). >=20 > + If EndBit is greater than 15, then ASSERT(). >=20 > + If EndBit is less than StartBit, then ASSERT(). >=20 > + >=20 > + @param Address The PCI configuration register to read. >=20 > + @param StartBit The ordinal of the least significant bit in the bit = field. >=20 > + Range 0..15. >=20 > + @param EndBit The ordinal of the most significant bit in the bit f= ield. >=20 > + Range 0..15. >=20 > + >=20 > + @return The value of the bit field read from the PCI configuration reg= ister. >=20 > + >=20 > +**/ >=20 > +UINT16 >=20 > +EFIAPI >=20 > +PciBitFieldRead16 ( >=20 > + IN UINTN Address, >=20 > + IN UINTN StartBit, >=20 > + IN UINTN EndBit >=20 > + ) >=20 > +{ >=20 > + if (mMMCONFEnabled) { >=20 > + return PciExpressBitFieldRead16 (Address, StartBit, EndBit); >=20 > + } else { >=20 > + return PciCf8BitFieldRead16 (Address, StartBit, EndBit); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Writes a bit field to a PCI configuration register. >=20 > + >=20 > + Writes Value to the bit field of the PCI configuration register. The b= it >=20 > + field is specified by the StartBit and the EndBit. All other bits in t= he >=20 > + destination PCI configuration register are preserved. The new value of= the >=20 > + 16-bit register is returned. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 16-bit boundary, then ASSERT(). >=20 > + If StartBit is greater than 15, then ASSERT(). >=20 > + If EndBit is greater than 15, then ASSERT(). >=20 > + If EndBit is less than StartBit, then ASSERT(). >=20 > + If Value is larger than the bitmask value range specified by StartBit = and > EndBit, then ASSERT(). >=20 > + >=20 > + @param Address The PCI configuration register to write. >=20 > + @param StartBit The ordinal of the least significant bit in the bit = field. >=20 > + Range 0..15. >=20 > + @param EndBit The ordinal of the most significant bit in the bit f= ield. >=20 > + Range 0..15. >=20 > + @param Value The new value of the bit field. >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT16 >=20 > +EFIAPI >=20 > +PciBitFieldWrite16 ( >=20 > + IN UINTN Address, >=20 > + IN UINTN StartBit, >=20 > + IN UINTN EndBit, >=20 > + IN UINT16 Value >=20 > + ) >=20 > +{ >=20 > + if (mMMCONFEnabled) { >=20 > + return PciExpressBitFieldWrite16 (Address, StartBit, EndBit, Value); >=20 > + } else { >=20 > + return PciCf8BitFieldWrite16 (Address, StartBit, EndBit, Value); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR= , and >=20 > + writes the result back to the bit field in the 16-bit port. >=20 > + >=20 > + Reads the 16-bit PCI configuration register specified by Address, perf= orms > a >=20 > + bitwise OR between the read result and the value specified by >=20 > + OrData, and writes the result to the 16-bit PCI configuration register >=20 > + specified by Address. The value written to the PCI configuration regis= ter is >=20 > + returned. This function must guarantee that all PCI read and write > operations >=20 > + are serialized. Extra left bits in OrData are stripped. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 16-bit boundary, then ASSERT(). >=20 > + If StartBit is greater than 15, then ASSERT(). >=20 > + If EndBit is greater than 15, then ASSERT(). >=20 > + If EndBit is less than StartBit, then ASSERT(). >=20 > + If OrData is larger than the bitmask value range specified by StartBit= and > EndBit, then ASSERT(). >=20 > + >=20 > + @param Address The PCI configuration register to write. >=20 > + @param StartBit The ordinal of the least significant bit in the bit = field. >=20 > + Range 0..15. >=20 > + @param EndBit The ordinal of the most significant bit in the bit f= ield. >=20 > + Range 0..15. >=20 > + @param OrData The value to OR with the PCI configuration register. >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT16 >=20 > +EFIAPI >=20 > +PciBitFieldOr16 ( >=20 > + IN UINTN Address, >=20 > + IN UINTN StartBit, >=20 > + IN UINTN EndBit, >=20 > + IN UINT16 OrData >=20 > + ) >=20 > +{ >=20 > + if (mMMCONFEnabled) { >=20 > + return PciExpressBitFieldOr16 (Address, StartBit, EndBit, OrData); >=20 > + } else { >=20 > + return PciCf8BitFieldOr16 (Address, StartBit, EndBit, OrData); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Reads a bit field in a 16-bit PCI configuration register, performs a b= itwise >=20 > + AND, and writes the result back to the bit field in the 16-bit registe= r. >=20 > + >=20 > + Reads the 16-bit PCI configuration register specified by Address, perf= orms > a >=20 > + bitwise AND between the read result and the value specified by AndData= , > and >=20 > + writes the result to the 16-bit PCI configuration register specified b= y >=20 > + Address. The value written to the PCI configuration register is return= ed. >=20 > + This function must guarantee that all PCI read and write operations ar= e >=20 > + serialized. Extra left bits in AndData are stripped. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 16-bit boundary, then ASSERT(). >=20 > + If StartBit is greater than 15, then ASSERT(). >=20 > + If EndBit is greater than 15, then ASSERT(). >=20 > + If EndBit is less than StartBit, then ASSERT(). >=20 > + If AndData is larger than the bitmask value range specified by StartBi= t and > EndBit, then ASSERT(). >=20 > + >=20 > + @param Address The PCI configuration register to write. >=20 > + @param StartBit The ordinal of the least significant bit in the bit = field. >=20 > + Range 0..15. >=20 > + @param EndBit The ordinal of the most significant bit in the bit f= ield. >=20 > + Range 0..15. >=20 > + @param AndData The value to AND with the PCI configuration register= . >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT16 >=20 > +EFIAPI >=20 > +PciBitFieldAnd16 ( >=20 > + IN UINTN Address, >=20 > + IN UINTN StartBit, >=20 > + IN UINTN EndBit, >=20 > + IN UINT16 AndData >=20 > + ) >=20 > +{ >=20 > + if (mMMCONFEnabled) { >=20 > + return PciExpressBitFieldAnd16 (Address, StartBit, EndBit, AndData); >=20 > + } else { >=20 > + return PciCf8BitFieldAnd16 (Address, StartBit, EndBit, AndData); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Reads a bit field in a 16-bit port, performs a bitwise AND followed by= a >=20 > + bitwise OR, and writes the result back to the bit field in the >=20 > + 16-bit port. >=20 > + >=20 > + Reads the 16-bit PCI configuration register specified by Address, perf= orms > a >=20 > + bitwise AND followed by a bitwise OR between the read result and >=20 > + the value specified by AndData, and writes the result to the 16-bit PC= I >=20 > + configuration register specified by Address. The value written to the = PCI >=20 > + configuration register is returned. This function must guarantee that = all PCI >=20 > + read and write operations are serialized. Extra left bits in both AndD= ata and >=20 > + OrData are stripped. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 16-bit boundary, then ASSERT(). >=20 > + If StartBit is greater than 15, then ASSERT(). >=20 > + If EndBit is greater than 15, then ASSERT(). >=20 > + If EndBit is less than StartBit, then ASSERT(). >=20 > + If AndData is larger than the bitmask value range specified by StartBi= t and > EndBit, then ASSERT(). >=20 > + If OrData is larger than the bitmask value range specified by StartBit= and > EndBit, then ASSERT(). >=20 > + >=20 > + @param Address The PCI configuration register to write. >=20 > + @param StartBit The ordinal of the least significant bit in the bit = field. >=20 > + Range 0..15. >=20 > + @param EndBit The ordinal of the most significant bit in the bit f= ield. >=20 > + Range 0..15. >=20 > + @param AndData The value to AND with the PCI configuration register= . >=20 > + @param OrData The value to OR with the result of the AND operation= . >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT16 >=20 > +EFIAPI >=20 > +PciBitFieldAndThenOr16 ( >=20 > + IN UINTN Address, >=20 > + IN UINTN StartBit, >=20 > + IN UINTN EndBit, >=20 > + IN UINT16 AndData, >=20 > + IN UINT16 OrData >=20 > + ) >=20 > +{ >=20 > + if (mMMCONFEnabled) { >=20 > + return PciExpressBitFieldAndThenOr16 (Address, StartBit, EndBit, > AndData, OrData); >=20 > + } else { >=20 > + return PciCf8BitFieldAndThenOr16 (Address, StartBit, EndBit, AndData= , > OrData); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Reads a 32-bit PCI configuration register. >=20 > + >=20 > + Reads and returns the 32-bit PCI configuration register specified by > Address. >=20 > + This function must guarantee that all PCI read and write operations ar= e >=20 > + serialized. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 32-bit boundary, then ASSERT(). >=20 > + >=20 > + @param Address The address that encodes the PCI Bus, Device, Function > and >=20 > + Register. >=20 > + >=20 > + @return The read value from the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT32 >=20 > +EFIAPI >=20 > +PciRead32 ( >=20 > + IN UINTN Address >=20 > + ) >=20 > +{ >=20 > + if (mMMCONFEnabled) { >=20 > + return PciExpressRead32 (Address); >=20 > + } else { >=20 > + return PciCf8Read32 (Address); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Writes a 32-bit PCI configuration register. >=20 > + >=20 > + Writes the 32-bit PCI configuration register specified by Address with= the >=20 > + value specified by Value. Value is returned. This function must guaran= tee >=20 > + that all PCI read and write operations are serialized. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 32-bit boundary, then ASSERT(). >=20 > + >=20 > + @param Address The address that encodes the PCI Bus, Device, Function > and >=20 > + Register. >=20 > + @param Value The value to write. >=20 > + >=20 > + @return The value written to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT32 >=20 > +EFIAPI >=20 > +PciWrite32 ( >=20 > + IN UINTN Address, >=20 > + IN UINT32 Value >=20 > + ) >=20 > +{ >=20 > + if (mMMCONFEnabled) { >=20 > + return PciExpressWrite32 (Address, Value); >=20 > + } else { >=20 > + return PciCf8Write32 (Address, Value); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs a bitwise OR of a 32-bit PCI configuration register with >=20 > + a 32-bit value. >=20 > + >=20 > + Reads the 32-bit PCI configuration register specified by Address, perf= orms > a >=20 > + bitwise OR between the read result and the value specified by >=20 > + OrData, and writes the result to the 32-bit PCI configuration register >=20 > + specified by Address. The value written to the PCI configuration regis= ter is >=20 > + returned. This function must guarantee that all PCI read and write > operations >=20 > + are serialized. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 32-bit boundary, then ASSERT(). >=20 > + >=20 > + @param Address The address that encodes the PCI Bus, Device, Function > and >=20 > + Register. >=20 > + @param OrData The value to OR with the PCI configuration register. >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT32 >=20 > +EFIAPI >=20 > +PciOr32 ( >=20 > + IN UINTN Address, >=20 > + IN UINT32 OrData >=20 > + ) >=20 > +{ >=20 > + if (mMMCONFEnabled) { >=20 > + return PciExpressOr32 (Address, OrData); >=20 > + } else { >=20 > + return PciCf8Or32 (Address, OrData); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs a bitwise AND of a 32-bit PCI configuration register with a 3= 2-bit >=20 > + value. >=20 > + >=20 > + Reads the 32-bit PCI configuration register specified by Address, perf= orms > a >=20 > + bitwise AND between the read result and the value specified by AndData= , > and >=20 > + writes the result to the 32-bit PCI configuration register specified b= y >=20 > + Address. The value written to the PCI configuration register is return= ed. >=20 > + This function must guarantee that all PCI read and write operations ar= e >=20 > + serialized. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 32-bit boundary, then ASSERT(). >=20 > + >=20 > + @param Address The address that encodes the PCI Bus, Device, Function > and >=20 > + Register. >=20 > + @param AndData The value to AND with the PCI configuration register. >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT32 >=20 > +EFIAPI >=20 > +PciAnd32 ( >=20 > + IN UINTN Address, >=20 > + IN UINT32 AndData >=20 > + ) >=20 > +{ >=20 > + if (mMMCONFEnabled) { >=20 > + return PciExpressAnd32 (Address, AndData); >=20 > + } else { >=20 > + return PciCf8And32 (Address, AndData); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs a bitwise AND of a 32-bit PCI configuration register with a 3= 2-bit >=20 > + value, followed a bitwise OR with another 32-bit value. >=20 > + >=20 > + Reads the 32-bit PCI configuration register specified by Address, perf= orms > a >=20 > + bitwise AND between the read result and the value specified by AndData= , >=20 > + performs a bitwise OR between the result of the AND operation and >=20 > + the value specified by OrData, and writes the result to the 32-bit PCI >=20 > + configuration register specified by Address. The value written to the = PCI >=20 > + configuration register is returned. This function must guarantee that = all PCI >=20 > + read and write operations are serialized. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 32-bit boundary, then ASSERT(). >=20 > + >=20 > + @param Address The address that encodes the PCI Bus, Device, Function > and >=20 > + Register. >=20 > + @param AndData The value to AND with the PCI configuration register. >=20 > + @param OrData The value to OR with the result of the AND operation. >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT32 >=20 > +EFIAPI >=20 > +PciAndThenOr32 ( >=20 > + IN UINTN Address, >=20 > + IN UINT32 AndData, >=20 > + IN UINT32 OrData >=20 > + ) >=20 > +{ >=20 > + if (mMMCONFEnabled) { >=20 > + return PciExpressAndThenOr32 (Address, AndData, OrData); >=20 > + } else { >=20 > + return PciCf8AndThenOr32 (Address, AndData, OrData); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Reads a bit field of a PCI configuration register. >=20 > + >=20 > + Reads the bit field in a 32-bit PCI configuration register. The bit fi= eld is >=20 > + specified by the StartBit and the EndBit. The value of the bit field i= s >=20 > + returned. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 32-bit boundary, then ASSERT(). >=20 > + If StartBit is greater than 31, then ASSERT(). >=20 > + If EndBit is greater than 31, then ASSERT(). >=20 > + If EndBit is less than StartBit, then ASSERT(). >=20 > + >=20 > + @param Address The PCI configuration register to read. >=20 > + @param StartBit The ordinal of the least significant bit in the bit = field. >=20 > + Range 0..31. >=20 > + @param EndBit The ordinal of the most significant bit in the bit f= ield. >=20 > + Range 0..31. >=20 > + >=20 > + @return The value of the bit field read from the PCI configuration reg= ister. >=20 > + >=20 > +**/ >=20 > +UINT32 >=20 > +EFIAPI >=20 > +PciBitFieldRead32 ( >=20 > + IN UINTN Address, >=20 > + IN UINTN StartBit, >=20 > + IN UINTN EndBit >=20 > + ) >=20 > +{ >=20 > + if (mMMCONFEnabled) { >=20 > + return PciExpressBitFieldRead32 (Address, StartBit, EndBit); >=20 > + } else { >=20 > + return PciCf8BitFieldRead32 (Address, StartBit, EndBit); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Writes a bit field to a PCI configuration register. >=20 > + >=20 > + Writes Value to the bit field of the PCI configuration register. The b= it >=20 > + field is specified by the StartBit and the EndBit. All other bits in t= he >=20 > + destination PCI configuration register are preserved. The new value of= the >=20 > + 32-bit register is returned. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 32-bit boundary, then ASSERT(). >=20 > + If StartBit is greater than 31, then ASSERT(). >=20 > + If EndBit is greater than 31, then ASSERT(). >=20 > + If EndBit is less than StartBit, then ASSERT(). >=20 > + If Value is larger than the bitmask value range specified by StartBit = and > EndBit, then ASSERT(). >=20 > + >=20 > + @param Address The PCI configuration register to write. >=20 > + @param StartBit The ordinal of the least significant bit in the bit = field. >=20 > + Range 0..31. >=20 > + @param EndBit The ordinal of the most significant bit in the bit f= ield. >=20 > + Range 0..31. >=20 > + @param Value The new value of the bit field. >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT32 >=20 > +EFIAPI >=20 > +PciBitFieldWrite32 ( >=20 > + IN UINTN Address, >=20 > + IN UINTN StartBit, >=20 > + IN UINTN EndBit, >=20 > + IN UINT32 Value >=20 > + ) >=20 > +{ >=20 > + if (mMMCONFEnabled) { >=20 > + return PciExpressBitFieldWrite32 (Address, StartBit, EndBit, Value); >=20 > + } else { >=20 > + return PciCf8BitFieldWrite32 (Address, StartBit, EndBit, Value); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR= , and >=20 > + writes the result back to the bit field in the 32-bit port. >=20 > + >=20 > + Reads the 32-bit PCI configuration register specified by Address, perf= orms > a >=20 > + bitwise OR between the read result and the value specified by >=20 > + OrData, and writes the result to the 32-bit PCI configuration register >=20 > + specified by Address. The value written to the PCI configuration regis= ter is >=20 > + returned. This function must guarantee that all PCI read and write > operations >=20 > + are serialized. Extra left bits in OrData are stripped. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 32-bit boundary, then ASSERT(). >=20 > + If StartBit is greater than 31, then ASSERT(). >=20 > + If EndBit is greater than 31, then ASSERT(). >=20 > + If EndBit is less than StartBit, then ASSERT(). >=20 > + If OrData is larger than the bitmask value range specified by StartBit= and > EndBit, then ASSERT(). >=20 > + >=20 > + @param Address The PCI configuration register to write. >=20 > + @param StartBit The ordinal of the least significant bit in the bit = field. >=20 > + Range 0..31. >=20 > + @param EndBit The ordinal of the most significant bit in the bit f= ield. >=20 > + Range 0..31. >=20 > + @param OrData The value to OR with the PCI configuration register. >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT32 >=20 > +EFIAPI >=20 > +PciBitFieldOr32 ( >=20 > + IN UINTN Address, >=20 > + IN UINTN StartBit, >=20 > + IN UINTN EndBit, >=20 > + IN UINT32 OrData >=20 > + ) >=20 > +{ >=20 > + if (mMMCONFEnabled) { >=20 > + return PciExpressBitFieldOr32 (Address, StartBit, EndBit, OrData); >=20 > + } else { >=20 > + return PciCf8BitFieldOr32 (Address, StartBit, EndBit, OrData); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Reads a bit field in a 32-bit PCI configuration register, performs a b= itwise >=20 > + AND, and writes the result back to the bit field in the 32-bit registe= r. >=20 > + >=20 > + Reads the 32-bit PCI configuration register specified by Address, perf= orms > a >=20 > + bitwise AND between the read result and the value specified by AndData= , > and >=20 > + writes the result to the 32-bit PCI configuration register specified b= y >=20 > + Address. The value written to the PCI configuration register is return= ed. >=20 > + This function must guarantee that all PCI read and write operations ar= e >=20 > + serialized. Extra left bits in AndData are stripped. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 32-bit boundary, then ASSERT(). >=20 > + If StartBit is greater than 31, then ASSERT(). >=20 > + If EndBit is greater than 31, then ASSERT(). >=20 > + If EndBit is less than StartBit, then ASSERT(). >=20 > + If AndData is larger than the bitmask value range specified by StartBi= t and > EndBit, then ASSERT(). >=20 > + >=20 > + @param Address The PCI configuration register to write. >=20 > + @param StartBit The ordinal of the least significant bit in the bit = field. >=20 > + Range 0..31. >=20 > + @param EndBit The ordinal of the most significant bit in the bit f= ield. >=20 > + Range 0..31. >=20 > + @param AndData The value to AND with the PCI configuration register= . >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT32 >=20 > +EFIAPI >=20 > +PciBitFieldAnd32 ( >=20 > + IN UINTN Address, >=20 > + IN UINTN StartBit, >=20 > + IN UINTN EndBit, >=20 > + IN UINT32 AndData >=20 > + ) >=20 > +{ >=20 > + if (mMMCONFEnabled) { >=20 > + return PciExpressBitFieldAnd32 (Address, StartBit, EndBit, AndData); >=20 > + } else { >=20 > + return PciCf8BitFieldAnd32 (Address, StartBit, EndBit, AndData); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Reads a bit field in a 32-bit port, performs a bitwise AND followed by= a >=20 > + bitwise OR, and writes the result back to the bit field in the >=20 > + 32-bit port. >=20 > + >=20 > + Reads the 32-bit PCI configuration register specified by Address, perf= orms > a >=20 > + bitwise AND followed by a bitwise OR between the read result and >=20 > + the value specified by AndData, and writes the result to the 32-bit PC= I >=20 > + configuration register specified by Address. The value written to the = PCI >=20 > + configuration register is returned. This function must guarantee that = all PCI >=20 > + read and write operations are serialized. Extra left bits in both AndD= ata and >=20 > + OrData are stripped. >=20 > + >=20 > + If Address > 0x0FFFFFFF, then ASSERT(). >=20 > + If Address is not aligned on a 32-bit boundary, then ASSERT(). >=20 > + If StartBit is greater than 31, then ASSERT(). >=20 > + If EndBit is greater than 31, then ASSERT(). >=20 > + If EndBit is less than StartBit, then ASSERT(). >=20 > + If AndData is larger than the bitmask value range specified by StartBi= t and > EndBit, then ASSERT(). >=20 > + If OrData is larger than the bitmask value range specified by StartBit= and > EndBit, then ASSERT(). >=20 > + >=20 > + @param Address The PCI configuration register to write. >=20 > + @param StartBit The ordinal of the least significant bit in the bit = field. >=20 > + Range 0..31. >=20 > + @param EndBit The ordinal of the most significant bit in the bit f= ield. >=20 > + Range 0..31. >=20 > + @param AndData The value to AND with the PCI configuration register= . >=20 > + @param OrData The value to OR with the result of the AND operation= . >=20 > + >=20 > + @return The value written back to the PCI configuration register. >=20 > + >=20 > +**/ >=20 > +UINT32 >=20 > +EFIAPI >=20 > +PciBitFieldAndThenOr32 ( >=20 > + IN UINTN Address, >=20 > + IN UINTN StartBit, >=20 > + IN UINTN EndBit, >=20 > + IN UINT32 AndData, >=20 > + IN UINT32 OrData >=20 > + ) >=20 > +{ >=20 > + if (mMMCONFEnabled) { >=20 > + return PciExpressBitFieldAndThenOr32 (Address, StartBit, EndBit, > AndData, OrData); >=20 > + } else { >=20 > + return PciCf8BitFieldAndThenOr32 (Address, StartBit, EndBit, AndData= , > OrData); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Reads a range of PCI configuration registers into a caller supplied bu= ffer. >=20 > + >=20 > + Reads the range of PCI configuration registers specified by StartAddre= ss > and >=20 > + Size into the buffer specified by Buffer. This function only allows th= e PCI >=20 > + configuration registers from a single PCI function to be read. Size is >=20 > + returned. When possible 32-bit PCI configuration read cycles are used = to > read >=20 > + from StartAdress to StartAddress + Size. Due to alignment restrictions= , 8- > bit >=20 > + and 16-bit PCI configuration read cycles may be used at the beginning = and > the >=20 > + end of the range. >=20 > + >=20 > + If StartAddress > 0x0FFFFFFF, then ASSERT(). >=20 > + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). >=20 > + If Size > 0 and Buffer is NULL, then ASSERT(). >=20 > + >=20 > + @param StartAddress The starting address that encodes the PCI Bus, > Device, >=20 > + Function and Register. >=20 > + @param Size The size in bytes of the transfer. >=20 > + @param Buffer The pointer to a buffer receiving the data read. >=20 > + >=20 > + @return Size >=20 > + >=20 > +**/ >=20 > +UINTN >=20 > +EFIAPI >=20 > +PciReadBuffer ( >=20 > + IN UINTN StartAddress, >=20 > + IN UINTN Size, >=20 > + OUT VOID *Buffer >=20 > + ) >=20 > +{ >=20 > + if (mMMCONFEnabled) { >=20 > + return PciExpressReadBuffer (StartAddress, Size, Buffer); >=20 > + } else { >=20 > + return PciCf8ReadBuffer (StartAddress, Size, Buffer); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Copies the data in a caller supplied buffer to a specified range of PC= I >=20 > + configuration space. >=20 > + >=20 > + Writes the range of PCI configuration registers specified by StartAddr= ess > and >=20 > + Size from the buffer specified by Buffer. This function only allows th= e PCI >=20 > + configuration registers from a single PCI function to be written. Size= is >=20 > + returned. When possible 32-bit PCI configuration write cycles are used= to >=20 > + write from StartAdress to StartAddress + Size. Due to alignment > restrictions, >=20 > + 8-bit and 16-bit PCI configuration write cycles may be used at the beg= inning >=20 > + and the end of the range. >=20 > + >=20 > + If StartAddress > 0x0FFFFFFF, then ASSERT(). >=20 > + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). >=20 > + If Size > 0 and Buffer is NULL, then ASSERT(). >=20 > + >=20 > + @param StartAddress The starting address that encodes the PCI Bus, > Device, >=20 > + Function and Register. >=20 > + @param Size The size in bytes of the transfer. >=20 > + @param Buffer The pointer to a buffer containing the data to w= rite. >=20 > + >=20 > + @return Size written to StartAddress. >=20 > + >=20 > +**/ >=20 > +UINTN >=20 > +EFIAPI >=20 > +PciWriteBuffer ( >=20 > + IN UINTN StartAddress, >=20 > + IN UINTN Size, >=20 > + IN VOID *Buffer >=20 > + ) >=20 > +{ >=20 > + if (mMMCONFEnabled) { >=20 > + return PciExpressWriteBuffer (StartAddress, Size, Buffer); >=20 > + } else { >=20 > + return PciCf8WriteBuffer (StartAddress, Size, Buffer); >=20 > + } >=20 > +} >=20 > diff --git a/UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLib.u= ni > b/UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLib.uni > new file mode 100644 > index 000000000000..98010ef2f929 > --- /dev/null > +++ b/UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLib.uni > @@ -0,0 +1,17 @@ > +// /** @file >=20 > +// Instance of PCI Express Library using the 256 MB PCI Express MMIO > window. >=20 > +// >=20 > +// PCI Express Library that uses the 256 MB PCI Express MMIO window to > perform >=20 > +// PCI Configuration cycles. Layers on top of an I/O Library instance. >=20 > +// >=20 > +// Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved. >=20 > +// >=20 > +// SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +// >=20 > +// **/ >=20 > + >=20 > + >=20 > +#string STR_MODULE_ABSTRACT #language en-US "Instance of PCI > Express Library using the 256 MB PCI Express MMIO window" >=20 > + >=20 > +#string STR_MODULE_DESCRIPTION #language en-US "PCI Express > Library that uses the 256 MB PCI Express MMIO window to perform PCI > Configuration cycles. Layers on top of an I/O Library instance." >=20 > + >=20 > diff --git > a/UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.uni > b/UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.uni > new file mode 100644 > index 000000000000..ccc456356cf2 > --- /dev/null > +++ > b/UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.uni > @@ -0,0 +1,17 @@ > +// /** @file >=20 > +// Instance of PCI Library based on PCI Express Library. >=20 > +// >=20 > +// PCI Library that uses the 256 MB PCI Express MMIO window to perform > PCI >=20 > +// Configuration cycles. Layers on one PCI Express Library instance. >=20 > +// >=20 > +// Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved. >=20 > +// >=20 > +// SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +// >=20 > +// **/ >=20 > + >=20 > + >=20 > +#string STR_MODULE_ABSTRACT #language en-US "Instance of PCI > Library based on PCI Express Library" >=20 > + >=20 > +#string STR_MODULE_DESCRIPTION #language en-US "PCI Library tha= t > uses the 256 MB PCI Express MMIO window to perform PCI Configuration > cycles. Layers on an PCI Express Library instance." >=20 > + >=20 > -- > 2.25.4 >=20 >=20 > -=3D-=3D-=3D-=3D-=3D-=3D > Groups.io Links: You receive all messages sent to this group. >=20 > View/Reply Online (#61655): https://edk2.groups.io/g/devel/message/61655 > Mute This Topic: https://groups.io/mt/75080104/1781375 > Group Owner: devel+owner@edk2.groups.io > Unsubscribe: https://edk2.groups.io/g/devel/unsub [guo.dong@intel.com] > -=3D-=3D-=3D-=3D-=3D-=3D