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Thread-Topic: [edk2-platforms: PATCH v2 1/6] MinPlatformPkg: Add SetCacheLib library class. Thread-Index: AQHVj4J62JAoepQ3BE+3PtcQNWiXTqd0P3pA Date: Thu, 31 Oct 2019 06:00:50 +0000 Message-ID: References: <20191031002952.3860-1-chasel.chiu@intel.com> <20191031002952.3860-2-chasel.chiu@intel.com> In-Reply-To: <20191031002952.3860-2-chasel.chiu@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows x-ctpclassification: CTP_NT x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYmIyZGVkYTEtZWIzZS00OTY4LWFlYWQtZGNlM2U3ZmEzNTM2IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiRlpneVRvUTV6WU9zRWtHem5BUXRnNGxWcXlcLytoSVI1SW1ydXI4Y21rZzJZZDgrb1k5anhwRnZVcGhXMVBxZlgifQ== dlp-reaction: no-action dlp-version: 11.2.0.6 authentication-results: spf=none (sender IP is ) smtp.mailfrom=michael.a.kubacki@intel.com; x-originating-ip: [134.134.136.217] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 6b469c4f-a968-49d5-1056-08d75dc7ae9c x-ms-traffictypediagnostic: BYAPR11MB3829: x-ms-exchange-purlcount: 1 x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:10000; x-forefront-prvs: 02070414A1 x-forefront-antispam-report: SFV:NSPM;SFS:(10019020)(366004)(396003)(136003)(376002)(346002)(39860400002)(13464003)(199004)(189003)(7736002)(14444005)(99286004)(76176011)(446003)(229853002)(256004)(11346002)(66476007)(66556008)(64756008)(66446008)(3846002)(8936002)(9686003)(2501003)(7696005)(478600001)(305945005)(316002)(6306002)(6116002)(6246003)(76116006)(186003)(71190400001)(71200400001)(4326008)(66946007)(26005)(107886003)(74316002)(5660300002)(486006)(966005)(25786009)(53546011)(6506007)(54906003)(86362001)(2906002)(8676002)(66066001)(6436002)(30864003)(102836004)(55016002)(52536014)(81166006)(476003)(81156014)(14454004)(110136005)(33656002);DIR:OUT;SFP:1102;SCL:1;SRVR:BYAPR11MB3829;H:BYAPR11MB3831.namprd11.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:3; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: /3lvvpfH88Z0dC/ImgjheW8V943DIdmLvYFyqiBSJThTR/IpQQfg+5pGI3mxyT2hqUBf7LxUIy9Y/7ABMLTWnoOat4wHnjjKfY08EgiH/azzyr8mGQA+daqDzAfRkpSQndSKKv6AEmSzdUTmcQVmh77kFAFSgelOZiD7CeiN5DV1lFcxVYDPMWdcXnoB3U9bK6Qg+FH6C78sQa29tHnDNcPF9HAn1MJGLnO7jvC5f3GfUS5t15fOCOxjP6JxdEZaNPI325jmLxcFHGR/BdP3yIQzPQ/tg5VFF7+8CH0zSCOfnGIsrZY7zJ1pfSdngGNJxPHiAxSQmPiyPgiB+yyxF1rqhgevcQJExiZT7xbUJtsbnoZnL3t+RoDSnKDTz8tNklSvF48M6UStbpLNYTb5Hm5boJcuVfO8gmCocJ2J03TkDGj+ib5KfIikPIh0V53SN6R/n3QVJZOITaymmucZkMMwNKZxPDKNjhfw/Pdan2w= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 6b469c4f-a968-49d5-1056-08d75dc7ae9c X-MS-Exchange-CrossTenant-originalarrivaltime: 31 Oct 2019 06:00:50.2814 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: GLuCPrKWQpOWwFVw6egk+tRXQYBJRkqrUsPLGAOHi8c76TY1/OX93cZPowtVFBxBD/qArWXxhg1qpNzJAdOjL4BefW+ZJKa0DHYmuGEFSwc= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR11MB3829 Return-Path: michael.a.kubacki@intel.com X-OriginatorOrg: intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable 1. It would be good to list the new library class in the [LibraryClasses] section of MinPlatformPkg.dec. 2. I think it would be more descriptive to call these library instances BaseSetCacheLibNull and BaseSetCacheLib. 3. It would be helpful to provide a description somewhere such as SetCacheLib.inf that explains in what scenarios that library instance would be useful. 4. The [Pcd] tag can be removed from SetCacheLibNull.inf since the section is empty. Thanks, Michael > -----Original Message----- > From: Chiu, Chasel > Sent: Wednesday, October 30, 2019 5:30 PM > To: devel@edk2.groups.io > Cc: Kubacki, Michael A ; Desimone, Nathaniel > L ; Gao, Liming > Subject: [edk2-platforms: PATCH v2 1/6] MinPlatformPkg: Add SetCacheLib > library class. >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2314 >=20 > MinPlatformPkg should contain the library class header (API) and the NULL > library class instance. >=20 > Cc: Michael Kubacki > Cc: Nate DeSimone > Cc: Liming Gao > Signed-off-by: Chasel Chiu > --- > Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLib.c | = 325 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++ > Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLibNull.c | > 37 +++++++++++++++++++++++++++++++++++++ > Platform/Intel/MinPlatformPkg/Include/Library/SetCacheLib.h | = 34 > ++++++++++++++++++++++++++++++++++ > Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLib.inf | = 44 > ++++++++++++++++++++++++++++++++++++++++++++ > Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLibNull.inf | > 30 ++++++++++++++++++++++++++++++ > 5 files changed, 470 insertions(+) >=20 > diff --git > a/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLib.c > b/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLib.c > new file mode 100644 > index 0000000000..b5c5041430 > --- /dev/null > +++ b/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLib.c > @@ -0,0 +1,325 @@ > +/** @file > + > +SetCache library functions. > + > +Copyright (c) 2019, Intel Corporation. All rights reserved.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/** > + Set Cache Mtrr. > +**/ > +VOID > +EFIAPI > +SetCacheMtrr ( > + VOID > + ) > +{ > + EFI_STATUS Status; > + EFI_PEI_HOB_POINTERS Hob; > + MTRR_SETTINGS MtrrSetting; > + UINT64 MemoryBase; > + UINT64 MemoryLength; > + UINT64 LowMemoryLength; > + UINT64 HighMemoryLength; > + EFI_BOOT_MODE BootMode; > + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute; > + UINT64 CacheMemoryLength; > + > + /// > + /// Reset all MTRR setting. > + /// > + ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS)); > + > + /// > + /// Cache the Flash area as WP to boost performance /// Status =3D > + MtrrSetMemoryAttributeInMtrrSettings ( > + &MtrrSetting, > + (UINTN) PcdGet32 (PcdFlashAreaBaseAddress), > + (UINTN) PcdGet32 (PcdFlashAreaSize), > + CacheWriteProtected > + ); > + ASSERT_EFI_ERROR (Status); > + > + /// > + /// Update MTRR setting from MTRR buffer for Flash Region to be WP to > + boost performance /// MtrrSetAllMtrrs (&MtrrSetting); > + > + /// > + /// Set low to 1 MB. Since 1MB cacheability will always be set /// > + until override by CSM. > + /// Initialize high memory to 0. > + /// > + LowMemoryLength =3D 0x100000; > + HighMemoryLength =3D 0; > + ResourceAttribute =3D ( > + EFI_RESOURCE_ATTRIBUTE_PRESENT | > + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | > + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | > + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | > + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | > + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE > + ); > + > + Status =3D PeiServicesGetBootMode (&BootMode); ASSERT_EFI_ERROR > + (Status); > + > + if (BootMode !=3D BOOT_ON_S3_RESUME) { > + ResourceAttribute |=3D EFI_RESOURCE_ATTRIBUTE_TESTED; } > + > + Status =3D PeiServicesGetHobList ((VOID **) &Hob.Raw); while > + (!END_OF_HOB_LIST (Hob)) { > + if (Hob.Header->HobType =3D=3D EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { > + if ((Hob.ResourceDescriptor->ResourceType =3D=3D > EFI_RESOURCE_SYSTEM_MEMORY) || > + ((Hob.ResourceDescriptor->ResourceType =3D=3D > EFI_RESOURCE_MEMORY_RESERVED) && > + (Hob.ResourceDescriptor->ResourceAttribute =3D=3D ResourceAtt= ribute)) > + ) { > + if (Hob.ResourceDescriptor->PhysicalStart >=3D 0x100000000ULL) { > + HighMemoryLength +=3D Hob.ResourceDescriptor->ResourceLength; > + } else if (Hob.ResourceDescriptor->PhysicalStart >=3D 0x100000) = { > + LowMemoryLength +=3D Hob.ResourceDescriptor->ResourceLength; > + } > + } > + } > + > + Hob.Raw =3D GET_NEXT_HOB (Hob); > + } > + > + DEBUG ((DEBUG_INFO, "Memory Length (Below 4GB) =3D %lx.\n", > + LowMemoryLength)); DEBUG ((DEBUG_INFO, "Memory Length (Above > 4GB) =3D > + %lx.\n", HighMemoryLength)); > + > + /// > + /// Assume size of main memory is multiple of 256MB /// > + MemoryLength =3D (LowMemoryLength + 0xFFFFFFF) & 0xF0000000; > MemoryBase > + =3D 0; > + > + CacheMemoryLength =3D MemoryLength; > + /// > + /// Programming MTRRs to avoid override SPI region with UC when MAX > + TOLUD Length >=3D 3.5GB /// if (MemoryLength > 0xDC000000) { > + CacheMemoryLength =3D 0xC0000000; > + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( > + &MtrrSetting, > + MemoryBase, > + CacheMemoryLength, > + CacheWriteBack > + ); > + ASSERT_EFI_ERROR (Status); > + > + MemoryBase =3D 0xC0000000; > + CacheMemoryLength =3D MemoryLength - 0xC0000000; > + if (MemoryLength > 0xE0000000) { > + CacheMemoryLength =3D 0x20000000; > + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( > + &MtrrSetting, > + MemoryBase, > + CacheMemoryLength, > + CacheWriteBack > + ); > + ASSERT_EFI_ERROR (Status); > + > + MemoryBase =3D 0xE0000000; > + CacheMemoryLength =3D MemoryLength - 0xE0000000; > + } > + } > + > + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( > + &MtrrSetting, > + MemoryBase, > + CacheMemoryLength, > + CacheWriteBack > + ); > + ASSERT_EFI_ERROR (Status); > + > + if (LowMemoryLength !=3D MemoryLength) { > + MemoryBase =3D LowMemoryLength; > + MemoryLength -=3D LowMemoryLength; > + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( > + &MtrrSetting, > + MemoryBase, > + MemoryLength, > + CacheUncacheable > + ); > + ASSERT_EFI_ERROR (Status); > + } > + > + /// > + /// VGA-MMIO - 0xA0000 to 0xC0000 to be UC /// Status =3D > + MtrrSetMemoryAttributeInMtrrSettings ( > + &MtrrSetting, > + 0xA0000, > + 0x20000, > + CacheUncacheable > + ); > + ASSERT_EFI_ERROR (Status); > + > + /// > + /// Update MTRR setting from MTRR buffer /// MtrrSetAllMtrrs > + (&MtrrSetting); > + > + return ; > +} > + > +/** > + Update MTRR setting and set write back as default memory attribute. > + > + @retval EFI_SUCCESS The function completes successfully. > + @retval Others Some error occurs. > +**/ > +EFI_STATUS > +EFIAPI > +SetCacheMtrrAfterEndOfPei ( > + VOID > + ) > +{ > + EFI_STATUS Status; > + MTRR_SETTINGS MtrrSetting; > + EFI_PEI_HOB_POINTERS Hob; > + UINT64 MemoryBase; > + UINT64 MemoryLength; > + UINT64 Power2Length; > + EFI_BOOT_MODE BootMode; > + UINTN Index; > + UINT64 SmramSize; > + UINT64 SmramBase; > + EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock; > + Status =3D PeiServicesGetBootMode (&BootMode); > + ASSERT_EFI_ERROR (Status); > + > + if (BootMode =3D=3D BOOT_ON_S3_RESUME) { > + return EFI_SUCCESS; > + } > + // > + // Clear the CAR Settings > + // > + ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS)); > + > + // > + // Default Cachable attribute will be set to WB to support large > + memory size/hot plug memory // MtrrSetting.MtrrDefType &=3D > + ~((UINT64)(0xFF)); MtrrSetting.MtrrDefType |=3D (UINT64) > + CacheWriteBack; > + > + // > + // Set fixed cache for memory range below 1MB // Status =3D > + MtrrSetMemoryAttributeInMtrrSettings ( > + &MtrrSetting, > + 0x0, > + 0xA0000, > + CacheWriteBack > + ); > + ASSERT_EFI_ERROR (Status); > + > + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( > + &MtrrSetting, > + 0xA0000, > + 0x20000, > + CacheUncacheable > + ); > + ASSERT_EFI_ERROR (Status); > + > + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( > + &MtrrSetting, > + 0xC0000, > + 0x40000, > + CacheWriteProtected > + ); > + ASSERT_EFI_ERROR ( Status); > + > + // > + // PI SMM IPL can't set SMRAM to WB because at that time CPU ARCH > protocol is not available. > + // Set cacheability of SMRAM to WB here to improve SMRAM initializatio= n > performance. > + // > + SmramSize =3D 0; > + SmramBase =3D 0; > + Status =3D PeiServicesGetHobList ((VOID **) &Hob.Raw); while > + (!END_OF_HOB_LIST (Hob)) { > + if (Hob.Header->HobType =3D=3D EFI_HOB_TYPE_GUID_EXTENSION) { > + if (CompareGuid (&Hob.Guid->Name, &gEfiSmmSmramMemoryGuid)) { > + SmramHobDescriptorBlock =3D (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK > *) (Hob.Guid + 1); > + for (Index =3D 0; Index < SmramHobDescriptorBlock- > >NumberOfSmmReservedRegions; Index++) { > + if (SmramHobDescriptorBlock->Descriptor[Index].PhysicalStart > > 0x100000) { > + SmramSize +=3D SmramHobDescriptorBlock- > >Descriptor[Index].PhysicalSize; > + if (SmramBase =3D=3D 0 || SmramBase > SmramHobDescriptorBloc= k- > >Descriptor[Index].CpuStart) { > + SmramBase =3D SmramHobDescriptorBlock- > >Descriptor[Index].CpuStart; > + } > + } > + } > + break; > + } > + } > + Hob.Raw =3D GET_NEXT_HOB (Hob); > + } > + > + // > + // Set non system memory as UC > + // > + MemoryBase =3D 0x100000000; > + > + // > + // Add IED size to set whole SMRAM as WB to save MTRR count // > + MemoryLength =3D MemoryBase - (SmramBase + SmramSize); while > + (MemoryLength !=3D 0) { > + Power2Length =3D GetPowerOfTwo64 (MemoryLength); > + MemoryBase -=3D Power2Length; > + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( > + &MtrrSetting, > + MemoryBase, > + Power2Length, > + CacheUncacheable > + ); > + ASSERT_EFI_ERROR (Status); > + MemoryLength -=3D Power2Length; > + } > + > + DEBUG ((DEBUG_INFO, "PcdPciReservedMemAbove4GBLimit - 0x%lx\n", > + PcdGet64 (PcdPciReservedMemAbove4GBLimit))); > + DEBUG ((DEBUG_INFO, "PcdPciReservedMemAbove4GBBase - 0x%lx\n", > + PcdGet64 (PcdPciReservedMemAbove4GBBase))); > + if (PcdGet64 (PcdPciReservedMemAbove4GBLimit) > PcdGet64 > (PcdPciReservedMemAbove4GBBase)) { > + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( > + &MtrrSetting, > + PcdGet64 (PcdPciReservedMemAbove4GBBase), > + PcdGet64 (PcdPciReservedMemAbove4GBLimit) - P= cdGet64 > (PcdPciReservedMemAbove4GBBase) + 1, > + CacheUncacheable > + ); > + ASSERT_EFI_ERROR ( Status); > + } > + > + DEBUG ((DEBUG_INFO, "PcdPciReservedPMemAbove4GBLimit - 0x%lx\n", > + PcdGet64 (PcdPciReservedPMemAbove4GBLimit))); > + DEBUG ((DEBUG_INFO, "PcdPciReservedPMemAbove4GBBase - 0x%lx\n", > + PcdGet64 (PcdPciReservedPMemAbove4GBBase))); > + if (PcdGet64 (PcdPciReservedPMemAbove4GBLimit) > PcdGet64 > (PcdPciReservedPMemAbove4GBBase)) { > + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( > + &MtrrSetting, > + PcdGet64 (PcdPciReservedPMemAbove4GBBase), > + PcdGet64 (PcdPciReservedPMemAbove4GBLimit) - = PcdGet64 > (PcdPciReservedPMemAbove4GBBase) + 1, > + CacheUncacheable > + ); > + ASSERT_EFI_ERROR ( Status); > + } > + > + // > + // Update MTRR setting from MTRR buffer // MtrrSetAllMtrrs > + (&MtrrSetting); > + > + return Status; > +} > diff --git > a/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLibNull.c > b/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLibNull.c > new file mode 100644 > index 0000000000..581bc7648b > --- /dev/null > +++ b/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLibNull. > +++ c > @@ -0,0 +1,37 @@ > +/** @file > + > +NULL instances of SetCache library functions. > + > +Copyright (c) 2019, Intel Corporation. All rights reserved.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > +#include > +#include > +#include > + > +/** > + Set Cache Mtrr. > +**/ > +VOID > +EFIAPI > +SetCacheMtrr ( > + VOID > + ) > +{ > + return; > +} > + > +/** > + Update MTRR setting and set write back as default memory attribute. > + > + @retval EFI_SUCCESS The function completes successfully. > +**/ > +EFI_STATUS > +EFIAPI > +SetCacheMtrrAfterEndOfPei ( > + VOID > + ) > +{ > + return EFI_SUCCESS; > +} > diff --git a/Platform/Intel/MinPlatformPkg/Include/Library/SetCacheLib.h > b/Platform/Intel/MinPlatformPkg/Include/Library/SetCacheLib.h > new file mode 100644 > index 0000000000..d67426cef7 > --- /dev/null > +++ b/Platform/Intel/MinPlatformPkg/Include/Library/SetCacheLib.h > @@ -0,0 +1,34 @@ > +/** @file > + > +Header for SetCache library functions. > + > +Copyright (c) 2019, Intel Corporation. All rights reserved.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#ifndef _SET_CACHE_LIB_H_ > +#define _SET_CACHE_LIB_H_ > + > +/** > + Set Cache Mtrr. > +**/ > +VOID > +EFIAPI > +SetCacheMtrr ( > + VOID > + ); > + > +/** > + Update MTRR setting and set write back as default memory attribute. > + > + @retval EFI_SUCCESS The function completes successfully. > + @retval Others Some error occurs. > +**/ > +EFI_STATUS > +EFIAPI > +SetCacheMtrrAfterEndOfPei ( > + VOID > + ); > + > +#endif > diff --git > a/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLib.inf > b/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLib.inf > new file mode 100644 > index 0000000000..a53aed858f > --- /dev/null > +++ b/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLib.inf > @@ -0,0 +1,44 @@ > +## @file > +# Component information file for Platform SetCache Library # # > +Copyright (c) 2019, Intel Corporation. All rights reserved.
# # > +SPDX-License-Identifier: BSD-2-Clause-Patent # ## > + > +[Defines] > + INF_VERSION =3D 0x00010005 > + BASE_NAME =3D SetCacheLib > + FILE_GUID =3D 9F2A2899-3AD7-4176-9B89-33B3AC456A9= 9 > + MODULE_TYPE =3D BASE > + VERSION_STRING =3D 1.0 > + LIBRARY_CLASS =3D SetCacheLib > + > +[LibraryClasses] > + BaseLib > + PcdLib > + DebugLib > + HobLib > + MtrrLib > + PeiServicesLib > + BaseMemoryLib > + > +[Packages] > + MinPlatformPkg/MinPlatformPkg.dec > + MdePkg/MdePkg.dec > + UefiCpuPkg/UefiCpuPkg.dec > + > +[Sources] > + SetCacheLib.c > + > +[Guids] > + gEfiSmmSmramMemoryGuid ## CONSUMES > + > +[Pcd] > + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase > ## CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit > ## > +CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBBase > ## > +CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBLimit > ## > +CONSUMES > diff --git > a/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLibNull.inf > b/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLibNull.inf > new file mode 100644 > index 0000000000..50419b398b > --- /dev/null > +++ b/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLibNull. > +++ inf > @@ -0,0 +1,30 @@ > +## @file > +# Component information file for Platform SetCache Library # # > +Copyright (c) 2019, Intel Corporation. All rights reserved.
# # > +SPDX-License-Identifier: BSD-2-Clause-Patent # ## > + > +[Defines] > + INF_VERSION =3D 0x00010005 > + BASE_NAME =3D SetCacheLibNull > + FILE_GUID =3D D1ED4CD7-AD20-4943-9192-3ABE766A941= 1 > + MODULE_TYPE =3D BASE > + VERSION_STRING =3D 1.0 > + LIBRARY_CLASS =3D SetCacheLib > + > +[LibraryClasses] > + BaseLib > + PcdLib > + DebugLib > + > +[Packages] > + MinPlatformPkg/MinPlatformPkg.dec > + MdePkg/MdePkg.dec > + > +[Sources] > + SetCacheLibNull.c > + > +[Pcd] > -- > 2.13.3.windows.1