From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mx.groups.io with SMTP id smtpd.web09.3702.1572541355522825213 for ; Thu, 31 Oct 2019 10:02:35 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@intel.onmicrosoft.com header.s=selector2-intel-onmicrosoft-com header.b=vbu0XQrN; spf=pass (domain: intel.com, ip: 134.134.136.126, mailfrom: michael.a.kubacki@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 31 Oct 2019 10:02:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,252,1569308400"; d="scan'208";a="211605315" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by fmsmga001.fm.intel.com with ESMTP; 31 Oct 2019 10:02:34 -0700 Received: from fmsmsx101.amr.corp.intel.com (10.18.124.199) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 31 Oct 2019 10:02:33 -0700 Received: from FMSEDG002.ED.cps.intel.com (10.1.192.134) by fmsmsx101.amr.corp.intel.com (10.18.124.199) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 31 Oct 2019 10:02:33 -0700 Received: from NAM03-DM3-obe.outbound.protection.outlook.com (104.47.41.55) by edgegateway.intel.com (192.55.55.69) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 31 Oct 2019 10:02:33 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Z53Bjs9VQsFTEQKy1sLmyrtTqnXXeF/vah48jh6onLaQlQohVCPMIDcClg+0qV5EzhJKucEwAqXjcgapn2UqCIvIxlDCDe4w+3/KS9LtwfH/ienqXJZY1Lymz7SEgCG9wNupknStjpWOdJ8rLajqqdf6z/PeoJMa5NtyOBm3+aVYOyH/ymsjjY349XCOADJV67kjDv2Gg2ws3HcR8HCudYN70Zfz/6Soj53rI/Wl+Gd3TAX+NYb1u5rBpTiHTgs2icoNDKQSfSJnmW8v2tH+/yUMvW4s4d3LjgkcE4Kd6jo/vwZO6Sk4eicMzyyrhjmM5egIkLszDwfX54ETW1yH9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=dqus7B3nZud5pglsIYjWb4RXUExVy0U8VZvzwnCAeuc=; b=OaSPt/TFqVIvm3TZmXlKo+PHooPyp4X7e+ROITqb+RMmHLTyfje1J9TduikzNP3VBii0w0ZW5K2e+MJ7oFQtu8ve3cls9wqZZm6oQz9r/yu72s+kWEy/ugn2BCEiF33csKO6uXHXZS9oNtYbvxWLHpneJcyH4X884R5GMMWuAsrf2XVwPOJjUdwoC5CfhXMZUCrgDHtAtCCrylK8jk9Y62bwBIvn3oi7meigxHsdUx76McIayA8xzrdQnkraI29pisvVKFmzKMpGR44eeSnnqpA9cqIIeDlmbV8qAR0cTlP154vgjyqzZRJj4ADjI7F8cVvX7IpDFVLiTLoEfsFRyg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=intel.onmicrosoft.com; s=selector2-intel-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=dqus7B3nZud5pglsIYjWb4RXUExVy0U8VZvzwnCAeuc=; b=vbu0XQrNZiW9TXUWjldx9NK42OFB+5+Q+tD7dFmoA2Oimd+0GFnPFN9O24wITViZRX3kh/3la8uOo6apYxFBvI962QHX9m2fkUJCQG6DesRaEMnvap9fbiMxRKdtGiLlO+A4cScHcZ+FGbiNuqHe9y1HuT+peJiKoPL7CFhoPNo= Received: from BYAPR11MB3831.namprd11.prod.outlook.com (20.178.239.150) by BYAPR11MB3575.namprd11.prod.outlook.com (20.178.206.97) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2387.22; Thu, 31 Oct 2019 17:02:13 +0000 Received: from BYAPR11MB3831.namprd11.prod.outlook.com ([fe80::1d66:1307:6b66:a78f]) by BYAPR11MB3831.namprd11.prod.outlook.com ([fe80::1d66:1307:6b66:a78f%5]) with mapi id 15.20.2387.028; Thu, 31 Oct 2019 17:02:13 +0000 From: "Kubacki, Michael A" To: "devel@edk2.groups.io" , "Chiu, Chasel" CC: "Desimone, Nathaniel L" , "Gao, Liming" Subject: Re: [edk2-devel] [edk2-platforms: PATCH v3 1/6] MinPlatformPkg: Add SetCacheMtrrLib library class. Thread-Topic: [edk2-devel] [edk2-platforms: PATCH v3 1/6] MinPlatformPkg: Add SetCacheMtrrLib library class. Thread-Index: AQHVj9X8At6+3lIY802vmxQWUmk20qd09llA Date: Thu, 31 Oct 2019 17:02:12 +0000 Message-ID: References: <20191031102817.17096-1-chasel.chiu@intel.com> <20191031102817.17096-2-chasel.chiu@intel.com> In-Reply-To: <20191031102817.17096-2-chasel.chiu@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows x-ctpclassification: CTP_NT x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMTYzZDNlNmEtZjQ1Yi00Njc2LWE4OWEtMzdjZGI2OTljYTg0IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoicWV1QmIwUFwvOVwvSEIyUVVydXdMcHZsYmNDSFhUXC91N0JVVlYxNHZ1azhXTWFubEpIdWN2bFB2VDd1aEswTjZpeiJ9 dlp-reaction: no-action dlp-version: 11.2.0.6 authentication-results: spf=none (sender IP is ) smtp.mailfrom=michael.a.kubacki@intel.com; x-originating-ip: [134.134.136.217] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: de5a8d2f-f0d2-436b-3a27-08d75e241345 x-ms-traffictypediagnostic: BYAPR11MB3575: x-ms-exchange-purlcount: 4 x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:9508; x-forefront-prvs: 02070414A1 x-forefront-antispam-report: SFV:NSPM;SFS:(10019020)(376002)(39850400004)(366004)(136003)(346002)(396003)(13464003)(199004)(189003)(99286004)(52536014)(14444005)(25786009)(6306002)(478600001)(54906003)(446003)(11346002)(256004)(76116006)(6436002)(110136005)(5660300002)(8936002)(14454004)(9686003)(66946007)(19627235002)(71200400001)(71190400001)(86362001)(2906002)(33656002)(486006)(30864003)(2501003)(476003)(74316002)(6506007)(53546011)(6246003)(7696005)(76176011)(55016002)(102836004)(26005)(7736002)(6636002)(966005)(4326008)(305945005)(66066001)(3846002)(107886003)(81166006)(316002)(81156014)(229853002)(64756008)(66446008)(66556008)(66476007)(6116002)(8676002)(186003)(579004);DIR:OUT;SFP:1102;SCL:1;SRVR:BYAPR11MB3575;H:BYAPR11MB3831.namprd11.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: uY7N2wEoNimTZx+vfJwM2/lJD2XmlCic0gG4i1fLHlguiWF1/CUdxkroZQCAzmYGoXUBWPIu7X1lYApxg1eGCKiRypd09A6/lBrJq31n4EbeKMXma7P/y8VY9lev8vG6YG48+q84V1XeIjhLsNYyiACX+7o7GLvtnOhOEhbV5hEVbMBPDXDWDXefIKjGEcfSU/q5n1xP7e7fz7UZrwnDlUVdVJ8Rl+LPjICKWTpiWnPHjZQ9jqogfBOgdmA3dIIn453U6EGAAICvzgSbW0rUucIoIYPbGG/bXymiY6U8kofqKAzDO83ofN0VzfhW3g68PCmDn33Zq8BUXMAGNdvpp10pXNgtrKrPKD8B+z72U6irtpSQxT0KuaS7UwmlSUWLvKnEqF9v/0JqzCNIA/ZA9/YKiQUxIu+Dw1pHWXXop63Dt6yjufiwesZOhgCSco3cNYY4gxf3/YEDbZNZ+ME9O1TXWGZHyolmOwqLIv/7WnA= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: de5a8d2f-f0d2-436b-3a27-08d75e241345 X-MS-Exchange-CrossTenant-originalarrivaltime: 31 Oct 2019 17:02:12.9942 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jMwwl7jEL5oa1R1+gsWhAzic+z8raNtJrcJ4AQdmGEkiNtdhbsQqrv7aMY8LVZr2ECUOp1C3nTlcf6ekiIb1D2XB8+jBy7ua5QVHg8V+UBw= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR11MB3575 Return-Path: michael.a.kubacki@intel.com X-OriginatorOrg: intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Thanks for updating the name. Platform\Intel\MinPlatformPkg\Include\Library\SetCacheMtrrLib.h: * The function description for SetCacheMtrrAfterEndOfPei () is constraining the implementation in a way that I don't believe is required: /** Update MTRR setting and set write back as default memory attribute. @retval EFI_SUCCESS The function completes successfully. @retval Others Some error occurs. **/ While it is typical to set the default memory type to WB, I don't think this API should care whether that is the case. * "SetCacheMtrrAtEndOfPei ()" better describes the way this is actually being used but I don't think it is a must change. With the function description updated: Reviewed-by: Michael Kubacki > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of Chiu, > Chasel > Sent: Thursday, October 31, 2019 3:28 AM > To: devel@edk2.groups.io > Cc: Kubacki, Michael A ; Desimone, Nathanie= l > L ; Gao, Liming > Subject: [edk2-devel] [edk2-platforms: PATCH v3 1/6] MinPlatformPkg: Add > SetCacheMtrrLib library class. >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2314 >=20 > MinPlatformPkg should contain the library class header (API) and the NUL= L > library class instance. >=20 > Cc: Michael Kubacki > Cc: Nate DeSimone > Cc: Liming Gao > Signed-off-by: Chasel Chiu > --- > Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c > | 327 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++ >=20 > Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLibN > ull.c | 37 +++++++++++++++++++++++++++++++++++++ > Platform/Intel/MinPlatformPkg/Include/Library/SetCacheMtrrLib.h = | > 34 ++++++++++++++++++++++++++++++++++ >=20 > Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.in > f | 46 ++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLibN > ull.inf | 29 +++++++++++++++++++++++++++++ > Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec = | 6 > ++++-- > 6 files changed, 477 insertions(+), 2 deletions(-) >=20 > diff --git > a/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib > .c > b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib > .c > new file mode 100644 > index 0000000000..26f06321f7 > --- /dev/null > +++ > b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrr > +++ Lib.c > @@ -0,0 +1,327 @@ > +/** @file > + > +SetCacheMtrr library functions. > +This implementation is for typical platforms and may not be needed when > +cache MTRR will be initialized by FSP. > + > +Copyright (c) 2019, Intel Corporation. All rights reserved.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/** > + Set Cache Mtrr. > +**/ > +VOID > +EFIAPI > +SetCacheMtrr ( > + VOID > + ) > +{ > + EFI_STATUS Status; > + EFI_PEI_HOB_POINTERS Hob; > + MTRR_SETTINGS MtrrSetting; > + UINT64 MemoryBase; > + UINT64 MemoryLength; > + UINT64 LowMemoryLength; > + UINT64 HighMemoryLength; > + EFI_BOOT_MODE BootMode; > + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute; > + UINT64 CacheMemoryLength; > + > + /// > + /// Reset all MTRR setting. > + /// > + ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS)); > + > + /// > + /// Cache the Flash area as WP to boost performance /// Status =3D > + MtrrSetMemoryAttributeInMtrrSettings ( > + &MtrrSetting, > + (UINTN) PcdGet32 (PcdFlashAreaBaseAddress), > + (UINTN) PcdGet32 (PcdFlashAreaSize), > + CacheWriteProtected > + ); > + ASSERT_EFI_ERROR (Status); > + > + /// > + /// Update MTRR setting from MTRR buffer for Flash Region to be WP to > + boost performance /// MtrrSetAllMtrrs (&MtrrSetting); > + > + /// > + /// Set low to 1 MB. Since 1MB cacheability will always be set /// > + until override by CSM. > + /// Initialize high memory to 0. > + /// > + LowMemoryLength =3D 0x100000; > + HighMemoryLength =3D 0; > + ResourceAttribute =3D ( > + EFI_RESOURCE_ATTRIBUTE_PRESENT | > + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | > + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | > + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | > + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | > + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE > + ); > + > + Status =3D PeiServicesGetBootMode (&BootMode); ASSERT_EFI_ERROR > + (Status); > + > + if (BootMode !=3D BOOT_ON_S3_RESUME) { > + ResourceAttribute |=3D EFI_RESOURCE_ATTRIBUTE_TESTED; } > + > + Status =3D PeiServicesGetHobList ((VOID **) &Hob.Raw); while > + (!END_OF_HOB_LIST (Hob)) { > + if (Hob.Header->HobType =3D=3D EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { > + if ((Hob.ResourceDescriptor->ResourceType =3D=3D > EFI_RESOURCE_SYSTEM_MEMORY) || > + ((Hob.ResourceDescriptor->ResourceType =3D=3D > EFI_RESOURCE_MEMORY_RESERVED) && > + (Hob.ResourceDescriptor->ResourceAttribute =3D=3D ResourceAt= tribute)) > + ) { > + if (Hob.ResourceDescriptor->PhysicalStart >=3D 0x100000000ULL) = { > + HighMemoryLength +=3D Hob.ResourceDescriptor->ResourceLength; > + } else if (Hob.ResourceDescriptor->PhysicalStart >=3D 0x100000)= { > + LowMemoryLength +=3D Hob.ResourceDescriptor->ResourceLength; > + } > + } > + } > + > + Hob.Raw =3D GET_NEXT_HOB (Hob); > + } > + > + DEBUG ((DEBUG_INFO, "Memory Length (Below 4GB) =3D %lx.\n", > + LowMemoryLength)); DEBUG ((DEBUG_INFO, "Memory Length (Above > 4GB) =3D > + %lx.\n", HighMemoryLength)); > + > + /// > + /// Assume size of main memory is multiple of 256MB /// > + MemoryLength =3D (LowMemoryLength + 0xFFFFFFF) & 0xF0000000; > MemoryBase > + =3D 0; > + > + CacheMemoryLength =3D MemoryLength; > + /// > + /// Programming MTRRs to avoid override SPI region with UC when MAX > + TOLUD Length >=3D 3.5GB /// if (MemoryLength > 0xDC000000) { > + CacheMemoryLength =3D 0xC0000000; > + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( > + &MtrrSetting, > + MemoryBase, > + CacheMemoryLength, > + CacheWriteBack > + ); > + ASSERT_EFI_ERROR (Status); > + > + MemoryBase =3D 0xC0000000; > + CacheMemoryLength =3D MemoryLength - 0xC0000000; > + if (MemoryLength > 0xE0000000) { > + CacheMemoryLength =3D 0x20000000; > + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( > + &MtrrSetting, > + MemoryBase, > + CacheMemoryLength, > + CacheWriteBack > + ); > + ASSERT_EFI_ERROR (Status); > + > + MemoryBase =3D 0xE0000000; > + CacheMemoryLength =3D MemoryLength - 0xE0000000; > + } > + } > + > + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( > + &MtrrSetting, > + MemoryBase, > + CacheMemoryLength, > + CacheWriteBack > + ); > + ASSERT_EFI_ERROR (Status); > + > + if (LowMemoryLength !=3D MemoryLength) { > + MemoryBase =3D LowMemoryLength; > + MemoryLength -=3D LowMemoryLength; > + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( > + &MtrrSetting, > + MemoryBase, > + MemoryLength, > + CacheUncacheable > + ); > + ASSERT_EFI_ERROR (Status); > + } > + > + /// > + /// VGA-MMIO - 0xA0000 to 0xC0000 to be UC /// Status =3D > + MtrrSetMemoryAttributeInMtrrSettings ( > + &MtrrSetting, > + 0xA0000, > + 0x20000, > + CacheUncacheable > + ); > + ASSERT_EFI_ERROR (Status); > + > + /// > + /// Update MTRR setting from MTRR buffer /// MtrrSetAllMtrrs > + (&MtrrSetting); > + > + return ; > +} > + > +/** > + Update MTRR setting and set write back as default memory attribute. > + > + @retval EFI_SUCCESS The function completes successfully. > + @retval Others Some error occurs. > +**/ > +EFI_STATUS > +EFIAPI > +SetCacheMtrrAfterEndOfPei ( > + VOID > + ) > +{ > + EFI_STATUS Status; > + MTRR_SETTINGS MtrrSetting; > + EFI_PEI_HOB_POINTERS Hob; > + UINT64 MemoryBase; > + UINT64 MemoryLength; > + UINT64 Power2Length; > + EFI_BOOT_MODE BootMode; > + UINTN Index; > + UINT64 SmramSize; > + UINT64 SmramBase; > + EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock; > + Status =3D PeiServicesGetBootMode (&BootMode); > + ASSERT_EFI_ERROR (Status); > + > + if (BootMode =3D=3D BOOT_ON_S3_RESUME) { > + return EFI_SUCCESS; > + } > + // > + // Clear the CAR Settings > + // > + ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS)); > + > + // > + // Default Cachable attribute will be set to WB to support large > + memory size/hot plug memory // MtrrSetting.MtrrDefType &=3D > + ~((UINT64)(0xFF)); MtrrSetting.MtrrDefType |=3D (UINT64) > + CacheWriteBack; > + > + // > + // Set fixed cache for memory range below 1MB // Status =3D > + MtrrSetMemoryAttributeInMtrrSettings ( > + &MtrrSetting, > + 0x0, > + 0xA0000, > + CacheWriteBack > + ); > + ASSERT_EFI_ERROR (Status); > + > + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( > + &MtrrSetting, > + 0xA0000, > + 0x20000, > + CacheUncacheable > + ); > + ASSERT_EFI_ERROR (Status); > + > + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( > + &MtrrSetting, > + 0xC0000, > + 0x40000, > + CacheWriteProtected > + ); > + ASSERT_EFI_ERROR ( Status); > + > + // > + // PI SMM IPL can't set SMRAM to WB because at that time CPU ARCH > protocol is not available. > + // Set cacheability of SMRAM to WB here to improve SMRAM initializati= on > performance. > + // > + SmramSize =3D 0; > + SmramBase =3D 0; > + Status =3D PeiServicesGetHobList ((VOID **) &Hob.Raw); while > + (!END_OF_HOB_LIST (Hob)) { > + if (Hob.Header->HobType =3D=3D EFI_HOB_TYPE_GUID_EXTENSION) { > + if (CompareGuid (&Hob.Guid->Name, &gEfiSmmSmramMemoryGuid)) { > + SmramHobDescriptorBlock =3D (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK > *) (Hob.Guid + 1); > + for (Index =3D 0; Index < SmramHobDescriptorBlock- > >NumberOfSmmReservedRegions; Index++) { > + if (SmramHobDescriptorBlock->Descriptor[Index].PhysicalStart = > > 0x100000) { > + SmramSize +=3D SmramHobDescriptorBlock- > >Descriptor[Index].PhysicalSize; > + if (SmramBase =3D=3D 0 || SmramBase > SmramHobDescriptorBlo= ck- > >Descriptor[Index].CpuStart) { > + SmramBase =3D SmramHobDescriptorBlock- > >Descriptor[Index].CpuStart; > + } > + } > + } > + break; > + } > + } > + Hob.Raw =3D GET_NEXT_HOB (Hob); > + } > + > + // > + // Set non system memory as UC > + // > + MemoryBase =3D 0x100000000; > + > + // > + // Add IED size to set whole SMRAM as WB to save MTRR count // > + MemoryLength =3D MemoryBase - (SmramBase + SmramSize); while > + (MemoryLength !=3D 0) { > + Power2Length =3D GetPowerOfTwo64 (MemoryLength); > + MemoryBase -=3D Power2Length; > + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( > + &MtrrSetting, > + MemoryBase, > + Power2Length, > + CacheUncacheable > + ); > + ASSERT_EFI_ERROR (Status); > + MemoryLength -=3D Power2Length; > + } > + > + DEBUG ((DEBUG_INFO, "PcdPciReservedMemAbove4GBLimit - 0x%lx\n", > + PcdGet64 (PcdPciReservedMemAbove4GBLimit))); > + DEBUG ((DEBUG_INFO, "PcdPciReservedMemAbove4GBBase - 0x%lx\n", > + PcdGet64 (PcdPciReservedMemAbove4GBBase))); > + if (PcdGet64 (PcdPciReservedMemAbove4GBLimit) > PcdGet64 > (PcdPciReservedMemAbove4GBBase)) { > + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( > + &MtrrSetting, > + PcdGet64 (PcdPciReservedMemAbove4GBBase), > + PcdGet64 (PcdPciReservedMemAbove4GBLimit) - = PcdGet64 > (PcdPciReservedMemAbove4GBBase) + 1, > + CacheUncacheable > + ); > + ASSERT_EFI_ERROR ( Status); > + } > + > + DEBUG ((DEBUG_INFO, "PcdPciReservedPMemAbove4GBLimit - 0x%lx\n", > + PcdGet64 (PcdPciReservedPMemAbove4GBLimit))); > + DEBUG ((DEBUG_INFO, "PcdPciReservedPMemAbove4GBBase - 0x%lx\n", > + PcdGet64 (PcdPciReservedPMemAbove4GBBase))); > + if (PcdGet64 (PcdPciReservedPMemAbove4GBLimit) > PcdGet64 > (PcdPciReservedPMemAbove4GBBase)) { > + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( > + &MtrrSetting, > + PcdGet64 (PcdPciReservedPMemAbove4GBBase), > + PcdGet64 (PcdPciReservedPMemAbove4GBLimit) -= PcdGet64 > (PcdPciReservedPMemAbove4GBBase) + 1, > + CacheUncacheable > + ); > + ASSERT_EFI_ERROR ( Status); > + } > + > + // > + // Update MTRR setting from MTRR buffer // MtrrSetAllMtrrs > + (&MtrrSetting); > + > + return Status; > +} > diff --git > a/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib > Null.c > b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib > Null.c > new file mode 100644 > index 0000000000..4f40de35f4 > --- /dev/null > +++ > b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrr > +++ LibNull.c > @@ -0,0 +1,37 @@ > +/** @file > + > +NULL instances of SetCacheMtrr library functions. > + > +Copyright (c) 2019, Intel Corporation. All rights reserved.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > +#include > +#include > +#include > + > +/** > + Set Cache Mtrr. > +**/ > +VOID > +EFIAPI > +SetCacheMtrr ( > + VOID > + ) > +{ > + return; > +} > + > +/** > + Update MTRR setting and set write back as default memory attribute. > + > + @retval EFI_SUCCESS The function completes successfully. > +**/ > +EFI_STATUS > +EFIAPI > +SetCacheMtrrAfterEndOfPei ( > + VOID > + ) > +{ > + return EFI_SUCCESS; > +} > diff --git > a/Platform/Intel/MinPlatformPkg/Include/Library/SetCacheMtrrLib.h > b/Platform/Intel/MinPlatformPkg/Include/Library/SetCacheMtrrLib.h > new file mode 100644 > index 0000000000..0fb566dfcc > --- /dev/null > +++ b/Platform/Intel/MinPlatformPkg/Include/Library/SetCacheMtrrLib.h > @@ -0,0 +1,34 @@ > +/** @file > + > +Header for SetCacheMtrr library functions. > + > +Copyright (c) 2019, Intel Corporation. All rights reserved.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#ifndef _SET_CACHE_MTRR_LIB_H_ > +#define _SET_CACHE_MTRR_LIB_H_ > + > +/** > + Set Cache Mtrr. > +**/ > +VOID > +EFIAPI > +SetCacheMtrr ( > + VOID > + ); > + > +/** > + Update MTRR setting and set write back as default memory attribute. > + > + @retval EFI_SUCCESS The function completes successfully. > + @retval Others Some error occurs. > +**/ > +EFI_STATUS > +EFIAPI > +SetCacheMtrrAfterEndOfPei ( > + VOID > + ); > + > +#endif > diff --git > a/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib > .inf > b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib > .inf > new file mode 100644 > index 0000000000..0cfdda414b > --- /dev/null > +++ > b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrr > +++ Lib.inf > @@ -0,0 +1,46 @@ > +## @file > +# Component information file for Platform SetCacheMtrr Library. > +# This library implementation is for typical platforms and may not be # > +needed when cache MTRR will be initialized by FSP. > +# > +# Copyright (c) 2019, Intel Corporation. All rights reserved.
# # > +SPDX-License-Identifier: BSD-2-Clause-Patent # ## > + > +[Defines] > + INF_VERSION =3D 0x00010005 > + BASE_NAME =3D PeiSetCacheMtrrLib > + FILE_GUID =3D 9F2A2899-3AD7-4176-9B89-33B3AC456A= 99 > + MODULE_TYPE =3D PEIM > + VERSION_STRING =3D 1.0 > + LIBRARY_CLASS =3D SetCacheMtrrLib > + > +[LibraryClasses] > + BaseLib > + PcdLib > + DebugLib > + HobLib > + MtrrLib > + PeiServicesLib > + BaseMemoryLib > + > +[Packages] > + MinPlatformPkg/MinPlatformPkg.dec > + MdePkg/MdePkg.dec > + UefiCpuPkg/UefiCpuPkg.dec > + > +[Sources] > + SetCacheMtrrLib.c > + > +[Guids] > + gEfiSmmSmramMemoryGuid ## CONSUMES > + > +[Pcd] > + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase > ## CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit > ## > +CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBBase > ## > +CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBLimit > ## > +CONSUMES > diff --git > a/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib > Null.inf > b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib > Null.inf > new file mode 100644 > index 0000000000..433bd47331 > --- /dev/null > +++ > b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrr > +++ LibNull.inf > @@ -0,0 +1,29 @@ > +## @file > +# Component information file for Platform SetCacheMtrr Library. > +# > +# Copyright (c) 2019, Intel Corporation. All rights reserved.
# # > +SPDX-License-Identifier: BSD-2-Clause-Patent # ## > + > +[Defines] > + INF_VERSION =3D 0x00010005 > + BASE_NAME =3D BaseSetCacheMtrrLibNull > + FILE_GUID =3D D1ED4CD7-AD20-4943-9192-3ABE766A94= 11 > + MODULE_TYPE =3D BASE > + VERSION_STRING =3D 1.0 > + LIBRARY_CLASS =3D SetCacheMtrrLib > + > +[LibraryClasses] > + BaseLib > + PcdLib > + DebugLib > + > +[Packages] > + MinPlatformPkg/MinPlatformPkg.dec > + MdePkg/MdePkg.dec > + > +[Sources] > + SetCacheMtrrLibNull.c > + > diff --git a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec > b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec > index d79f5ec1bd..a851021c0b 100644 > --- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec > +++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec > @@ -65,6 +65,8 @@ SecBoardInitLib|Include/Library/SecBoardInitLib.h > TestPointLib|Include/Library/TestPointLib.h > TestPointCheckLib|Include/Library/TestPointCheckLib.h >=20 > +SetCacheMtrrLib|Include/Library/SetCacheMtrrLib.h > + > [PcdsFixedAtBuild, PcdsPatchableInModule] >=20 >=20 > gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|FALSE|BOOLE > AN|0x80000008 > @@ -204,11 +206,11 @@ > gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0|UINT32|0x90000 > 019 > gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemBase > |0x90000000 |UINT32|0x40010043 > gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemLimit > |0x00000000 |UINT32|0x40010044 > gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase > |0xFFFFFFFFFFFFFFFF |UINT64|0x40010045 > - gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit > |0x0000000000000000 |UINT64|0x40010046 > + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit > + |0x0000000000000000 |UINT64|0x40010046 > gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemBase > |0xFFFFFFFF |UINT32|0x40010047 > gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemLimit > |0x00000000 |UINT32|0x40010048 > gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBBase > |0xFFFFFFFFFFFFFFFF |UINT64|0x40010049 > - > gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBLimit|0x > 0000000000000000 |UINT64|0x4001004A > + > + > gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBLimit|0x > 000000 > + 0000000000 |UINT64|0x4001004A > gMinPlatformPkgTokenSpaceGuid.PcdPciDmaAbove4G > |FALSE|BOOLEAN|0x4001004B > gMinPlatformPkgTokenSpaceGuid.PcdPciNoExtendedConfigSpace > |FALSE|BOOLEAN|0x4001004C > gMinPlatformPkgTokenSpaceGuid.PcdPciResourceAssigned > |FALSE|BOOLEAN|0x4001004D > -- > 2.13.3.windows.1 >=20 >=20 >=20