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b=PXm2ZL76ZwTix0sqNrwvaokTirfVNtBHeSIlQqGoLLPpn4IjVHPY5vIE2cSGoth6M ozoqh/EQanIpgNm93GUGWE+cBQQC+UiTJEj3Exm/CDMCuIRNl/toYxAhXzVzwzpBej A/TFWhXkk2vsyERJIJuk0JQR086ZgWPpCrz1OfB071Z6p9dew35Ipbi/g7e0WWqhe7 1lYJ4tOSoD6WnQb6jqJw6CKXgA5q7PbpRHlmglxc2iZAMdpbfTqPoiAnj+BNBnWHfE bLBxal6Aiw8/NeMQv+TI9Igk6bTkFSzPqWaGOV890SBEsLGamuzSKn7ENjabMEcfhw r1Ejn9FNTc/Lw== Subject: Re: [PATCH v3 2/2] MdeModulePkg/SdMmcPciHcDxe: Add V4 64bit SDMA and ADMA2 support. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 27 Nov 2018 19:34:39 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hello, Any feedback on this patch yet? Thanks Ashish -----Original Message----- From: Ashish Singhal =20 Sent: Monday, November 19, 2018 1:59 PM To: edk2-devel@lists.01.org Cc: Ashish Singhal Subject: [PATCH v3 2/2] MdeModulePkg/SdMmcPciHcDxe: Add V4 64bit SDMA and= =20ADMA2 support. If V4 64 bit address mode is enabled in compatibility register, program c= ontroller to enable V4 host mode. Use appropriate ADMA2 descriptors supporting 64 bit addresses. Use appropriate registers for SDMA mode operation. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ashish Singhal --- =20MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 4 +- =20MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 273 +++++++++++++= ++++---- =20MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 28 ++- =203 files changed, 260 insertions(+), 45 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h b/MdeModu= lePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h index c683600..22795df 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h @@ -2,6 +2,7 @@ =20 =20 Provides some data structure definitions used by the SD/MMC host con= troller driver. =20 +Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. =20Copyright (c) 2015, Intel Corporation. All rights reserved.
This = program and the accompanying materials are licensed and made available u= nder the terms and conditions of the BSD License @@ -144,7 +145,8 @@ type= def struct { =20 BOOLEAN Started; =20 UINT64 Timeout; =20 - SD_MMC_HC_ADMA_DESC_LINE *AdmaDesc; + SD_MMC_HC_ADMA_32_DESC_LINE *Adma32Desc; + SD_MMC_HC_ADMA_64_DESC_LINE *Adma64Desc; =20 EFI_PHYSICAL_ADDRESS AdmaDescPhy; =20 VOID *AdmaMap; =20 UINT32 AdmaPages; diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c b/MdeModule= Pkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c index e506875..9fef3fb 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c @@ -4,6 +4,7 @@ =20 =20 It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use. =20 + Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. =20 Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved. =20 This program and the accompanying materials =20 are licensed and made available under the terms and conditions of th= e BSD License @@ -418,6 +419,36 @@ SdMmcHcWaitMmioSet ( } =20 =20/** + Get the controller version information from the specified slot. + + @param[in] PciIo The PCI IO protocol instance. + @param[in] Slot The slot number of the SD card to send the= =20command to. + @param[out] Version The buffer to store the version informatio= n. + + @retval EFI_SUCCESS The operation executes successfully. + @retval Others The operation fails. + +**/ +EFI_STATUS +SdMmcHcGetControllerVersion ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN UINT8 Slot, + OUT UINT16 *Version + ) +{ + EFI_STATUS Status; + + Status =3D SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CTRL_VER, TRUE, sizeo= f=20 + (UINT16), Version); if (EFI_ERROR (Status)) { + return Status; + } + + *Version &=3D 0xFF; + + return EFI_SUCCESS; +} + +/** =20 Software reset the specified SD/MMC host controller and enable all i= nterrupts. =20 =20 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA in= stance. @@ -776,18 +807,18 @@ SdMmcHcClockSupply ( =20 =20 DEBUG ((DEBUG_INFO, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n"= , BaseClkFreq, Divisor, ClockFreq)); =20 - Status =3D SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CTRL_VER, TRUE, sizeo= f (ControllerVer), &ControllerVer); + Status =3D SdMmcHcGetControllerVersion (PciIo, Slot, &ControllerVer); =20 if (EFI_ERROR (Status)) { =20 return Status; =20 } =20 // =20 // Set SDCLK Frequency Select and Internal Clock Enable fields in Cl= ock Control register. =20 // - if (((ControllerVer & 0xFF) >=3D SD_MMC_HC_CTRL_VER_300) && - ((ControllerVer & 0xFF) <=3D SD_MMC_HC_CTRL_VER_420)) { + if ((ControllerVer >=3D SD_MMC_HC_CTRL_VER_300) && + (ControllerVer <=3D SD_MMC_HC_CTRL_VER_420)) { =20 ASSERT (Divisor <=3D 0x3FF); =20 ClockCtrl =3D ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2); - } else if (((ControllerVer & 0xFF) =3D=3D 0) || ((ControllerVer & 0xFF= ) =3D=3D 1)) { + } else if ((ControllerVer =3D=3D 0) || (ControllerVer =3D=3D 1)) { =20 // =20 // Only the most significant bit can be used as divisor. =20 // @@ -935,6 +966,54 @@ SdMmcHcSetBusWidth ( } =20 =20/** + Configure V4 64 bit system address support at initialization. + + @param[in] PciIo The PCI IO protocol instance. + @param[in] Slot The slot number of the SD card to send the c= ommand to. + @param[in] Capability The capability of the slot. + + @retval EFI_SUCCESS The clock is supplied successfully. + +**/ +EFI_STATUS +SdMmcHcV4Init64BitSupport ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN UINT8 Slot, + IN SD_MMC_HC_SLOT_CAP Capability + ) +{ + EFI_STATUS Status; + UINT16 ControllerVer; + UINT16 HostCtrl2; + + // + // Check if V4 64bit support is available // Status =3D=20 + SdMmcHcGetControllerVersion (PciIo, Slot, &ControllerVer); if=20 + (EFI_ERROR (Status)) { + return Status; + } + + if (ControllerVer >=3D SD_MMC_HC_CTRL_VER_400) { + HostCtrl2 =3D SD_MMC_HC_V4_EN; + // + // Check if V4 64bit support is available + // + if (Capability.SysBus64V4 =3D=3D TRUE) { + HostCtrl2 |=3D SD_MMC_HC_64_ADDR_EN; + DEBUG ((DEBUG_INFO, "Enabled V4 64 bit system bus support\n")); + } + Status =3D SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof = (HostCtrl2), &HostCtrl2); + if (EFI_ERROR (Status)) { + return Status; + } + DEBUG ((DEBUG_INFO, "Enabled V4 64 bit system bus support\n")); } + + return EFI_SUCCESS; +} + +/** =20 Supply SD/MMC card with lowest clock frequency at initialization. =20 =20 @param[in] PciIo The PCI IO protocol instance. @@ -1101,6 +1180,11 @@ SdMmcHcInitHost ( =20 PciIo =3D Private->PciIo; =20 Capability =3D Private->Capability[Slot]; =20 + Status =3D SdMmcHcV4Init64BitSupport (PciIo, Slot, Capability); if=20 + (EFI_ERROR (Status)) { + return Status; + } + =20 Status =3D SdMmcHcInitClockFreq (PciIo, Slot, Capability); =20 if (EFI_ERROR (Status)) { =20 return Status; @@ -1169,7 +1253,7 @@ SdMmcHcLedOnOff ( =20/** =20 Build ADMA descriptor table for transfer. =20 - Refer to SD Host Controller Simplified spec 3.0 Section 1.13 for detai= ls. + Refer to SD Host Controller Simplified spec 4.2 Section 1.13 for detai= ls. =20 =20 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.= =20 @@ -1187,49 +1271,69 @@ BuildAdmaDescTable ( =20 UINT64 Entries; =20 UINT32 Index; =20 UINT64 Remaining; - UINT32 Address; + UINT64 Address; =20 UINTN TableSize; =20 EFI_PCI_IO_PROTOCOL *PciIo; =20 EFI_STATUS Status; =20 UINTN Bytes; + UINT16 ControllerVer; + BOOLEAN AddressingMode64 =3D FALSE; + UINTN DescSize =3D sizeof (SD_MMC_HC_ADMA_32_DESC_= LINE); + VOID *AdmaDesc =3D NULL; =20 =20 Data =3D Trb->DataPhy; =20 DataLen =3D Trb->DataLen; =20 PciIo =3D Trb->Private->PciIo; + + // + // Detect whether 64bit addressing is supported. =20 // - // Only support 32bit ADMA Descriptor Table + Status =3D SdMmcHcGetControllerVersion (PciIo, Trb->Slot,=20 + &ControllerVer); if (EFI_ERROR (Status)) { + return Status; + } + if (ControllerVer >=3D SD_MMC_HC_CTRL_VER_400) { + Status =3D SdMmcHcCheckMmioSet(PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL= 2, 0x2, + SD_MMC_HC_V4_EN|SD_MMC_HC_64_ADDR_EN, S= D_MMC_HC_V4_EN|SD_MMC_HC_64_ADDR_EN); + if (!EFI_ERROR (Status)) { + AddressingMode64 =3D TRUE; + DescSize =3D sizeof (SD_MMC_HC_ADMA_64_DESC_LINE); + } + } =20 // - if ((Data >=3D 0x100000000ul) || ((Data + DataLen) > 0x100000000ul)) {= + // Check for valid ranges in 32bit ADMA Descriptor Table // if=20 + (AddressingMode64 =3D=3D FALSE && + ((Data >=3D 0x100000000ul) || ((Data + DataLen) > 0x100000000ul)))= =20 + { =20 return EFI_INVALID_PARAMETER; =20 } =20 // =20 // Address field shall be set on 32-bit boundary (Lower 2-bit is alw= ays set to 0) - // for 32-bit address descriptor table. =20 // =20 if ((Data & (BIT0 | BIT1)) !=3D 0) { =20 DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is n= ot aligned to 4 bytes boundary!\n", Data)); =20 } =20 =20 Entries =3D DivU64x32 ((DataLen + ADMA_MAX_DATA_PER_LINE - 1), ADM= A_MAX_DATA_PER_LINE); - TableSize =3D (UINTN)MultU64x32 (Entries, sizeof (SD_MMC_HC_ADMA_DESC_= LINE)); + TableSize =3D (UINTN)MultU64x32 (Entries, DescSize); =20 Trb->AdmaPages =3D (UINT32)EFI_SIZE_TO_PAGES (TableSize); =20 Status =3D PciIo->AllocateBuffer ( =20 PciIo, =20 AllocateAnyPages, =20 EfiBootServicesData, =20 EFI_SIZE_TO_PAGES (TableSize), - (VOID **)&Trb->AdmaDesc, + (VOID **)&AdmaDesc, =20 0 =20 ); =20 if (EFI_ERROR (Status)) { =20 return EFI_OUT_OF_RESOURCES; =20 } - ZeroMem (Trb->AdmaDesc, TableSize); + ZeroMem (AdmaDesc, TableSize); =20 Bytes =3D TableSize; =20 Status =3D PciIo->Map ( =20 PciIo, =20 EfiPciIoOperationBusMasterCommonBuffer, - Trb->AdmaDesc, + AdmaDesc, =20 &Bytes, =20 &Trb->AdmaDescPhy, =20 &Trb->AdmaMap @@ -1242,12 +1346,13 @@ BuildAdmaDescTable ( =20 PciIo->FreeBuffer ( =20 PciIo, =20 EFI_SIZE_TO_PAGES (TableSize), - Trb->AdmaDesc + AdmaDesc =20 ); =20 return EFI_OUT_OF_RESOURCES; =20 } =20 - if ((UINT64)(UINTN)Trb->AdmaDescPhy > 0x100000000ul) { + if ((AddressingMode64 =3D=3D FALSE) && + (UINT64)(UINTN)Trb->AdmaDescPhy > 0x100000000ul) { =20 // =20 // The ADMA doesn't support 64bit addressing. =20 // @@ -1258,25 +1363,49 @@ BuildAdmaDescTable ( =20 PciIo->FreeBuffer ( =20 PciIo, =20 EFI_SIZE_TO_PAGES (TableSize), - Trb->AdmaDesc + AdmaDesc =20 ); =20 return EFI_DEVICE_ERROR; =20 } =20 =20 Remaining =3D DataLen; - Address =3D (UINT32)Data; + Address =3D Data; + if (AddressingMode64 =3D=3D FALSE) { + Trb->Adma32Desc =3D AdmaDesc; + Trb->Adma64Desc =3D NULL; + } else { + Trb->Adma64Desc =3D AdmaDesc; + Trb->Adma32Desc =3D NULL; + } =20 for (Index =3D 0; Index < Entries; Index++) { - if (Remaining <=3D ADMA_MAX_DATA_PER_LINE) { - Trb->AdmaDesc[Index].Valid =3D 1; - Trb->AdmaDesc[Index].Act =3D 2; - Trb->AdmaDesc[Index].Length =3D (UINT16)Remaining; - Trb->AdmaDesc[Index].Address =3D Address; - break; + if (AddressingMode64 =3D=3D FALSE) { + if (Remaining < ADMA_MAX_DATA_PER_LINE) { + Trb->Adma32Desc[Index].Valid =3D 1; + Trb->Adma32Desc[Index].Act =3D 2; + Trb->Adma32Desc[Index].Length =3D (UINT16)Remaining; + Trb->Adma32Desc[Index].Address =3D (UINT32)Address; + break; + } else { + Trb->Adma32Desc[Index].Valid =3D 1; + Trb->Adma32Desc[Index].Act =3D 2; + Trb->Adma32Desc[Index].Length =3D 0; + Trb->Adma32Desc[Index].Address =3D (UINT32)Address; + } =20 } else { - Trb->AdmaDesc[Index].Valid =3D 1; - Trb->AdmaDesc[Index].Act =3D 2; - Trb->AdmaDesc[Index].Length =3D 0; - Trb->AdmaDesc[Index].Address =3D Address; + if (Remaining < ADMA_MAX_DATA_PER_LINE) { + Trb->Adma64Desc[Index].Valid =3D 1; + Trb->Adma64Desc[Index].Act =3D 2; + Trb->Adma64Desc[Index].Length =3D (UINT16)Remaining; + Trb->Adma64Desc[Index].LowerAddress =3D (UINT32)(Address & MAX_U= INT32); + Trb->Adma64Desc[Index].UpperAddress =3D (UINT32)(Address>>32); + break; + } else { + Trb->Adma64Desc[Index].Valid =3D 1; + Trb->Adma64Desc[Index].Act =3D 2; + Trb->Adma64Desc[Index].Length =3D 0; + Trb->Adma64Desc[Index].LowerAddress =3D (UINT32)(Address & MAX_U= INT32); + Trb->Adma64Desc[Index].UpperAddress =3D (UINT32)(Address>>32); + } =20 } =20 =20 Remaining -=3D ADMA_MAX_DATA_PER_LINE; @@ -1286,7 +1415,7 @@ Build= AdmaDescTable ( =20 // =20 // Set the last descriptor line as end of descriptor table =20 // - Trb->AdmaDesc[Index].End =3D 1; + AddressingMode64 ? (Trb->Adma64Desc[Index].End =3D 1) :=20 + (Trb->Adma32Desc[Index].End =3D 1); =20 return EFI_SUCCESS; =20} =20 @@ -1430,11 +1559,18 @@ SdMmcFreeTrb ( =20 Trb->AdmaMap =20 ); =20 } - if (Trb->AdmaDesc !=3D NULL) { + if (Trb->Adma32Desc !=3D NULL) { =20 PciIo->FreeBuffer ( =20 PciIo, =20 Trb->AdmaPages, - Trb->AdmaDesc + Trb->Adma32Desc + ); + } + if (Trb->Adma64Desc !=3D NULL) { + PciIo->FreeBuffer ( + PciIo, + Trb->AdmaPages, + Trb->Adma64Desc =20 ); =20 } =20 if (Trb->DataMap !=3D NULL) { @@ -1574,12 +1710,14 @@ SdMmcExecTrb ( =20 UINT16 Cmd; =20 UINT16 IntStatus; =20 UINT32 Argument; - UINT16 BlkCount; + UINT32 BlkCount; =20 UINT16 BlkSize; =20 UINT16 TransMode; =20 UINT8 HostCtrl1; - UINT32 SdmaAddr; + UINT64 SdmaAddr; =20 UINT64 AdmaAddr; + UINT16 ControllerVer; + BOOLEAN AddressingMode64 =3D FALSE; =20 =20 Packet =3D Trb->Packet; =20 PciIo =3D Trb->Private->PciIo; @@ -1612,13 +1750,33 @@ SdMmcExecTrb ( =20 =20 SdMmcHcLedOnOff (PciIo, Trb->Slot, TRUE); =20 + Status =3D SdMmcHcGetControllerVersion (PciIo, Trb->Slot,=20 + &ControllerVer); if (EFI_ERROR (Status)) { + return Status; + } + if (ControllerVer >=3D SD_MMC_HC_CTRL_VER_400) { + Status =3D SdMmcHcCheckMmioSet(PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL= 2, 0x2, + SD_MMC_HC_V4_EN|SD_MMC_HC_64_ADDR_EN, S= D_MMC_HC_V4_EN|SD_MMC_HC_64_ADDR_EN); + if (!EFI_ERROR (Status)) { + AddressingMode64 =3D TRUE; + } + } + =20 if (Trb->Mode =3D=3D SdMmcSdmaMode) { - if ((UINT64)(UINTN)Trb->DataPhy >=3D 0x100000000ul) { + if ((AddressingMode64 =3D=3D FALSE) && + ((UINT64)(UINTN)Trb->DataPhy >=3D 0x100000000ul)) { =20 return EFI_INVALID_PARAMETER; =20 } =20 - SdmaAddr =3D (UINT32)(UINTN)Trb->DataPhy; - Status =3D SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, F= ALSE, sizeof (SdmaAddr), &SdmaAddr); + SdmaAddr =3D (UINT64)(UINTN)Trb->DataPhy; + + if (ControllerVer >=3D SD_MMC_HC_CTRL_VER_400) { + Status =3D SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADD= R, FALSE, sizeof (UINT64), &SdmaAddr); + } + else { + Status =3D SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, F= ALSE, sizeof (UINT32), &SdmaAddr); + } + =20 if (EFI_ERROR (Status)) { =20 return Status; =20 } @@ -1648,9 +1806,14 @@ SdMmcExecTrb ( =20 // =20 // Calcuate Block Count. =20 // - BlkCount =3D (UINT16)(Trb->DataLen / Trb->BlockSize); + BlkCount =3D (Trb->DataLen / Trb->BlockSize); } if (ControllerVer = + >=3D SD_MMC_HC_CTRL_VER_410) { + Status =3D SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR,=20 + FALSE, sizeof (UINT32), &BlkCount); } else { + Status =3D SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_COUNT,=20 + FALSE, sizeof (UINT16), &BlkCount); =20 } - Status =3D SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_COUNT, FAL= SE, sizeof (BlkCount), &BlkCount); =20 if (EFI_ERROR (Status)) { =20 return Status; =20 } @@ -1746,10 +1909,11 @@ SdMmcCheckTrbResult ( =20 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet; =20 UINT16 IntStatus; =20 UINT32 Response[4]; - UINT32 SdmaAddr; + UINT64 SdmaAddr; =20 UINT8 Index; =20 UINT8 SwReset; =20 UINT32 PioLength; + UINT16 ControllerVer; =20 =20 SwReset =3D 0; =20 Packet =3D Trb->Packet; @@ -1870,19 +2034,42 @@ SdMmcCheckTrbResult ( =20 // =20 // Update SDMA Address register. =20 // - SdmaAddr =3D SD_MMC_SDMA_ROUND_UP ((UINT32)(UINTN)Trb->DataPhy, SD_M= MC_SDMA_BOUNDARY); - Status =3D SdMmcHcRwMmio ( + SdmaAddr =3D SD_MMC_SDMA_ROUND_UP ((UINTN)Trb->DataPhy,=20 + SD_MMC_SDMA_BOUNDARY); + + Status =3D SdMmcHcGetControllerVersion ( + Private->PciIo, + Trb->Slot, + &ControllerVer + ); + if (EFI_ERROR (Status)) { + return Status; + } + + if (ControllerVer >=3D SD_MMC_HC_CTRL_VER_400) { + Status =3D SdMmcHcRwMmio ( =20 Private->PciIo, =20 Trb->Slot, - SD_MMC_HC_SDMA_ADDR, + SD_MMC_HC_ADMA_SYS_ADDR, =20 FALSE, - sizeof (UINT32), + sizeof (UINT64), =20 &SdmaAddr =20 ); + } + else { + Status =3D SdMmcHcRwMmio ( + Private->PciIo, + Trb->Slot, + SD_MMC_HC_SDMA_ADDR, + FALSE, + sizeof (UINT32), + &SdmaAddr + ); + } + =20 if (EFI_ERROR (Status)) { =20 goto Done; =20 } - Trb->DataPhy =3D (UINT32)(UINTN)SdmaAddr; + Trb->DataPhy =3D (UINT64)(UINTN)SdmaAddr; =20 } =20 =20 if ((Packet->SdMmcCmdBlk->CommandType !=3D SdMmcCommandTypeAdtc) && = diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h b/MdeModule= Pkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h index cc138fc..a6234f1 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h @@ -2,6 +2,7 @@ =20 =20 Provides some data structure definitions used by the SD/MMC host con= troller driver. =20 +Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. =20Copyright (c) 2015, Intel Corporation. All rights reserved.
This = program and the accompanying materials are licensed and made available u= nder the terms and conditions of the BSD License @@ -78,6 +79,9 @@ typede= f enum { // =20#define ADMA_MAX_DATA_PER_LINE 0x10000 =20 +// +// ADMA descriptor for 32b addressing. +// =20typedef struct { =20 UINT32 Valid:1; =20 UINT32 End:1; @@ -87,7 +91,23 @@ typedef struct { =20 UINT32 Reserved1:10; =20 UINT32 Length:16; =20 UINT32 Address; -} SD_MMC_HC_ADMA_DESC_LINE; +} SD_MMC_HC_ADMA_32_DESC_LINE; + +// +// ADMA descriptor for 64b addressing. +// +typedef struct { + UINT32 Valid:1; + UINT32 End:1; + UINT32 Int:1; + UINT32 Reserved:1; + UINT32 Act:2; + UINT32 Reserved1:10; + UINT32 Length:16; + UINT32 LowerAddress; + UINT32 UpperAddress; + UINT32 Reserved2; +} SD_MMC_HC_ADMA_64_DESC_LINE; =20 =20#define SD_MMC_SDMA_BOUNDARY 512 * 1024 =20#define SD_MMC_SDMA_ROUND_UP(x, n) (((x) + n) & ~(n - 1)) @@ -145,6 +165,12 @@ typedef struct { =20#define SD_MMC_HC_CTRL_VER_410 0x04 =20#define SD_MMC_HC_CTRL_VER_420 0x05 =20 +// +// SD Host controller V4 Support +// +#define SD_MMC_HC_V4_EN BIT12 +#define SD_MMC_HC_64_ADDR_EN BIT13 + =20/** =20 Dump the content of SD/MMC host controller's Capability Register. =20 -- 2.7.4 -------------------------------------------------------------------------= ---------- This email message is for the sole use of the intended recipient(s) and m= ay contain confidential information. Any unauthorized review, use, disclosure or di= stribution is prohibited. If you are not the intended recipient, please contact the= =20sender by reply email and destroy all copies of the original message. -------------------------------------------------------------------------= ----------