From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web12.705.1570584910076712466 for ; Tue, 08 Oct 2019 18:35:10 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.100, mailfrom: prince.agyeman@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Oct 2019 18:35:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,273,1566889200"; d="scan'208";a="223422773" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by fmsmga002.fm.intel.com with ESMTP; 08 Oct 2019 18:35:09 -0700 Received: from fmsmsx114.amr.corp.intel.com (10.18.116.8) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 8 Oct 2019 18:35:08 -0700 Received: from FMSMSX110.amr.corp.intel.com ([169.254.14.36]) by FMSMSX114.amr.corp.intel.com ([169.254.6.30]) with mapi id 14.03.0439.000; Tue, 8 Oct 2019 18:35:08 -0700 From: "Agyeman, Prince" To: "Kubacki, Michael A" , "devel@edk2.groups.io" CC: "Wei, David Y" Subject: Re: [edk2-platforms][PATCH V1 17/17] SimicsOpenBoardPkg: Assign unique token namespace Thread-Topic: [edk2-platforms][PATCH V1 17/17] SimicsOpenBoardPkg: Assign unique token namespace Thread-Index: AQHVfZeuIcXVRtGRaEenhQo8r8sKe6dRiEuA Date: Wed, 9 Oct 2019 01:35:08 +0000 Message-ID: References: <20191008051645.22052-1-michael.a.kubacki@intel.com> <20191008051645.22052-18-michael.a.kubacki@intel.com> In-Reply-To: <20191008051645.22052-18-michael.a.kubacki@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.1.200.108] MIME-Version: 1.0 Return-Path: prince.agyeman@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Prince Agyeman -----Original Message----- From: Kubacki, Michael A=20 Sent: Monday, October 7, 2019 10:17 PM To: devel@edk2.groups.io Cc: Agyeman, Prince ; Wei, David Y Subject: [edk2-platforms][PATCH V1 17/17] SimicsOpenBoardPkg: Assign unique= token namespace REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2249 PCDs declared in the SimicsOpenBoardPkg currently use the GUID gBoardModule= TokenSpaceGuid. The same name is used in other board packages and a package= has been added called BoardModulePkg so this name is now misleading. This change assigns a unique GUID value and a name specific to the package = to provide differentiation from PCDs in other board packages. Cc: Agyeman Prince Cc: Wei David Y Signed-off-by: Michael Kubacki --- Platform/Intel/SimicsOpenBoardPkg/OpenBoardPkg.dec = | 72 ++++++++++---------- Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc = | 14 ++-- Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf = | 12 ++-- Platform/Intel/SimicsOpenBoardPkg/Library/PciHostBridgeLib/PciHostBridgeLi= b.inf | 14 ++-- Platform/Intel/SimicsOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.in= f | 10 +-- Platform/Intel/SimicsOpenBoardPkg/Library/PlatformBootManagerLib/PlatformB= ootManagerLib.inf | 10 +-- Platform/Intel/SimicsOpenBoardPkg/SecCore/SecMain.inf = | 18 ++--- Platform/Intel/SimicsOpenBoardPkg/SimicsPei/SimicsPei.inf = | 36 +++++----- Platform/Intel/SimicsOpenBoardPkg/SimicsVideoDxe/SimicsVideoDxe.inf = | 2 +- Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/DecomprScratchEnd.fdf.inc = | 6 +- Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf.inc = | 16 ++--- 11 files changed, 105 insertions(+), 105 deletions(-) diff --git a/Platform/Intel/SimicsOpenBoardPkg/OpenBoardPkg.dec b/Platform/= Intel/SimicsOpenBoardPkg/OpenBoardPkg.dec index 40487820fa..421c464023 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/OpenBoardPkg.dec +++ b/Platform/Intel/SimicsOpenBoardPkg/OpenBoardPkg.dec @@ -17,57 +17,57 @@ Include =20 [Guids] - gBoardModuleTokenSpaceGuid =3D {0xeed35f57, 0x4ff2, 0x4244, {0xb8, 0x3a= , 0xea, 0x71, 0x5f, 0xd3, 0x59, 0xa5}} + gSimicsOpenBoardPkgTokenSpaceGuid =3D {0x75fd61da, 0x3931, 0x49aa,=20 + {0x8f, 0x11, 0x18, 0x25, 0xf6, 0x31, 0x21, 0xd2}} gSimicsBoardConfigGuid =3D {0xeed35f57, 0x4ff2, 0x4244, {0xb8, 0x3a, 0x= ea, 0x71, 0x5f, 0xd3, 0x59, 0xa5}} =20 [PcdsFixedAtBuild] - gBoardModuleTokenSpaceGuid.PcdSimicsPeiMemFvBase|0x0|UINT32|0 - gBoardModuleTokenSpaceGuid.PcdSimicsPeiMemFvSize|0x0|UINT32|1 - gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvBase|0x0|UINT32|0x15 - gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvSize|0x0|UINT32|0x16 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsPeiMemFvBase|0x0|UINT32|0 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsPeiMemFvSize|0x0|UINT32|1 + =20 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDxeMemFvBase|0x0|UINT32|0x1 + 5 + =20 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDxeMemFvSize|0x0|UINT32|0x1 + 6 =20 #TODO: Remove these two when we integrate new PlatformPei - gBoardModuleTokenSpaceGuid.PcdSimicsMemFvBase|0x00800000|UINT32|2 - gBoardModuleTokenSpaceGuid.PcdSimicsMemFvSize|0x00500000|UINT32|3 + =20 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsMemFvBase|0x00800000|UINT32 + |2 + =20 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsMemFvSize|0x00500000|UINT32 + |3 =20 - gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogBase|0x0|UINT3= 2|0x8 - gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogSize|0x0|UINT3= 2|0x9 - gBoardModuleTokenSpaceGuid.PcdSimicsFirmwareFdSize|0x0|UINT32|0xa - gBoardModuleTokenSpaceGuid.PcdSimicsFirmwareBlockSize|0|UINT32|0xb - gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageVariableBase|0x0|UINT3= 2|0xc - gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageFtwSpareBase|0x0|UINT3= 2|0xd - gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageFtwWorkingBase|0x0|UIN= T32|0xe - gBoardModuleTokenSpaceGuid.PcdSimicsFdBaseAddress|0x0|UINT32|0xf - gBoardModuleTokenSpaceGuid.PcdSimicsSecPageTablesBase|0x0|UINT32|0x11 - gBoardModuleTokenSpaceGuid.PcdSimicsSecPageTablesSize|0x0|UINT32|0x12 - gBoardModuleTokenSpaceGuid.PcdSimicsSecPeiTempRamBase|0x0|UINT32|0x13 - gBoardModuleTokenSpaceGuid.PcdSimicsSecPeiTempRamSize|0x0|UINT32|0x14 - gBoardModuleTokenSpaceGuid.PcdSimicsLockBoxStorageBase|0x0|UINT32|0x18 - gBoardModuleTokenSpaceGuid.PcdSimicsLockBoxStorageSize|0x0|UINT32|0x19 - gBoardModuleTokenSpaceGuid.PcdGuidedExtractHandlerTableSize|0x0|UINT32|0= x1a - gBoardModuleTokenSpaceGuid.PcdSimicsDecompressionScratchEnd|0x0|UINT32|0= x1f + =20 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogBase| + 0x0|UINT32|0x8 + =20 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogSize| + 0x0|UINT32|0x9 =20 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFirmwareFdSize|0x0|UINT32|0 + xa =20 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFirmwareBlockSize|0|UINT32| + 0xb =20 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageVariableBase| + 0x0|UINT32|0xc =20 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageFtwSpareBase| + 0x0|UINT32|0xd =20 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageFtwWorkingBas + e|0x0|UINT32|0xe =20 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFdBaseAddress|0x0|UINT32|0x + f + =20 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsSecPageTablesBase|0x0|UINT3 + 2|0x11 + =20 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsSecPageTablesSize|0x0|UINT3 + 2|0x12 + =20 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsSecPeiTempRamBase|0x0|UINT3 + 2|0x13 + =20 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsSecPeiTempRamSize|0x0|UINT3 + 2|0x14 + =20 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsLockBoxStorageBase|0x0|UINT + 32|0x18 + =20 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsLockBoxStorageSize|0x0|UINT + 32|0x19 =20 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize|0x0 + |UINT32|0x1a =20 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDecompressionScratchEnd|0x0 + |UINT32|0x1f =20 [PcdsDynamic, PcdsDynamicEx] =20 # TODO: investigate whether next two Pcds are needed - gBoardModuleTokenSpaceGuid.PcdEmuVariableEvent|0|UINT64|0x28 - gBoardModuleTokenSpaceGuid.PcdOvmfFlashVariablesEnable|FALSE|BOOLEAN|0x1= 0 - gBoardModuleTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId|0|UINT16|0x1b + gSimicsOpenBoardPkgTokenSpaceGuid.PcdEmuVariableEvent|0|UINT64|0x28 + =20 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdOvmfFlashVariablesEnable|FALSE|BO + OLEAN|0x10 =20 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId|0|UIN + T16|0x1b =20 ## The IO port aperture shared by all PCI root bridges. # - gBoardModuleTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x22 - gBoardModuleTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x23 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x22 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x23 =20 ## The 32-bit MMIO aperture shared by all PCI root bridges. # - gBoardModuleTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT64|0x24 - gBoardModuleTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT64|0x25 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT64|0x24 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT64|0x25 =20 ## The 64-bit MMIO aperture shared by all PCI root bridges. # - gBoardModuleTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x26 - gBoardModuleTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x27 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x26 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x27 =20 [PcdsFixedAtBuild, PcdsDynamic, PcdsDynamicEx, PcdsPatchableInModule] ## Pcd8259LegacyModeMask defines the default mask value for platform. Th= is value is determined

@@ -131,7 +131,7 @@ [PcdsFixedAtBuild, Pcds= PatchableInModule] ## FFS filename to find the shell application. # @Prompt FFS Name of Shell Application - gBoardModuleTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, = 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }|VOID*|0x= 40000004 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04,=20 + 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0,=20 + 0xB4, 0xD1 }|VOID*|0x40000004 =20 ## ISA Bus features to support DMA, SlaveDMA and ISA Memory.

# BIT0 indicates if DMA is supported
@@ -140,10 +140,10 @@ # Other BITs are reseved and must be zero. # If more than one features are supported, the different BIT will be en= abled at the same time. # @Prompt ISA Bus Features - # @Expression 0x80000002 | (gBoardModuleTokenSpaceGuid.PcdIsaBusSupporte= dFeatures & 0xF8) =3D=3D 0 - gBoardModuleTokenSpaceGuid.PcdIsaBusSupportedFeatures|0x05|UINT8|0x00010= 040 + # @Expression 0x80000002 |=20 + (gSimicsOpenBoardPkgTokenSpaceGuid.PcdIsaBusSupportedFeatures & 0xF8)=20 + =3D=3D 0 + =20 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdIsaBusSupportedFeatures|0x05|UINT + 8|0x00010040 =20 - gBoardModuleTokenSpaceGuid.PcdLogoFile |{ 0x99, 0x8b, 0xB2, 0x7B, 0xBB, = 0x61, 0xD5, 0x11, 0x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D }|VOID*|0x= 00010037 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdLogoFile |{ 0x99, 0x8b, 0xB2,=20 + 0x7B, 0xBB, 0x61, 0xD5, 0x11, 0x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F,=20 + 0xC1, 0x4D }|VOID*|0x00010037 =20 [Protocols] ## diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPc= d.dsc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc index 29cd2455f6..0298e4b12d 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.ds +++ c @@ -235,13 +235,13 @@ ###################################### # Board Configuration ###################################### - gBoardModuleTokenSpaceGuid.PcdPciIoBase|0x0 - gBoardModuleTokenSpaceGuid.PcdPciIoSize|0x0 - gBoardModuleTokenSpaceGuid.PcdPciMmio32Base|0x0 - gBoardModuleTokenSpaceGuid.PcdPciMmio32Size|0x0 - gBoardModuleTokenSpaceGuid.PcdPciMmio64Base|0x0 - gBoardModuleTokenSpaceGuid.PcdPciMmio64Size|0x800000000 - gBoardModuleTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId|0 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciIoBase|0x0 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciIoSize|0x0 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio32Base|0x0 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio32Size|0x0 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio64Base|0x0 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio64Size|0x800000000 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId|0 =20 ###################################### # Advanced Feature Configuration diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.f= df b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf index 6c1579bef7..75a99a5270 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf @@ -80,23 +80,23 @@ BlockSize =3D 0x10000 NumBlocks =3D 0xB0 =20 0x000000|0x006000 -gBoardModuleTokenSpaceGuid.PcdSimicsSecPageTablesBase|gBoardModuleTokenSpa= ceGuid.PcdSimicsSecPageTablesSize +gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsSecPageTablesBase|gSimicsOpe +nBoardPkgTokenSpaceGuid.PcdSimicsSecPageTablesSize =20 0x006000|0x001000 -gBoardModuleTokenSpaceGuid.PcdSimicsLockBoxStorageBase|gBoardModuleTokenSp= aceGuid.PcdSimicsLockBoxStorageSize +gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsLockBoxStorageBase|gSimicsOp +enBoardPkgTokenSpaceGuid.PcdSimicsLockBoxStorageSize =20 0x007000|0x001000 -gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|gBoardModuleT= okenSpaceGuid.PcdGuidedExtractHandlerTableSize +gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|gSimicsOpe +nBoardPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize =20 0x010000|0x008000 -gBoardModuleTokenSpaceGuid.PcdSimicsSecPeiTempRamBase|gBoardModuleTokenSpa= ceGuid.PcdSimicsSecPeiTempRamSize +gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsSecPeiTempRamBase|gSimicsOpe +nBoardPkgTokenSpaceGuid.PcdSimicsSecPeiTempRamSize =20 0x020000|0x0E0000 -gBoardModuleTokenSpaceGuid.PcdSimicsPeiMemFvBase|gBoardModuleTokenSpaceGui= d.PcdSimicsPeiMemFvSize +gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsPeiMemFvBase|gSimicsOpenBoar +dPkgTokenSpaceGuid.PcdSimicsPeiMemFvSize FV =3D FvPreMemory =20 0x100000|0xA00000 -gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvBase|gBoardModuleTokenSpaceGui= d.PcdSimicsDxeMemFvSize +gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDxeMemFvBase|gSimicsOpenBoar +dPkgTokenSpaceGuid.PcdSimicsDxeMemFvSize FV =3D DXEFV =20 ##########################################################################= ###### diff --git a/Platform/Intel/SimicsOpenBoardPkg/Library/PciHostBridgeLib/Pci= HostBridgeLib.inf b/Platform/Intel/SimicsOpenBoardPkg/Library/PciHostBridge= Lib/PciHostBridgeLib.inf index e1920bd2ff..372e0c9651 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/Library/PciHostBridgeLib/PciHostBri= dgeLib.inf +++ b/Platform/Intel/SimicsOpenBoardPkg/Library/PciHostBridgeLib/PciHost +++ BridgeLib.inf @@ -41,11 +41,11 @@ PciLib =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdPciIoBase - gBoardModuleTokenSpaceGuid.PcdPciIoSize - gBoardModuleTokenSpaceGuid.PcdPciMmio32Base - gBoardModuleTokenSpaceGuid.PcdPciMmio32Size - gBoardModuleTokenSpaceGuid.PcdPciMmio64Base - gBoardModuleTokenSpaceGuid.PcdPciMmio64Size - gBoardModuleTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciIoBase + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciIoSize + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio32Base + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio32Size + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio64Base + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio64Size + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration diff --git a/Platform/Intel/SimicsOpenBoardPkg/Library/PeiReportFvLib/PeiRe= portFvLib.inf b/Platform/Intel/SimicsOpenBoardPkg/Library/PeiReportFvLib/Pe= iReportFvLib.inf index bc85420f97..5d2e39532c 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvL= ib.inf +++ b/Platform/Intel/SimicsOpenBoardPkg/Library/PeiReportFvLib/PeiReport +++ FvLib.inf @@ -48,9 +48,9 @@ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize ## CONSUMES gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase ## CONSUMES gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdSimicsPeiMemFvBase - gBoardModuleTokenSpaceGuid.PcdSimicsPeiMemFvSize - gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvBase - gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvSize - gBoardModuleTokenSpaceGuid.PcdSimicsDecompressionScratchEnd + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsPeiMemFvBase + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsPeiMemFvSize + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDxeMemFvBase + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDxeMemFvSize + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDecompressionScratchEnd gSimicsX58PkgTokenSpaceGuid.PcdSmmSmramRequire diff --git a/Platform/Intel/SimicsOpenBoardPkg/Library/PlatformBootManagerL= ib/PlatformBootManagerLib.inf b/Platform/Intel/SimicsOpenBoardPkg/Library/P= latformBootManagerLib/PlatformBootManagerLib.inf index cdb6e242e8..3fb76c3564 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/Library/PlatformBootManagerLib/Plat= formBootManagerLib.inf +++ b/Platform/Intel/SimicsOpenBoardPkg/Library/PlatformBootManagerLib/P +++ latformBootManagerLib.inf @@ -50,12 +50,12 @@ LogoLib =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdEmuVariableEvent - gBoardModuleTokenSpaceGuid.PcdOvmfFlashVariablesEnable - gBoardModuleTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId + gSimicsOpenBoardPkgTokenSpaceGuid.PcdEmuVariableEvent + gSimicsOpenBoardPkgTokenSpaceGuid.PcdOvmfFlashVariablesEnable + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut - gBoardModuleTokenSpaceGuid.PcdShellFile - gBoardModuleTokenSpaceGuid.PcdLogoFile + gSimicsOpenBoardPkgTokenSpaceGuid.PcdShellFile + gSimicsOpenBoardPkgTokenSpaceGuid.PcdLogoFile =20 [Pcd.IA32, Pcd.X64] gEfiMdePkgTokenSpaceGuid.PcdFSBClock diff --git a/Platform/Intel/SimicsOpenBoardPkg/SecCore/SecMain.inf b/Platfo= rm/Intel/SimicsOpenBoardPkg/SecCore/SecMain.inf index b1d319c5ea..61ca2c0613 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/SecCore/SecMain.inf +++ b/Platform/Intel/SimicsOpenBoardPkg/SecCore/SecMain.inf @@ -58,16 +58,16 @@ gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdSimicsPeiMemFvBase - gBoardModuleTokenSpaceGuid.PcdSimicsPeiMemFvSize - gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvBase - gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvSize - gBoardModuleTokenSpaceGuid.PcdSimicsSecPageTablesBase - gBoardModuleTokenSpaceGuid.PcdSimicsSecPeiTempRamBase - gBoardModuleTokenSpaceGuid.PcdSimicsSecPeiTempRamSize + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsPeiMemFvBase + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsPeiMemFvSize + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDxeMemFvBase + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDxeMemFvSize + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsSecPageTablesBase + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsSecPeiTempRamBase + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsSecPeiTempRamSize gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress - gBoardModuleTokenSpaceGuid.PcdGuidedExtractHandlerTableSize - gBoardModuleTokenSpaceGuid.PcdSimicsDecompressionScratchEnd + gSimicsOpenBoardPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDecompressionScratchEnd =20 [FeaturePcd] gSimicsX58PkgTokenSpaceGuid.PcdSmmSmramRequire diff --git a/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/SimicsPei.inf b/Pl= atform/Intel/SimicsOpenBoardPkg/SimicsPei/SimicsPei.inf index e466d57e4e..9499d2aad5 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/SimicsPei.inf +++ b/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/SimicsPei.inf @@ -55,25 +55,25 @@ PcdLib =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdSimicsPeiMemFvBase - gBoardModuleTokenSpaceGuid.PcdSimicsPeiMemFvSize - gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvBase - gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvSize - gBoardModuleTokenSpaceGuid.PcdSimicsLockBoxStorageBase - gBoardModuleTokenSpaceGuid.PcdSimicsLockBoxStorageSize - gBoardModuleTokenSpaceGuid.PcdSimicsSecPageTablesBase - gBoardModuleTokenSpaceGuid.PcdSimicsSecPeiTempRamBase - gBoardModuleTokenSpaceGuid.PcdSimicsSecPeiTempRamSize + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsPeiMemFvBase + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsPeiMemFvSize + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDxeMemFvBase + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDxeMemFvSize + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsLockBoxStorageBase + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsLockBoxStorageSize + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsSecPageTablesBase + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsSecPeiTempRamBase + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsSecPeiTempRamSize gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress - gBoardModuleTokenSpaceGuid.PcdGuidedExtractHandlerTableSize - gBoardModuleTokenSpaceGuid.PcdSimicsDecompressionScratchEnd - gBoardModuleTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId - gBoardModuleTokenSpaceGuid.PcdPciIoBase - gBoardModuleTokenSpaceGuid.PcdPciIoSize - gBoardModuleTokenSpaceGuid.PcdPciMmio32Base - gBoardModuleTokenSpaceGuid.PcdPciMmio32Size - gBoardModuleTokenSpaceGuid.PcdPciMmio64Base - gBoardModuleTokenSpaceGuid.PcdPciMmio64Size + gSimicsOpenBoardPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDecompressionScratchEnd + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciIoBase + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciIoSize + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio32Base + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio32Size + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio64Base + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio64Size gSimicsX58PkgTokenSpaceGuid.PcdX58TsegMbytes gSimicsX58PkgTokenSpaceGuid.PcdSmmSmramRequire gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize diff --git a/Platform/Intel/SimicsOpenBoardPkg/SimicsVideoDxe/SimicsVideoDx= e.inf b/Platform/Intel/SimicsOpenBoardPkg/SimicsVideoDxe/SimicsVideoDxe.inf index 002cb56826..e0eee30985 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/SimicsVideoDxe/SimicsVideoDxe.inf +++ b/Platform/Intel/SimicsOpenBoardPkg/SimicsVideoDxe/SimicsVideoDxe.in +++ f @@ -70,5 +70,5 @@ =20 [Pcd] gOptionRomPkgTokenSpaceGuid.PcdDriverSupportedEfiVersion - gBoardModuleTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/DecomprScratch= End.fdf.inc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/DecomprScratc= hEnd.fdf.inc index ae9a625da9..af583ecde6 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/DecomprScratchEnd.fdf= .inc +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/DecomprScratchEnd. +++ fdf.inc @@ -45,7 +45,7 @@ # The total size after decompression is (128 + PcdSimicsPeiMemFvSize + 16 = + # PcdSimicsDxeMemFvSize). =20 -DEFINE OUTPUT_SIZE =3D (128 + gBoardModuleTokenSpaceGuid.PcdSimicsPeiMemFv= Size + 16 + gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvSize) +DEFINE OUTPUT_SIZE =3D (128 +=20 +gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsPeiMemFvSize + 16 +=20 +gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDxeMemFvSize) =20 # LzmaCustomDecompressLib uses a constant scratch buffer size of 64KB; see= # SCRATCH_BUFFER_REQUEST_SIZE in @@ -58,10 +58,10 @@ DEFINE DECOMP_SCRATC= H_SIZE =3D 0x00010000 # # The calculation below mirrors DecompressMemFvs(= ) [SimicsX58Pkg/Sec/SecMain.c]. =20 -DEFINE OUTPUT_BASE =3D ($(MEMFD_BASE_ADDRESS) + gBoardMo= duleTokenSpaceGuid.PcdSimicsDxeMemFvBase + 0x00100000) +DEFINE OUTPUT_BASE =3D ($(MEMFD_BASE_ADDRESS) + gSimicsO= penBoardPkgTokenSpaceGuid.PcdSimicsDxeMemFvBase + 0x00100000) DEFINE DECOMP_SCRATCH_BASE_UNALIGNED =3D ($(OUTPUT_BASE) + $(OUTPUT_SIZE))= DEFINE DECOMP_SCRATCH_BASE_ALIGNMENT =3D 0x000FFFFF DEFINE DECOMP_SCRATCH_BASE_MASK =3D 0xFFF00000 DEFINE DECOMP_SCRATCH_BASE =3D (($(DECOMP_SCRATCH_BASE_UNALIGNED= ) + $(DECOMP_SCRATCH_BASE_ALIGNMENT)) & $(DECOMP_SCRATCH_BASE_MASK)) =20 -SET gBoardModuleTokenSpaceGuid.PcdSimicsDecompressionScratchEnd =3D $(DECO= MP_SCRATCH_BASE) + $(DECOMP_SCRATCH_SIZE) +SET gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDecompressionScratchEnd=20 +=3D $(DECOMP_SCRATCH_BASE) + $(DECOMP_SCRATCH_SIZE) diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.f= df.inc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf.i= nc index 044129c941..9c2436c3ad 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf.inc +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf.i +++ nc @@ -29,20 +29,20 @@ DEFINE SECFV_OFFSET =3D 0x001EC000 DEFINE SECFV_SIZE =3D 0x14000 =20 =20 -SET gBoardModuleTokenSpaceGuid.PcdSimicsFdBaseAddress =3D $(FW_BASE_AD= DRESS) -SET gBoardModuleTokenSpaceGuid.PcdSimicsFirmwareFdSize =3D $(FW_SIZE) -SET gBoardModuleTokenSpaceGuid.PcdSimicsFirmwareBlockSize =3D $(BLOCK_SIZE= ) +SET gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFdBaseAddress =3D $(FW_= BASE_ADDRESS) +SET gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFirmwareFdSize =3D $(FW_= SIZE) +SET gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFirmwareBlockSize =3D=20 +$(BLOCK_SIZE) =20 -SET gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageVariableBase =3D $(F= W_BASE_ADDRESS) +SET=20 +gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageVariableBase =3D= =20 +$(FW_BASE_ADDRESS) SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize =3D 0xE00= 0 =20 -SET gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogBase =3D gBo= ardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageVariableBase + gEfiMdeModule= PkgTokenSpaceGuid.PcdFlashNvStorageVariableSize -SET gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogSize =3D $(B= LOCK_SIZE) +SET=20 +gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogBase =3D= =20 +gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageVariableBase +=20 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +SET=20 +gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogSize =3D= =20 +$(BLOCK_SIZE) =20 -SET gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageFtwWorkingBase =3D g= BoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogBase + gBoardModul= eTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogSize +SET=20 +gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageFtwWorkingBase=20 +=3D gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogBase= =20 ++ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogSize SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize =3D $(B= LOCK_SIZE) =20 -SET gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageFtwSpareBase =3D gBo= ardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageFtwWorkingBase + gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +SET=20 +gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageFtwSpareBase =3D= =20 +gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageFtwWorkingBase=20 ++ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize =3D 0x100= 00 =20 SET gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress =3D 0xFFE00000 -- 2.16.2.windows.1