* [edk2-platforms: PATCH v3 0/6] Add SetCacheMtrrLib library class.
@ 2019-10-31 10:28 Chiu, Chasel
2019-10-31 10:28 ` [edk2-platforms: PATCH v3 1/6] MinPlatformPkg: " Chiu, Chasel
` (5 more replies)
0 siblings, 6 replies; 16+ messages in thread
From: Chiu, Chasel @ 2019-10-31 10:28 UTC (permalink / raw)
To: devel
Cc: Michael Kubacki, Nate DeSimone, Liming Gao, Jeremy Soller,
Shifei A Lu, Xiaohu Zhou, Isaac W Oram, Wei David Y,
Agyeman Prince
V3 updates:
. Rename SetCacheLib to SetCacheMtrrLib
. SetCacheMtrrLib.inf base name and type changed to PeiSetCacheMtrrLib and PEIM
. SetCacheMtrrLibNull.inf base name changed to BaseSetCacheMtrrlibNull
. Add SetCacheMtrrLib.h to MinPlatformPkg.dec
. Add usage description to SetCacheMtrrLib.c and SetCacheMtrrLib.inf
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2314
The MTRRs may be redundantly or incorrectly configured.
It is recommended to move this functionality to a library
class that with a NULL library by default. The board
package may provide its own library implementation.
MinPlatformPkg should contain the library class header (API)
and the NULL library class instance.
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Jeremy Soller <jeremy@system76.com>
Cc: Shifei A Lu <shifei.a.lu@intel.com>
Cc: Xiaohu Zhou <bowen.zhou@intel.com>
Cc: Isaac W Oram <isaac.w.oram@intel.com>
Cc: Wei David Y <david.y.wei@intel.com>
Cc: Agyeman Prince <prince.agyeman@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Chasel Chiu (6):
MinPlatformPkg: Add SetCacheMtrrLib library class.
MinPlatformPkg: Add SetCacheMtrrLib library class.
KabylakeOpenBoardPkg: Add SetCacheMtrrLib library class.
WhiskeylakeOpenBoardPkg: Add SetCacheMtrrLib library class.
PurleyOpenBoardPkg/BoardMtOlympus: Add SetCacheMtrrLib library class.
SimicsOpenBoardPkg/BoardX58Ich10: Add SetCacheMtrrLib library class.
Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c | 640 ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c | 327 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLibNull.c | 37 +++++++++++++++++++++++++++++++++++++
Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.c | 151 ++-----------------------------------------------------------------------------------------------------------------------------------------------------
Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c | 164 ++------------------------------------------------------------------------------------------------------------------------------------------------------------------
Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc | 3 ++-
Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf | 2 +-
Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf | 67 -------------------------------------------------------------------
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc | 1 +
Platform/Intel/MinPlatformPkg/Include/Library/SetCacheMtrrLib.h | 34 ++++++++++++++++++++++++++++++++++
Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf | 46 ++++++++++++++++++++++++++++++++++++++++++++++
Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLibNull.inf | 29 +++++++++++++++++++++++++++++
Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec | 6 ++++--
Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf | 11 +----------
Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf | 7 ++-----
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkg.dsc | 3 ++-
Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc | 1 +
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc | 1 +
18 files changed, 492 insertions(+), 1038 deletions(-)
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c
create mode 100644 Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c
create mode 100644 Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLibNull.c
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
create mode 100644 Platform/Intel/MinPlatformPkg/Include/Library/SetCacheMtrrLib.h
create mode 100644 Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
create mode 100644 Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLibNull.inf
--
2.13.3.windows.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [edk2-platforms: PATCH v3 1/6] MinPlatformPkg: Add SetCacheMtrrLib library class.
2019-10-31 10:28 [edk2-platforms: PATCH v3 0/6] Add SetCacheMtrrLib library class Chiu, Chasel
@ 2019-10-31 10:28 ` Chiu, Chasel
2019-10-31 17:02 ` [edk2-devel] " Kubacki, Michael A
2019-11-01 18:29 ` Nate DeSimone
2019-10-31 10:28 ` [edk2-platforms: PATCH v3 2/6] " Chiu, Chasel
` (4 subsequent siblings)
5 siblings, 2 replies; 16+ messages in thread
From: Chiu, Chasel @ 2019-10-31 10:28 UTC (permalink / raw)
To: devel; +Cc: Michael Kubacki, Nate DeSimone, Liming Gao
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2314
MinPlatformPkg should contain the library class header (API)
and the NULL library class instance.
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c | 327 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLibNull.c | 37 +++++++++++++++++++++++++++++++++++++
Platform/Intel/MinPlatformPkg/Include/Library/SetCacheMtrrLib.h | 34 ++++++++++++++++++++++++++++++++++
Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf | 46 ++++++++++++++++++++++++++++++++++++++++++++++
Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLibNull.inf | 29 +++++++++++++++++++++++++++++
Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec | 6 ++++--
6 files changed, 477 insertions(+), 2 deletions(-)
diff --git a/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c
new file mode 100644
index 0000000000..26f06321f7
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c
@@ -0,0 +1,327 @@
+/** @file
+
+SetCacheMtrr library functions.
+This implementation is for typical platforms and may not be
+needed when cache MTRR will be initialized by FSP.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <PiPei.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MtrrLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Guid/SmramMemoryReserve.h>
+
+/**
+ Set Cache Mtrr.
+**/
+VOID
+EFIAPI
+SetCacheMtrr (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_HOB_POINTERS Hob;
+ MTRR_SETTINGS MtrrSetting;
+ UINT64 MemoryBase;
+ UINT64 MemoryLength;
+ UINT64 LowMemoryLength;
+ UINT64 HighMemoryLength;
+ EFI_BOOT_MODE BootMode;
+ EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;
+ UINT64 CacheMemoryLength;
+
+ ///
+ /// Reset all MTRR setting.
+ ///
+ ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS));
+
+ ///
+ /// Cache the Flash area as WP to boost performance
+ ///
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ &MtrrSetting,
+ (UINTN) PcdGet32 (PcdFlashAreaBaseAddress),
+ (UINTN) PcdGet32 (PcdFlashAreaSize),
+ CacheWriteProtected
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ ///
+ /// Update MTRR setting from MTRR buffer for Flash Region to be WP to boost performance
+ ///
+ MtrrSetAllMtrrs (&MtrrSetting);
+
+ ///
+ /// Set low to 1 MB. Since 1MB cacheability will always be set
+ /// until override by CSM.
+ /// Initialize high memory to 0.
+ ///
+ LowMemoryLength = 0x100000;
+ HighMemoryLength = 0;
+ ResourceAttribute = (
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
+ );
+
+ Status = PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+
+ if (BootMode != BOOT_ON_S3_RESUME) {
+ ResourceAttribute |= EFI_RESOURCE_ATTRIBUTE_TESTED;
+ }
+
+ Status = PeiServicesGetHobList ((VOID **) &Hob.Raw);
+ while (!END_OF_HOB_LIST (Hob)) {
+ if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {
+ if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) ||
+ ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) &&
+ (Hob.ResourceDescriptor->ResourceAttribute == ResourceAttribute))
+ ) {
+ if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000000ULL) {
+ HighMemoryLength += Hob.ResourceDescriptor->ResourceLength;
+ } else if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000) {
+ LowMemoryLength += Hob.ResourceDescriptor->ResourceLength;
+ }
+ }
+ }
+
+ Hob.Raw = GET_NEXT_HOB (Hob);
+ }
+
+ DEBUG ((DEBUG_INFO, "Memory Length (Below 4GB) = %lx.\n", LowMemoryLength));
+ DEBUG ((DEBUG_INFO, "Memory Length (Above 4GB) = %lx.\n", HighMemoryLength));
+
+ ///
+ /// Assume size of main memory is multiple of 256MB
+ ///
+ MemoryLength = (LowMemoryLength + 0xFFFFFFF) & 0xF0000000;
+ MemoryBase = 0;
+
+ CacheMemoryLength = MemoryLength;
+ ///
+ /// Programming MTRRs to avoid override SPI region with UC when MAX TOLUD Length >= 3.5GB
+ ///
+ if (MemoryLength > 0xDC000000) {
+ CacheMemoryLength = 0xC0000000;
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ &MtrrSetting,
+ MemoryBase,
+ CacheMemoryLength,
+ CacheWriteBack
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ MemoryBase = 0xC0000000;
+ CacheMemoryLength = MemoryLength - 0xC0000000;
+ if (MemoryLength > 0xE0000000) {
+ CacheMemoryLength = 0x20000000;
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ &MtrrSetting,
+ MemoryBase,
+ CacheMemoryLength,
+ CacheWriteBack
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ MemoryBase = 0xE0000000;
+ CacheMemoryLength = MemoryLength - 0xE0000000;
+ }
+ }
+
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ &MtrrSetting,
+ MemoryBase,
+ CacheMemoryLength,
+ CacheWriteBack
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ if (LowMemoryLength != MemoryLength) {
+ MemoryBase = LowMemoryLength;
+ MemoryLength -= LowMemoryLength;
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ &MtrrSetting,
+ MemoryBase,
+ MemoryLength,
+ CacheUncacheable
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
+
+ ///
+ /// VGA-MMIO - 0xA0000 to 0xC0000 to be UC
+ ///
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ &MtrrSetting,
+ 0xA0000,
+ 0x20000,
+ CacheUncacheable
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ ///
+ /// Update MTRR setting from MTRR buffer
+ ///
+ MtrrSetAllMtrrs (&MtrrSetting);
+
+ return ;
+}
+
+/**
+ Update MTRR setting and set write back as default memory attribute.
+
+ @retval EFI_SUCCESS The function completes successfully.
+ @retval Others Some error occurs.
+**/
+EFI_STATUS
+EFIAPI
+SetCacheMtrrAfterEndOfPei (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ MTRR_SETTINGS MtrrSetting;
+ EFI_PEI_HOB_POINTERS Hob;
+ UINT64 MemoryBase;
+ UINT64 MemoryLength;
+ UINT64 Power2Length;
+ EFI_BOOT_MODE BootMode;
+ UINTN Index;
+ UINT64 SmramSize;
+ UINT64 SmramBase;
+ EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock;
+ Status = PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+
+ if (BootMode == BOOT_ON_S3_RESUME) {
+ return EFI_SUCCESS;
+ }
+ //
+ // Clear the CAR Settings
+ //
+ ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS));
+
+ //
+ // Default Cachable attribute will be set to WB to support large memory size/hot plug memory
+ //
+ MtrrSetting.MtrrDefType &= ~((UINT64)(0xFF));
+ MtrrSetting.MtrrDefType |= (UINT64) CacheWriteBack;
+
+ //
+ // Set fixed cache for memory range below 1MB
+ //
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ &MtrrSetting,
+ 0x0,
+ 0xA0000,
+ CacheWriteBack
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ &MtrrSetting,
+ 0xA0000,
+ 0x20000,
+ CacheUncacheable
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ &MtrrSetting,
+ 0xC0000,
+ 0x40000,
+ CacheWriteProtected
+ );
+ ASSERT_EFI_ERROR ( Status);
+
+ //
+ // PI SMM IPL can't set SMRAM to WB because at that time CPU ARCH protocol is not available.
+ // Set cacheability of SMRAM to WB here to improve SMRAM initialization performance.
+ //
+ SmramSize = 0;
+ SmramBase = 0;
+ Status = PeiServicesGetHobList ((VOID **) &Hob.Raw);
+ while (!END_OF_HOB_LIST (Hob)) {
+ if (Hob.Header->HobType == EFI_HOB_TYPE_GUID_EXTENSION) {
+ if (CompareGuid (&Hob.Guid->Name, &gEfiSmmSmramMemoryGuid)) {
+ SmramHobDescriptorBlock = (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *) (Hob.Guid + 1);
+ for (Index = 0; Index < SmramHobDescriptorBlock->NumberOfSmmReservedRegions; Index++) {
+ if (SmramHobDescriptorBlock->Descriptor[Index].PhysicalStart > 0x100000) {
+ SmramSize += SmramHobDescriptorBlock->Descriptor[Index].PhysicalSize;
+ if (SmramBase == 0 || SmramBase > SmramHobDescriptorBlock->Descriptor[Index].CpuStart) {
+ SmramBase = SmramHobDescriptorBlock->Descriptor[Index].CpuStart;
+ }
+ }
+ }
+ break;
+ }
+ }
+ Hob.Raw = GET_NEXT_HOB (Hob);
+ }
+
+ //
+ // Set non system memory as UC
+ //
+ MemoryBase = 0x100000000;
+
+ //
+ // Add IED size to set whole SMRAM as WB to save MTRR count
+ //
+ MemoryLength = MemoryBase - (SmramBase + SmramSize);
+ while (MemoryLength != 0) {
+ Power2Length = GetPowerOfTwo64 (MemoryLength);
+ MemoryBase -= Power2Length;
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ &MtrrSetting,
+ MemoryBase,
+ Power2Length,
+ CacheUncacheable
+ );
+ ASSERT_EFI_ERROR (Status);
+ MemoryLength -= Power2Length;
+ }
+
+ DEBUG ((DEBUG_INFO, "PcdPciReservedMemAbove4GBLimit - 0x%lx\n", PcdGet64 (PcdPciReservedMemAbove4GBLimit)));
+ DEBUG ((DEBUG_INFO, "PcdPciReservedMemAbove4GBBase - 0x%lx\n", PcdGet64 (PcdPciReservedMemAbove4GBBase)));
+ if (PcdGet64 (PcdPciReservedMemAbove4GBLimit) > PcdGet64 (PcdPciReservedMemAbove4GBBase)) {
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ &MtrrSetting,
+ PcdGet64 (PcdPciReservedMemAbove4GBBase),
+ PcdGet64 (PcdPciReservedMemAbove4GBLimit) - PcdGet64 (PcdPciReservedMemAbove4GBBase) + 1,
+ CacheUncacheable
+ );
+ ASSERT_EFI_ERROR ( Status);
+ }
+
+ DEBUG ((DEBUG_INFO, "PcdPciReservedPMemAbove4GBLimit - 0x%lx\n", PcdGet64 (PcdPciReservedPMemAbove4GBLimit)));
+ DEBUG ((DEBUG_INFO, "PcdPciReservedPMemAbove4GBBase - 0x%lx\n", PcdGet64 (PcdPciReservedPMemAbove4GBBase)));
+ if (PcdGet64 (PcdPciReservedPMemAbove4GBLimit) > PcdGet64 (PcdPciReservedPMemAbove4GBBase)) {
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ &MtrrSetting,
+ PcdGet64 (PcdPciReservedPMemAbove4GBBase),
+ PcdGet64 (PcdPciReservedPMemAbove4GBLimit) - PcdGet64 (PcdPciReservedPMemAbove4GBBase) + 1,
+ CacheUncacheable
+ );
+ ASSERT_EFI_ERROR ( Status);
+ }
+
+ //
+ // Update MTRR setting from MTRR buffer
+ //
+ MtrrSetAllMtrrs (&MtrrSetting);
+
+ return Status;
+}
diff --git a/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLibNull.c b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLibNull.c
new file mode 100644
index 0000000000..4f40de35f4
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLibNull.c
@@ -0,0 +1,37 @@
+/** @file
+
+NULL instances of SetCacheMtrr library functions.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include <Uefi.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+/**
+ Set Cache Mtrr.
+**/
+VOID
+EFIAPI
+SetCacheMtrr (
+ VOID
+ )
+{
+ return;
+}
+
+/**
+ Update MTRR setting and set write back as default memory attribute.
+
+ @retval EFI_SUCCESS The function completes successfully.
+**/
+EFI_STATUS
+EFIAPI
+SetCacheMtrrAfterEndOfPei (
+ VOID
+ )
+{
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/MinPlatformPkg/Include/Library/SetCacheMtrrLib.h b/Platform/Intel/MinPlatformPkg/Include/Library/SetCacheMtrrLib.h
new file mode 100644
index 0000000000..0fb566dfcc
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/Include/Library/SetCacheMtrrLib.h
@@ -0,0 +1,34 @@
+/** @file
+
+Header for SetCacheMtrr library functions.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _SET_CACHE_MTRR_LIB_H_
+#define _SET_CACHE_MTRR_LIB_H_
+
+/**
+ Set Cache Mtrr.
+**/
+VOID
+EFIAPI
+SetCacheMtrr (
+ VOID
+ );
+
+/**
+ Update MTRR setting and set write back as default memory attribute.
+
+ @retval EFI_SUCCESS The function completes successfully.
+ @retval Others Some error occurs.
+**/
+EFI_STATUS
+EFIAPI
+SetCacheMtrrAfterEndOfPei (
+ VOID
+ );
+
+#endif
diff --git a/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
new file mode 100644
index 0000000000..0cfdda414b
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
@@ -0,0 +1,46 @@
+## @file
+# Component information file for Platform SetCacheMtrr Library.
+# This library implementation is for typical platforms and may not be
+# needed when cache MTRR will be initialized by FSP.
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiSetCacheMtrrLib
+ FILE_GUID = 9F2A2899-3AD7-4176-9B89-33B3AC456A99
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SetCacheMtrrLib
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ DebugLib
+ HobLib
+ MtrrLib
+ PeiServicesLib
+ BaseMemoryLib
+
+[Packages]
+ MinPlatformPkg/MinPlatformPkg.dec
+ MdePkg/MdePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+[Sources]
+ SetCacheMtrrLib.c
+
+[Guids]
+ gEfiSmmSmramMemoryGuid ## CONSUMES
+
+[Pcd]
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBLimit ## CONSUMES
diff --git a/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLibNull.inf b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLibNull.inf
new file mode 100644
index 0000000000..433bd47331
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLibNull.inf
@@ -0,0 +1,29 @@
+## @file
+# Component information file for Platform SetCacheMtrr Library.
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BaseSetCacheMtrrLibNull
+ FILE_GUID = D1ED4CD7-AD20-4943-9192-3ABE766A9411
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SetCacheMtrrLib
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ DebugLib
+
+[Packages]
+ MinPlatformPkg/MinPlatformPkg.dec
+ MdePkg/MdePkg.dec
+
+[Sources]
+ SetCacheMtrrLibNull.c
+
diff --git a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
index d79f5ec1bd..a851021c0b 100644
--- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
+++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
@@ -65,6 +65,8 @@ SecBoardInitLib|Include/Library/SecBoardInitLib.h
TestPointLib|Include/Library/TestPointLib.h
TestPointCheckLib|Include/Library/TestPointCheckLib.h
+SetCacheMtrrLib|Include/Library/SetCacheMtrrLib.h
+
[PcdsFixedAtBuild, PcdsPatchableInModule]
gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|FALSE|BOOLEAN|0x80000008
@@ -204,11 +206,11 @@ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0|UINT32|0x90000019
gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemBase |0x90000000 |UINT32|0x40010043
gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemLimit |0x00000000 |UINT32|0x40010044
gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase |0xFFFFFFFFFFFFFFFF |UINT64|0x40010045
- gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit |0x0000000000000000 |UINT64|0x40010046
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit |0x0000000000000000 |UINT64|0x40010046
gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemBase |0xFFFFFFFF |UINT32|0x40010047
gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemLimit |0x00000000 |UINT32|0x40010048
gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBBase |0xFFFFFFFFFFFFFFFF |UINT64|0x40010049
- gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBLimit|0x0000000000000000 |UINT64|0x4001004A
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBLimit|0x0000000000000000 |UINT64|0x4001004A
gMinPlatformPkgTokenSpaceGuid.PcdPciDmaAbove4G |FALSE|BOOLEAN|0x4001004B
gMinPlatformPkgTokenSpaceGuid.PcdPciNoExtendedConfigSpace |FALSE|BOOLEAN|0x4001004C
gMinPlatformPkgTokenSpaceGuid.PcdPciResourceAssigned |FALSE|BOOLEAN|0x4001004D
--
2.13.3.windows.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [edk2-platforms: PATCH v3 2/6] MinPlatformPkg: Add SetCacheMtrrLib library class.
2019-10-31 10:28 [edk2-platforms: PATCH v3 0/6] Add SetCacheMtrrLib library class Chiu, Chasel
2019-10-31 10:28 ` [edk2-platforms: PATCH v3 1/6] MinPlatformPkg: " Chiu, Chasel
@ 2019-10-31 10:28 ` Chiu, Chasel
2019-11-01 18:29 ` [edk2-devel] " Nate DeSimone
2019-10-31 10:28 ` [edk2-platforms: PATCH v3 3/6] KabylakeOpenBoardPkg: " Chiu, Chasel
` (3 subsequent siblings)
5 siblings, 1 reply; 16+ messages in thread
From: Chiu, Chasel @ 2019-10-31 10:28 UTC (permalink / raw)
To: devel; +Cc: Michael Kubacki, Nate DeSimone, Liming Gao
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2314
MinPlatformPkg PlatformInit modules to consume
SetCacheMtrrLib.
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.c | 151 ++-----------------------------------------------------------------------------------------------------------------------------------------------------
Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c | 164 ++------------------------------------------------------------------------------------------------------------------------------------------------------------------
Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf | 11 +----------
Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf | 7 ++-----
4 files changed, 7 insertions(+), 326 deletions(-)
diff --git a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.c b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.c
index 70e6b9a495..1b00d1dd6a 100644
--- a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.c
+++ b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.c
@@ -13,8 +13,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/PeiServicesLib.h>
#include <IndustryStandard/Pci30.h>
#include <Ppi/EndOfPeiPhase.h>
-#include <Library/MtrrLib.h>
-#include <Guid/SmramMemoryReserve.h>
#include <Guid/FirmwareFileSystem2.h>
#include <Protocol/FirmwareVolumeBlock.h>
@@ -22,6 +20,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/TimerLib.h>
#include <Library/BoardInitLib.h>
#include <Library/TestPointCheckLib.h>
+#include <Library/SetCacheMtrrLib.h>
EFI_STATUS
EFIAPI
@@ -38,152 +37,6 @@ static EFI_PEI_NOTIFY_DESCRIPTOR mEndOfPeiNotifyList = {
};
/**
- Update MTRR setting and set write back as default memory attribute.
-
- @retval EFI_SUCCESS The function completes successfully.
- @retval Others Some error occurs.
-**/
-EFI_STATUS
-EFIAPI
-SetCacheMtrrAfterEndOfPei (
- VOID
- )
-{
- EFI_STATUS Status;
- MTRR_SETTINGS MtrrSetting;
- EFI_PEI_HOB_POINTERS Hob;
- UINT64 MemoryBase;
- UINT64 MemoryLength;
- UINT64 Power2Length;
- EFI_BOOT_MODE BootMode;
- UINTN Index;
- UINT64 SmramSize;
- UINT64 SmramBase;
- EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock;
- Status = PeiServicesGetBootMode (&BootMode);
- ASSERT_EFI_ERROR (Status);
-
- if (BootMode == BOOT_ON_S3_RESUME) {
- return EFI_SUCCESS;
- }
- //
- // Clear the CAR Settings
- //
- ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS));
-
- //
- // Default Cachable attribute will be set to WB to support large memory size/hot plug memory
- //
- MtrrSetting.MtrrDefType &= ~((UINT64)(0xFF));
- MtrrSetting.MtrrDefType |= (UINT64) CacheWriteBack;
-
- //
- // Set fixed cache for memory range below 1MB
- //
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- 0x0,
- 0xA0000,
- CacheWriteBack
- );
- ASSERT_EFI_ERROR (Status);
-
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- 0xA0000,
- 0x20000,
- CacheUncacheable
- );
- ASSERT_EFI_ERROR (Status);
-
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- 0xC0000,
- 0x40000,
- CacheWriteProtected
- );
- ASSERT_EFI_ERROR ( Status);
-
- //
- // PI SMM IPL can't set SMRAM to WB because at that time CPU ARCH protocol is not available.
- // Set cacheability of SMRAM to WB here to improve SMRAM initialization performance.
- //
- SmramSize = 0;
- SmramBase = 0;
- Status = PeiServicesGetHobList ((VOID **) &Hob.Raw);
- while (!END_OF_HOB_LIST (Hob)) {
- if (Hob.Header->HobType == EFI_HOB_TYPE_GUID_EXTENSION) {
- if (CompareGuid (&Hob.Guid->Name, &gEfiSmmSmramMemoryGuid)) {
- SmramHobDescriptorBlock = (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *) (Hob.Guid + 1);
- for (Index = 0; Index < SmramHobDescriptorBlock->NumberOfSmmReservedRegions; Index++) {
- if (SmramHobDescriptorBlock->Descriptor[Index].PhysicalStart > 0x100000) {
- SmramSize += SmramHobDescriptorBlock->Descriptor[Index].PhysicalSize;
- if (SmramBase == 0 || SmramBase > SmramHobDescriptorBlock->Descriptor[Index].CpuStart) {
- SmramBase = SmramHobDescriptorBlock->Descriptor[Index].CpuStart;
- }
- }
- }
- break;
- }
- }
- Hob.Raw = GET_NEXT_HOB (Hob);
- }
-
- //
- // Set non system memory as UC
- //
- MemoryBase = 0x100000000;
-
- //
- // Add IED size to set whole SMRAM as WB to save MTRR count
- //
- MemoryLength = MemoryBase - (SmramBase + SmramSize);
- while (MemoryLength != 0) {
- Power2Length = GetPowerOfTwo64 (MemoryLength);
- MemoryBase -= Power2Length;
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- MemoryBase,
- Power2Length,
- CacheUncacheable
- );
- ASSERT_EFI_ERROR (Status);
- MemoryLength -= Power2Length;
- }
-
- DEBUG ((DEBUG_INFO, "PcdPciReservedMemAbove4GBLimit - 0x%lx\n", PcdGet64 (PcdPciReservedMemAbove4GBLimit)));
- DEBUG ((DEBUG_INFO, "PcdPciReservedMemAbove4GBBase - 0x%lx\n", PcdGet64 (PcdPciReservedMemAbove4GBBase)));
- if (PcdGet64 (PcdPciReservedMemAbove4GBLimit) > PcdGet64 (PcdPciReservedMemAbove4GBBase)) {
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- PcdGet64 (PcdPciReservedMemAbove4GBBase),
- PcdGet64 (PcdPciReservedMemAbove4GBLimit) - PcdGet64 (PcdPciReservedMemAbove4GBBase) + 1,
- CacheUncacheable
- );
- ASSERT_EFI_ERROR ( Status);
- }
-
- DEBUG ((DEBUG_INFO, "PcdPciReservedPMemAbove4GBLimit - 0x%lx\n", PcdGet64 (PcdPciReservedPMemAbove4GBLimit)));
- DEBUG ((DEBUG_INFO, "PcdPciReservedPMemAbove4GBBase - 0x%lx\n", PcdGet64 (PcdPciReservedPMemAbove4GBBase)));
- if (PcdGet64 (PcdPciReservedPMemAbove4GBLimit) > PcdGet64 (PcdPciReservedPMemAbove4GBBase)) {
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- PcdGet64 (PcdPciReservedPMemAbove4GBBase),
- PcdGet64 (PcdPciReservedPMemAbove4GBLimit) - PcdGet64 (PcdPciReservedPMemAbove4GBBase) + 1,
- CacheUncacheable
- );
- ASSERT_EFI_ERROR ( Status);
- }
-
- //
- // Update MTRR setting from MTRR buffer
- //
- MtrrSetAllMtrrs (&MtrrSetting);
-
- return Status;
-}
-
-/**
This function handles PlatformInit task at the end of PEI
@param[in] PeiServices Pointer to PEI Services Table.
@@ -203,7 +56,7 @@ PlatformInitEndOfPei (
)
{
EFI_STATUS Status;
-
+
Status = BoardInitAfterSiliconInit ();
ASSERT_EFI_ERROR (Status);
diff --git a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c
index 2690511abe..c579ff008e 100644
--- a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c
+++ b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c
@@ -1,7 +1,7 @@
/** @file
Source code file for Platform Init Pre-Memory PEI module
-Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -15,7 +15,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/TimerLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/PeiServicesLib.h>
-#include <Library/MtrrLib.h>
#include <Library/ReportFvLib.h>
#include <Ppi/ReadOnlyVariable2.h>
#include <Ppi/MemoryDiscovered.h>
@@ -26,6 +25,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/PeiServicesTablePointerLib.h>
#include <Library/BoardInitLib.h>
#include <Library/TestPointCheckLib.h>
+#include <Library/SetCacheMtrrLib.h>
#include <Guid/MemoryTypeInformation.h>
#include <Ppi/PlatformMemorySize.h>
#include <Ppi/BaseMemoryTest.h>
@@ -319,166 +319,6 @@ Done:
return EFI_SUCCESS;
}
-/**
- Set Cache Mtrr.
-**/
-VOID
-SetCacheMtrr (
- VOID
- )
-{
- EFI_STATUS Status;
- EFI_PEI_HOB_POINTERS Hob;
- MTRR_SETTINGS MtrrSetting;
- UINT64 MemoryBase;
- UINT64 MemoryLength;
- UINT64 LowMemoryLength;
- UINT64 HighMemoryLength;
- EFI_BOOT_MODE BootMode;
- EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;
- UINT64 CacheMemoryLength;
-
- ///
- /// Reset all MTRR setting.
- ///
- ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS));
-
- ///
- /// Cache the Flash area as WP to boost performance
- ///
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- (UINTN) PcdGet32 (PcdFlashAreaBaseAddress),
- (UINTN) PcdGet32 (PcdFlashAreaSize),
- CacheWriteProtected
- );
- ASSERT_EFI_ERROR (Status);
-
- ///
- /// Update MTRR setting from MTRR buffer for Flash Region to be WP to boost performance
- ///
- MtrrSetAllMtrrs (&MtrrSetting);
-
- ///
- /// Set low to 1 MB. Since 1MB cacheability will always be set
- /// until override by CSM.
- /// Initialize high memory to 0.
- ///
- LowMemoryLength = 0x100000;
- HighMemoryLength = 0;
- ResourceAttribute = (
- EFI_RESOURCE_ATTRIBUTE_PRESENT |
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
- );
-
- Status = PeiServicesGetBootMode (&BootMode);
- ASSERT_EFI_ERROR (Status);
-
- if (BootMode != BOOT_ON_S3_RESUME) {
- ResourceAttribute |= EFI_RESOURCE_ATTRIBUTE_TESTED;
- }
-
- Status = PeiServicesGetHobList ((VOID **) &Hob.Raw);
- while (!END_OF_HOB_LIST (Hob)) {
- if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {
- if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) ||
- ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) &&
- (Hob.ResourceDescriptor->ResourceAttribute == ResourceAttribute))
- ) {
- if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000000ULL) {
- HighMemoryLength += Hob.ResourceDescriptor->ResourceLength;
- } else if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000) {
- LowMemoryLength += Hob.ResourceDescriptor->ResourceLength;
- }
- }
- }
-
- Hob.Raw = GET_NEXT_HOB (Hob);
- }
-
- DEBUG ((DEBUG_INFO, "Memory Length (Below 4GB) = %lx.\n", LowMemoryLength));
- DEBUG ((DEBUG_INFO, "Memory Length (Above 4GB) = %lx.\n", HighMemoryLength));
-
- ///
- /// Assume size of main memory is multiple of 256MB
- ///
- MemoryLength = (LowMemoryLength + 0xFFFFFFF) & 0xF0000000;
- MemoryBase = 0;
-
- CacheMemoryLength = MemoryLength;
- ///
- /// Programming MTRRs to avoid override SPI region with UC when MAX TOLUD Length >= 3.5GB
- ///
- if (MemoryLength > 0xDC000000) {
- CacheMemoryLength = 0xC0000000;
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- MemoryBase,
- CacheMemoryLength,
- CacheWriteBack
- );
- ASSERT_EFI_ERROR (Status);
-
- MemoryBase = 0xC0000000;
- CacheMemoryLength = MemoryLength - 0xC0000000;
- if (MemoryLength > 0xE0000000) {
- CacheMemoryLength = 0x20000000;
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- MemoryBase,
- CacheMemoryLength,
- CacheWriteBack
- );
- ASSERT_EFI_ERROR (Status);
-
- MemoryBase = 0xE0000000;
- CacheMemoryLength = MemoryLength - 0xE0000000;
- }
- }
-
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- MemoryBase,
- CacheMemoryLength,
- CacheWriteBack
- );
- ASSERT_EFI_ERROR (Status);
-
- if (LowMemoryLength != MemoryLength) {
- MemoryBase = LowMemoryLength;
- MemoryLength -= LowMemoryLength;
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- MemoryBase,
- MemoryLength,
- CacheUncacheable
- );
- ASSERT_EFI_ERROR (Status);
- }
-
- ///
- /// VGA-MMIO - 0xA0000 to 0xC0000 to be UC
- ///
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- 0xA0000,
- 0x20000,
- CacheUncacheable
- );
- ASSERT_EFI_ERROR (Status);
-
- ///
- /// Update MTRR setting from MTRR buffer
- ///
- MtrrSetAllMtrrs (&MtrrSetting);
-
- return ;
-}
-
VOID
ReportCpuHob (
VOID
diff --git a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf
index 0736c8d494..74a9b91540 100644
--- a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf
+++ b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf
@@ -23,15 +23,14 @@
BaseMemoryLib
HobLib
PeiServicesLib
- MtrrLib
BoardInitLib
TestPointCheckLib
+ SetCacheMtrrLib
[Packages]
MinPlatformPkg/MinPlatformPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- UefiCpuPkg/UefiCpuPkg.dec
[Sources]
PlatformInitPostMem.c
@@ -44,14 +43,6 @@
[Protocols]
-[Guids]
- gEfiSmmSmramMemoryGuid ## CONSUMES
-
[Depex]
gEfiPeiMemoryDiscoveredPpiGuid
-[Pcd]
- gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase
- gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit
- gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBBase
- gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBLimit
diff --git a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
index 2c3a13106e..af5dbe8772 100644
--- a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
+++ b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
@@ -1,7 +1,7 @@
### @file
# Component information file for the Platform Init Pre-Memory PEI module.
#
-# Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -22,23 +22,20 @@
HobLib
IoLib
MemoryAllocationLib
- MtrrLib
PeimEntryPoint
PeiServicesLib
ReportFvLib
TestPointCheckLib
TimerLib
+ SetCacheMtrrLib
[Packages]
MinPlatformPkg/MinPlatformPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- UefiCpuPkg/UefiCpuPkg.dec
[Pcd]
gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode ## CONSUMES
- gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSUMES
- gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## CONSUMES
gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit ## CONSUMES
gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit ## CONSUMES
--
2.13.3.windows.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [edk2-platforms: PATCH v3 3/6] KabylakeOpenBoardPkg: Add SetCacheMtrrLib library class.
2019-10-31 10:28 [edk2-platforms: PATCH v3 0/6] Add SetCacheMtrrLib library class Chiu, Chasel
2019-10-31 10:28 ` [edk2-platforms: PATCH v3 1/6] MinPlatformPkg: " Chiu, Chasel
2019-10-31 10:28 ` [edk2-platforms: PATCH v3 2/6] " Chiu, Chasel
@ 2019-10-31 10:28 ` Chiu, Chasel
2019-11-01 18:29 ` [edk2-devel] " Nate DeSimone
2019-10-31 10:28 ` [edk2-platforms: PATCH v3 4/6] WhiskeylakeOpenBoardPkg: " Chiu, Chasel
` (2 subsequent siblings)
5 siblings, 1 reply; 16+ messages in thread
From: Chiu, Chasel @ 2019-10-31 10:28 UTC (permalink / raw)
To: devel; +Cc: Michael Kubacki, Nate DeSimone, Liming Gao, Jeremy Soller
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2314
Kabylake boards are relying on FSP to configure MTRRs so
they can include SetCacheMtrrLibNull.
Test: internal platform can boot with FSP API and Dispatch modes.
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c | 640 ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc | 3 ++-
Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf | 2 +-
Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf | 67 -------------------------------------------------------------------
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc | 1 +
5 files changed, 4 insertions(+), 709 deletions(-)
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c
deleted file mode 100644
index b784026c1b..0000000000
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c
+++ /dev/null
@@ -1,640 +0,0 @@
-/** @file
- Source code file for Platform Init Pre-Memory PEI module
-
-Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <Base.h>
-#include <IndustryStandard/Pci30.h>
-#include <Library/IoLib.h>
-#include <Library/DebugLib.h>
-#include <Library/HobLib.h>
-#include <Library/PcdLib.h>
-#include <Library/TimerLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/PeiServicesLib.h>
-#include <Library/MtrrLib.h>
-#include <Library/ReportFvLib.h>
-#include <Ppi/ReadOnlyVariable2.h>
-#include <Ppi/MemoryDiscovered.h>
-#include <Ppi/FirmwareVolumeInfo.h>
-#include <Ppi/BootInRecoveryMode.h>
-#include <Ppi/MasterBootMode.h>
-#include <Guid/FirmwareFileSystem2.h>
-#include <Library/PeiServicesTablePointerLib.h>
-#include <Library/BoardInitLib.h>
-#include <Library/TestPointCheckLib.h>
-#include <Guid/MemoryTypeInformation.h>
-#include <Ppi/PlatformMemorySize.h>
-#include <Ppi/BaseMemoryTest.h>
-
-EFI_STATUS
-EFIAPI
-MemoryDiscoveredPpiNotifyCallback (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
- IN VOID *Ppi
- );
-
-EFI_STATUS
-EFIAPI
-GetPlatformMemorySize (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_PLATFORM_MEMORY_SIZE_PPI *This,
- IN OUT UINT64 *MemorySize
- );
-
-/**
-
- This function checks the memory range in PEI.
-
- @param PeiServices Pointer to PEI Services.
- @param This Pei memory test PPI pointer.
- @param BeginAddress Beginning of the memory address to be checked.
- @param MemoryLength Bytes of memory range to be checked.
- @param Operation Type of memory check operation to be performed.
- @param ErrorAddress Return the address of the error memory address.
-
- @retval EFI_SUCCESS The operation completed successfully.
- @retval EFI_DEVICE_ERROR Memory test failed. It's not safe to use this range of memory.
-
-**/
-EFI_STATUS
-EFIAPI
-BaseMemoryTest (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_BASE_MEMORY_TEST_PPI *This,
- IN EFI_PHYSICAL_ADDRESS BeginAddress,
- IN UINT64 MemoryLength,
- IN PEI_MEMORY_TEST_OP Operation,
- OUT EFI_PHYSICAL_ADDRESS *ErrorAddress
- );
-
-static EFI_PEI_NOTIFY_DESCRIPTOR mMemDiscoveredNotifyList = {
- (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
- &gEfiPeiMemoryDiscoveredPpiGuid,
- (EFI_PEIM_NOTIFY_ENTRY_POINT) MemoryDiscoveredPpiNotifyCallback
-};
-
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mPpiListRecoveryBootMode = {
- (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
- &gEfiPeiBootInRecoveryModePpiGuid,
- NULL
-};
-
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mPpiBootMode = {
- (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
- &gEfiPeiMasterBootModePpiGuid,
- NULL
-};
-
-static PEI_BASE_MEMORY_TEST_PPI mPeiBaseMemoryTestPpi = { BaseMemoryTest };
-
-static PEI_PLATFORM_MEMORY_SIZE_PPI mMemoryMemorySizePpi = { GetPlatformMemorySize };
-
-static EFI_PEI_PPI_DESCRIPTOR mMemPpiList[] = {
- {
- EFI_PEI_PPI_DESCRIPTOR_PPI,
- &gPeiBaseMemoryTestPpiGuid,
- &mPeiBaseMemoryTestPpi
- },
- {
- (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
- &gPeiPlatformMemorySizePpiGuid,
- &mMemoryMemorySizePpi
- },
-};
-
-///
-/// Memory Reserved should be between 125% to 150% of the Current required memory
-/// otherwise BdsMisc.c would do a reset to make it 125% to avoid s4 resume issues.
-///
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
- { EfiACPIReclaimMemory, FixedPcdGet32 (PcdPlatformEfiAcpiReclaimMemorySize) }, // ASL
- { EfiACPIMemoryNVS, FixedPcdGet32 (PcdPlatformEfiAcpiNvsMemorySize) }, // ACPI NVS (including S3 related)
- { EfiReservedMemoryType, FixedPcdGet32 (PcdPlatformEfiReservedMemorySize) }, // BIOS Reserved (including S3 related)
- { EfiRuntimeServicesData, FixedPcdGet32 (PcdPlatformEfiRtDataMemorySize) }, // Runtime Service Data
- { EfiRuntimeServicesCode, FixedPcdGet32 (PcdPlatformEfiRtCodeMemorySize) }, // Runtime Service Code
- { EfiMaxMemoryType, 0 }
-};
-
-VOID
-BuildMemoryTypeInformation (
- VOID
- )
-{
- EFI_STATUS Status;
- EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
- UINTN DataSize;
- EFI_MEMORY_TYPE_INFORMATION MemoryData[EfiMaxMemoryType + 1];
-
- //
- // Locate system configuration variable
- //
- Status = PeiServicesLocatePpi(
- &gEfiPeiReadOnlyVariable2PpiGuid, // GUID
- 0, // INSTANCE
- NULL, // EFI_PEI_PPI_DESCRIPTOR
- (VOID **) &VariableServices // PPI
- );
- ASSERT_EFI_ERROR(Status);
-
- DataSize = sizeof (MemoryData);
- Status = VariableServices->GetVariable (
- VariableServices,
- EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME,
- &gEfiMemoryTypeInformationGuid,
- NULL,
- &DataSize,
- &MemoryData
- );
- if (EFI_ERROR(Status)) {
- DataSize = sizeof (mDefaultMemoryTypeInformation);
- CopyMem(MemoryData, mDefaultMemoryTypeInformation, DataSize);
- }
-
- ///
- /// Build the GUID'd HOB for DXE
- ///
- BuildGuidDataHob (
- &gEfiMemoryTypeInformationGuid,
- MemoryData,
- DataSize
- );
-}
-
-EFI_STATUS
-EFIAPI
-GetPlatformMemorySize (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_PLATFORM_MEMORY_SIZE_PPI *This,
- IN OUT UINT64 *MemorySize
- )
-{
- EFI_STATUS Status;
- EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable;
- UINTN DataSize;
- EFI_MEMORY_TYPE_INFORMATION MemoryData[EfiMaxMemoryType + 1];
- UINTN Index;
- EFI_BOOT_MODE BootMode;
- UINTN IndexNumber;
-
-#define PEI_MIN_MEMORY_SIZE (EFI_PHYSICAL_ADDRESS) ((320 * 0x100000))
-
- *MemorySize = PEI_MIN_MEMORY_SIZE;
- Status = PeiServicesLocatePpi (
- &gEfiPeiReadOnlyVariable2PpiGuid,
- 0,
- NULL,
- (VOID **)&Variable
- );
-
- ASSERT_EFI_ERROR (Status);
-
- Status = PeiServicesGetBootMode (&BootMode);
- ASSERT_EFI_ERROR (Status);
-
- DataSize = sizeof (MemoryData);
-
- Status = Variable->GetVariable (
- Variable,
- EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME,
- &gEfiMemoryTypeInformationGuid,
- NULL,
- &DataSize,
- &MemoryData
- );
- IndexNumber = sizeof (mDefaultMemoryTypeInformation) / sizeof (EFI_MEMORY_TYPE_INFORMATION);
-
- //
- // Accumulate maximum amount of memory needed
- //
-
- DEBUG((DEBUG_ERROR, "PEI_MIN_MEMORY_SIZE:%dKB \n", DivU64x32(*MemorySize,1024)));
- DEBUG((DEBUG_ERROR, "IndexNumber:%d MemoryDataNumber%d \n", IndexNumber,DataSize/ sizeof (EFI_MEMORY_TYPE_INFORMATION)));
- if (EFI_ERROR (Status)) {
- //
- // Start with minimum memory
- //
- for (Index = 0; Index < IndexNumber; Index++) {
- DEBUG((DEBUG_ERROR, "Index[%d].Type = %d .NumberOfPages=0x%x\n", Index,mDefaultMemoryTypeInformation[Index].Type,mDefaultMemoryTypeInformation[Index].NumberOfPages));
- *MemorySize += mDefaultMemoryTypeInformation[Index].NumberOfPages * EFI_PAGE_SIZE;
- }
- DEBUG((DEBUG_ERROR, "No memory type, Total platform memory:%dKB \n", DivU64x32(*MemorySize,1024)));
- } else {
- //
- // Start with at least 0x200 pages of memory for the DXE Core and the DXE Stack
- //
- for (Index = 0; Index < IndexNumber; Index++) {
- DEBUG((DEBUG_ERROR, "Index[%d].Type = %d .NumberOfPages=0x%x\n", Index,MemoryData[Index].Type,MemoryData[Index].NumberOfPages));
- *MemorySize += MemoryData[Index].NumberOfPages * EFI_PAGE_SIZE;
-
- }
- DEBUG((DEBUG_ERROR, "has memory type, Total platform memory:%dKB \n", DivU64x32(*MemorySize,1024)));
- }
-
- return EFI_SUCCESS;
-}
-
-/**
-
- This function checks the memory range in PEI.
-
- @param PeiServices Pointer to PEI Services.
- @param This Pei memory test PPI pointer.
- @param BeginAddress Beginning of the memory address to be checked.
- @param MemoryLength Bytes of memory range to be checked.
- @param Operation Type of memory check operation to be performed.
- @param ErrorAddress Return the address of the error memory address.
-
- @retval EFI_SUCCESS The operation completed successfully.
- @retval EFI_DEVICE_ERROR Memory test failed. It's not safe to use this range of memory.
-
-**/
-EFI_STATUS
-EFIAPI
-BaseMemoryTest (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_BASE_MEMORY_TEST_PPI *This,
- IN EFI_PHYSICAL_ADDRESS BeginAddress,
- IN UINT64 MemoryLength,
- IN PEI_MEMORY_TEST_OP Operation,
- OUT EFI_PHYSICAL_ADDRESS *ErrorAddress
- )
-{
- UINT32 TestPattern;
- UINT32 SpanSize;
- EFI_PHYSICAL_ADDRESS TempAddress;
-
-#define MEMORY_TEST_PATTERN 0x5A5A5A5A
-#define MEMORY_TEST_COVER_SPAN 0x40000
-
- TestPattern = MEMORY_TEST_PATTERN;
- SpanSize = 0;
-
- //
- // Make sure we don't try and test anything above the max physical address range
- //
- ASSERT (BeginAddress + MemoryLength < MAX_ADDRESS);
-
- switch (Operation) {
- case Extensive:
- SpanSize = 0x4;
- break;
-
- case Sparse:
- case Quick:
- SpanSize = MEMORY_TEST_COVER_SPAN;
- break;
-
- case Ignore:
- goto Done;
- break;
- }
- //
- // Write the test pattern into memory range
- //
- TempAddress = BeginAddress;
- while (TempAddress < BeginAddress + MemoryLength) {
- (*(UINT32 *) (UINTN) TempAddress) = TestPattern;
- TempAddress += SpanSize;
- }
- //
- // Read pattern from memory and compare it
- //
- TempAddress = BeginAddress;
- while (TempAddress < BeginAddress + MemoryLength) {
- if ((*(UINT32 *) (UINTN) TempAddress) != TestPattern) {
- *ErrorAddress = TempAddress;
- return EFI_DEVICE_ERROR;
- }
-
- TempAddress += SpanSize;
- }
-
-Done:
-
- return EFI_SUCCESS;
-}
-
-/**
- Set Cache Mtrr.
-**/
-VOID
-SetCacheMtrr (
- VOID
- )
-{
- EFI_STATUS Status;
- EFI_PEI_HOB_POINTERS Hob;
- MTRR_SETTINGS MtrrSetting;
- UINT64 MemoryBase;
- UINT64 MemoryLength;
- UINT64 LowMemoryLength;
- UINT64 HighMemoryLength;
- EFI_BOOT_MODE BootMode;
- EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;
- UINT64 CacheMemoryLength;
-
- ///
- /// Reset all MTRR setting.
- ///
- ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS));
-
- ///
- /// Cache the Flash area as WP to boost performance
- ///
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- (UINTN) PcdGet32 (PcdFlashAreaBaseAddress),
- (UINTN) PcdGet32 (PcdFlashAreaSize),
- CacheWriteProtected
- );
- ASSERT_EFI_ERROR (Status);
-
- ///
- /// Update MTRR setting from MTRR buffer for Flash Region to be WP to boost performance
- ///
- MtrrSetAllMtrrs (&MtrrSetting);
-
- ///
- /// Set low to 1 MB. Since 1MB cacheability will always be set
- /// until override by CSM.
- /// Initialize high memory to 0.
- ///
- LowMemoryLength = 0x100000;
- HighMemoryLength = 0;
- ResourceAttribute = (
- EFI_RESOURCE_ATTRIBUTE_PRESENT |
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
- );
-
- Status = PeiServicesGetBootMode (&BootMode);
- ASSERT_EFI_ERROR (Status);
-
- if (BootMode != BOOT_ON_S3_RESUME) {
- ResourceAttribute |= EFI_RESOURCE_ATTRIBUTE_TESTED;
- }
-
- Status = PeiServicesGetHobList ((VOID **) &Hob.Raw);
- while (!END_OF_HOB_LIST (Hob)) {
- if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {
- if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) ||
- ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) &&
- (Hob.ResourceDescriptor->ResourceAttribute == ResourceAttribute))
- ) {
- if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000000ULL) {
- HighMemoryLength += Hob.ResourceDescriptor->ResourceLength;
- } else if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000) {
- LowMemoryLength += Hob.ResourceDescriptor->ResourceLength;
- }
- }
- }
-
- Hob.Raw = GET_NEXT_HOB (Hob);
- }
-
- DEBUG ((DEBUG_INFO, "Memory Length (Below 4GB) = %lx.\n", LowMemoryLength));
- DEBUG ((DEBUG_INFO, "Memory Length (Above 4GB) = %lx.\n", HighMemoryLength));
-
- ///
- /// Assume size of main memory is multiple of 256MB
- ///
- MemoryLength = (LowMemoryLength + 0xFFFFFFF) & 0xF0000000;
- MemoryBase = 0;
-
- CacheMemoryLength = MemoryLength;
- ///
- /// Programming MTRRs to avoid override SPI region with UC when MAX TOLUD Length >= 3.5GB
- ///
- if (MemoryLength > 0xDC000000) {
- CacheMemoryLength = 0xC0000000;
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- MemoryBase,
- CacheMemoryLength,
- CacheWriteBack
- );
- ASSERT_EFI_ERROR (Status);
-
- MemoryBase = 0xC0000000;
- CacheMemoryLength = MemoryLength - 0xC0000000;
- if (MemoryLength > 0xE0000000) {
- CacheMemoryLength = 0x20000000;
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- MemoryBase,
- CacheMemoryLength,
- CacheWriteBack
- );
- ASSERT_EFI_ERROR (Status);
-
- MemoryBase = 0xE0000000;
- CacheMemoryLength = MemoryLength - 0xE0000000;
- }
- }
-
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- MemoryBase,
- CacheMemoryLength,
- CacheWriteBack
- );
- ASSERT_EFI_ERROR (Status);
-
- if (LowMemoryLength != MemoryLength) {
- MemoryBase = LowMemoryLength;
- MemoryLength -= LowMemoryLength;
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- MemoryBase,
- MemoryLength,
- CacheUncacheable
- );
- ASSERT_EFI_ERROR (Status);
- }
-
- ///
- /// VGA-MMIO - 0xA0000 to 0xC0000 to be UC
- ///
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- 0xA0000,
- 0x20000,
- CacheUncacheable
- );
- ASSERT_EFI_ERROR (Status);
-
- ///
- /// Update MTRR setting from MTRR buffer
- ///
- MtrrSetAllMtrrs (&MtrrSetting);
-
- return ;
-}
-
-VOID
-ReportCpuHob (
- VOID
- )
-{
- UINT8 PhysicalAddressBits;
- UINT32 RegEax;
-
- AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
- if (RegEax >= 0x80000008) {
- AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
- PhysicalAddressBits = (UINT8) RegEax;
- } else {
- PhysicalAddressBits = 36;
- }
-
- ///
- /// Create a CPU hand-off information
- ///
- BuildCpuHob (PhysicalAddressBits, 16);
-}
-
-/**
- Install Firmware Volume Hob's once there is main memory
-
- @param[in] PeiServices General purpose services available to every PEIM.
- @param[in] NotifyDescriptor Notify that this module published.
- @param[in] Ppi PPI that was installed.
-
- @retval EFI_SUCCESS The function completed successfully.
-**/
-EFI_STATUS
-EFIAPI
-MemoryDiscoveredPpiNotifyCallback (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
- IN VOID *Ppi
- )
-{
- EFI_STATUS Status;
- EFI_BOOT_MODE BootMode;
-
- Status = BoardInitAfterMemoryInit ();
- ASSERT_EFI_ERROR (Status);
-
- Status = PeiServicesGetBootMode (&BootMode);
- ASSERT_EFI_ERROR (Status);
-
-
- ReportCpuHob ();
-
- TestPointMemoryDiscoveredMtrrFunctional ();
-
- TestPointMemoryDiscoveredMemoryResourceFunctional ();
-
- ///
- /// If S3 resume, then we are done
- ///
- if (BootMode == BOOT_ON_S3_RESUME) {
- return EFI_SUCCESS;
- }
-
- TestPointMemoryDiscoveredDmaProtectionEnabled ();
-
- if (PcdGetBool (PcdStopAfterMemInit)) {
- CpuDeadLoop ();
- }
-
- return Status;
-}
-
-
-/**
- This function handles PlatformInit task after PeiReadOnlyVariable2 PPI produced
-
- @param[in] PeiServices Pointer to PEI Services Table.
-
- @retval EFI_SUCCESS The function completes successfully
- @retval others
-**/
-EFI_STATUS
-EFIAPI
-PlatformInitPreMem (
- IN CONST EFI_PEI_SERVICES **PeiServices
- )
-{
- EFI_STATUS Status;
- EFI_BOOT_MODE BootMode;
-
- //
- // Start board detection
- //
- BoardDetect ();
-
- BoardDebugInit ();
-
- TestPointDebugInitDone ();
-
- if (PcdGetBool (PcdStopAfterDebugInit)) {
- CpuDeadLoop ();
- }
-
- BootMode = BoardBootModeDetect ();
- Status = PeiServicesSetBootMode (BootMode);
- ASSERT_EFI_ERROR (Status);
- if (BootMode == BOOT_IN_RECOVERY_MODE) {
- Status = PeiServicesInstallPpi (&mPpiListRecoveryBootMode);
- }
- ///
- /// Signal possible dependent modules that there has been a
- /// final boot mode determination, it is used to build BIST
- /// Hob for Dxe use.
- ///
- Status = PeiServicesInstallPpi (&mPpiBootMode);
- ASSERT_EFI_ERROR (Status);
-
- BuildMemoryTypeInformation ();
-
- if (!PcdGetBool(PcdFspWrapperBootMode)) {
- Status = PeiServicesInstallPpi (mMemPpiList);
- ASSERT_EFI_ERROR (Status);
- }
-
- Status = BoardInitBeforeMemoryInit ();
- ASSERT_EFI_ERROR (Status);
-
- return Status;
-}
-
-
-/**
- Platform Init before memory PEI module entry point
-
- @param[in] FileHandle Not used.
- @param[in] PeiServices General purpose services available to every PEIM.
-
- @retval EFI_SUCCESS The function completes successfully
- @retval EFI_OUT_OF_RESOURCES Insufficient resources to create database
-**/
-EFI_STATUS
-EFIAPI
-PlatformInitPreMemEntryPoint (
- IN EFI_PEI_FILE_HANDLE FileHandle,
- IN CONST EFI_PEI_SERVICES **PeiServices
- )
-{
- EFI_STATUS Status;
-
- Status = PlatformInitPreMem (PeiServices);
-
- ///
- /// After code reorangized, memorycallback will run because the PPI is already
- /// installed when code run to here, it is supposed that the InstallEfiMemory is
- /// done before.
- ///
- Status = PeiServicesNotifyPpi (&mMemDiscoveredNotifyList);
-
- return Status;
-}
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
index f59248bba4..000cf2be4c 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
@@ -159,6 +159,7 @@
#######################################
DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
+ SetCacheMtrrLib|$(PLATFORM_PACKAGE)/Library/SetCacheMtrrLib/SetCacheMtrrLibNull.inf
#######################################
# Platform Package
@@ -260,7 +261,7 @@
# Platform Package
#######################################
$(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf
- $(PROJECT)/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf {
+ $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf {
<LibraryClasses>
!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport == FALSE
BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf
index 80efab1aad..6827019c25 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf
@@ -237,7 +237,7 @@ INF MdeModulePkg/Core/Pei/PeiMain.inf
!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePreMemoryInclude.fdf
INF $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf
-INF $(PROJECT)/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
+INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf
INF $(PLATFORM_BOARD_PACKAGE)/BiosInfo/BiosInfo.inf
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
deleted file mode 100644
index 76dd67d1a8..0000000000
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
+++ /dev/null
@@ -1,67 +0,0 @@
-### @file
-# Component information file for the Platform Init Pre-Memory PEI module.
-#
-# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-###
-
-[Defines]
- INF_VERSION = 0x00010017
- BASE_NAME = PlatformInitPreMem
- FILE_GUID = EEEE611D-F78F-4FB9-B868-55907F169280
- VERSION_STRING = 1.0
- MODULE_TYPE = PEIM
- ENTRY_POINT = PlatformInitPreMemEntryPoint
-
-[LibraryClasses]
- BaseMemoryLib
- BoardInitLib
- DebugLib
- HobLib
- IoLib
- MemoryAllocationLib
- MtrrLib
- PeimEntryPoint
- PeiServicesLib
- ReportFvLib
- TestPointCheckLib
- TimerLib
-
-[Packages]
- MinPlatformPkg/MinPlatformPkg.dec
- MdeModulePkg/MdeModulePkg.dec
- MdePkg/MdePkg.dec
- UefiCpuPkg/UefiCpuPkg.dec
-
-[Pcd]
- gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode ## CONSUMES
- gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSUMES
- gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## CONSUMES
- gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit ## CONSUMES
- gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit ## CONSUMES
-
-[FixedPcd]
- gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize ## CONSUMES
- gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize ## CONSUMES
- gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize ## CONSUMES
- gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize ## CONSUMES
- gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize ## CONSUMES
-
-[Sources]
- PlatformInitPreMem.c
-
-[Ppis]
- gEfiPeiMemoryDiscoveredPpiGuid
- gEfiPeiMasterBootModePpiGuid ## PRODUCES
- gEfiPeiBootInRecoveryModePpiGuid ## PRODUCES
- gEfiPeiReadOnlyVariable2PpiGuid
- gPeiBaseMemoryTestPpiGuid
- gPeiPlatformMemorySizePpiGuid
-
-[Guids]
- gEfiMemoryTypeInformationGuid
-
-[Depex]
- gEfiPeiReadOnlyVariable2PpiGuid
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
index 7e65eeda6f..8178604554 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
@@ -208,6 +208,7 @@
!if $(TARGET) == DEBUG
TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf
!endif
+ SetCacheMtrrLib|$(PLATFORM_PACKAGE)/Library/SetCacheMtrrLib/SetCacheMtrrLibNull.inf
#######################################
# Board Package
--
2.13.3.windows.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [edk2-platforms: PATCH v3 4/6] WhiskeylakeOpenBoardPkg: Add SetCacheMtrrLib library class.
2019-10-31 10:28 [edk2-platforms: PATCH v3 0/6] Add SetCacheMtrrLib library class Chiu, Chasel
` (2 preceding siblings ...)
2019-10-31 10:28 ` [edk2-platforms: PATCH v3 3/6] KabylakeOpenBoardPkg: " Chiu, Chasel
@ 2019-10-31 10:28 ` Chiu, Chasel
2019-11-01 18:29 ` [edk2-devel] " Nate DeSimone
2019-10-31 10:28 ` [edk2-platforms: PATCH v3 5/6] PurleyOpenBoardPkg/BoardMtOlympus: " Chiu, Chasel
2019-10-31 10:28 ` [edk2-platforms: PATCH v3 6/6] SimicsOpenBoardPkg/BoardX58Ich10: " Chiu, Chasel
5 siblings, 1 reply; 16+ messages in thread
From: Chiu, Chasel @ 2019-10-31 10:28 UTC (permalink / raw)
To: devel; +Cc: Michael Kubacki, Nate DeSimone
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2314
Whiskeylake board relying on FSP to configure MTRRs so
it can include SetCacheMtrrLibNull.
Test: internal platform can boot with FSP API modes.
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc | 1 +
1 file changed, 1 insertion(+)
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc
index 8e0ea2d5ce..20b16fd7ef 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc
@@ -164,6 +164,7 @@
!if $(TARGET) == DEBUG
TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf
!endif
+ SetCacheMtrrLib|$(PLATFORM_PACKAGE)/Library/SetCacheMtrrLib/SetCacheMtrrLibNull.inf
#######################################
# Board Package
--
2.13.3.windows.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [edk2-platforms: PATCH v3 5/6] PurleyOpenBoardPkg/BoardMtOlympus: Add SetCacheMtrrLib library class.
2019-10-31 10:28 [edk2-platforms: PATCH v3 0/6] Add SetCacheMtrrLib library class Chiu, Chasel
` (3 preceding siblings ...)
2019-10-31 10:28 ` [edk2-platforms: PATCH v3 4/6] WhiskeylakeOpenBoardPkg: " Chiu, Chasel
@ 2019-10-31 10:28 ` Chiu, Chasel
2019-11-01 18:29 ` [edk2-devel] " Nate DeSimone
2019-10-31 10:28 ` [edk2-platforms: PATCH v3 6/6] SimicsOpenBoardPkg/BoardX58Ich10: " Chiu, Chasel
5 siblings, 1 reply; 16+ messages in thread
From: Chiu, Chasel @ 2019-10-31 10:28 UTC (permalink / raw)
To: devel; +Cc: Shifei A Lu, Xiaohu Zhou, Isaac W Oram
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2314
Include SetCacheMtrrLib from MinPlatformPkg.
Cc: Shifei A Lu <shifei.a.lu@intel.com>
Cc: Xiaohu Zhou <bowen.zhou@intel.com>
Cc: Isaac W Oram <isaac.w.oram@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkg.dsc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkg.dsc b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkg.dsc
index 595ffd4144..488243081f 100644
--- a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkg.dsc
+++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkg.dsc
@@ -1,6 +1,6 @@
### @file
#
-# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -135,6 +135,7 @@
!include $(RC_PKG)/RcDxeLib.dsc
!include $(SKT_PKG)/SktDxeLib.dsc
!include $(PCH_PKG)/PchDxeLib.dsc
+ SetCacheMtrrLib|MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
[LibraryClasses.X64]
BoardAcpiTableLib|$(BOARD_PKG)/$(BOARD_NAME)/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf
--
2.13.3.windows.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [edk2-platforms: PATCH v3 6/6] SimicsOpenBoardPkg/BoardX58Ich10: Add SetCacheMtrrLib library class.
2019-10-31 10:28 [edk2-platforms: PATCH v3 0/6] Add SetCacheMtrrLib library class Chiu, Chasel
` (4 preceding siblings ...)
2019-10-31 10:28 ` [edk2-platforms: PATCH v3 5/6] PurleyOpenBoardPkg/BoardMtOlympus: " Chiu, Chasel
@ 2019-10-31 10:28 ` Chiu, Chasel
2019-10-31 19:42 ` Agyeman, Prince
2019-11-01 18:29 ` [edk2-devel] " Nate DeSimone
5 siblings, 2 replies; 16+ messages in thread
From: Chiu, Chasel @ 2019-10-31 10:28 UTC (permalink / raw)
To: devel; +Cc: Wei David Y, Agyeman Prince
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2314
Include SetCacheMtrrLib from MinPlatformPkg.
Cc: Wei David Y <david.y.wei@intel.com>
Cc: Agyeman Prince <prince.agyeman@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc | 1 +
1 file changed, 1 insertion(+)
diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc
index 4f8ab4170d..8cad7b5b69 100644
--- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc
+++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc
@@ -136,6 +136,7 @@
TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf
!endif
TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPointLib.inf
+ SetCacheMtrrLib|$(PLATFORM_PACKAGE)/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
[LibraryClasses.common.DXE_DRIVER]
#######################################
--
2.13.3.windows.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [edk2-devel] [edk2-platforms: PATCH v3 1/6] MinPlatformPkg: Add SetCacheMtrrLib library class.
2019-10-31 10:28 ` [edk2-platforms: PATCH v3 1/6] MinPlatformPkg: " Chiu, Chasel
@ 2019-10-31 17:02 ` Kubacki, Michael A
2019-11-01 1:24 ` Chiu, Chasel
2019-11-01 18:29 ` Nate DeSimone
1 sibling, 1 reply; 16+ messages in thread
From: Kubacki, Michael A @ 2019-10-31 17:02 UTC (permalink / raw)
To: devel@edk2.groups.io, Chiu, Chasel; +Cc: Desimone, Nathaniel L, Gao, Liming
Thanks for updating the name.
Platform\Intel\MinPlatformPkg\Include\Library\SetCacheMtrrLib.h:
* The function description for SetCacheMtrrAfterEndOfPei () is
constraining the implementation in a way that I don't believe
is required:
/**
Update MTRR setting and set write back as default memory attribute.
@retval EFI_SUCCESS The function completes successfully.
@retval Others Some error occurs.
**/
While it is typical to set the default memory type to WB, I don't
think this API should care whether that is the case.
* "SetCacheMtrrAtEndOfPei ()" better describes the way this
is actually being used but I don't think it is a must change.
With the function description updated:
Reviewed-by: Michael Kubacki <michael.a.kubacki@intel.com>
> -----Original Message-----
> From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Chiu,
> Chasel
> Sent: Thursday, October 31, 2019 3:28 AM
> To: devel@edk2.groups.io
> Cc: Kubacki, Michael A <michael.a.kubacki@intel.com>; Desimone, Nathaniel
> L <nathaniel.l.desimone@intel.com>; Gao, Liming <liming.gao@intel.com>
> Subject: [edk2-devel] [edk2-platforms: PATCH v3 1/6] MinPlatformPkg: Add
> SetCacheMtrrLib library class.
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2314
>
> MinPlatformPkg should contain the library class header (API) and the NULL
> library class instance.
>
> Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
> ---
> Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c
> | 327
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++
>
> Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLibN
> ull.c | 37 +++++++++++++++++++++++++++++++++++++
> Platform/Intel/MinPlatformPkg/Include/Library/SetCacheMtrrLib.h |
> 34 ++++++++++++++++++++++++++++++++++
>
> Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.in
> f | 46 ++++++++++++++++++++++++++++++++++++++++++++++
>
> Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLibN
> ull.inf | 29 +++++++++++++++++++++++++++++
> Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec | 6
> ++++--
> 6 files changed, 477 insertions(+), 2 deletions(-)
>
> diff --git
> a/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib
> .c
> b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib
> .c
> new file mode 100644
> index 0000000000..26f06321f7
> --- /dev/null
> +++
> b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrr
> +++ Lib.c
> @@ -0,0 +1,327 @@
> +/** @file
> +
> +SetCacheMtrr library functions.
> +This implementation is for typical platforms and may not be needed when
> +cache MTRR will be initialized by FSP.
> +
> +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <Uefi.h>
> +#include <PiPei.h>
> +#include <Library/HobLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/MtrrLib.h>
> +#include <Library/PeiServicesLib.h>
> +#include <Guid/SmramMemoryReserve.h>
> +
> +/**
> + Set Cache Mtrr.
> +**/
> +VOID
> +EFIAPI
> +SetCacheMtrr (
> + VOID
> + )
> +{
> + EFI_STATUS Status;
> + EFI_PEI_HOB_POINTERS Hob;
> + MTRR_SETTINGS MtrrSetting;
> + UINT64 MemoryBase;
> + UINT64 MemoryLength;
> + UINT64 LowMemoryLength;
> + UINT64 HighMemoryLength;
> + EFI_BOOT_MODE BootMode;
> + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;
> + UINT64 CacheMemoryLength;
> +
> + ///
> + /// Reset all MTRR setting.
> + ///
> + ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS));
> +
> + ///
> + /// Cache the Flash area as WP to boost performance /// Status =
> + MtrrSetMemoryAttributeInMtrrSettings (
> + &MtrrSetting,
> + (UINTN) PcdGet32 (PcdFlashAreaBaseAddress),
> + (UINTN) PcdGet32 (PcdFlashAreaSize),
> + CacheWriteProtected
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + ///
> + /// Update MTRR setting from MTRR buffer for Flash Region to be WP to
> + boost performance /// MtrrSetAllMtrrs (&MtrrSetting);
> +
> + ///
> + /// Set low to 1 MB. Since 1MB cacheability will always be set ///
> + until override by CSM.
> + /// Initialize high memory to 0.
> + ///
> + LowMemoryLength = 0x100000;
> + HighMemoryLength = 0;
> + ResourceAttribute = (
> + EFI_RESOURCE_ATTRIBUTE_PRESENT |
> + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
> + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
> + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
> + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
> + );
> +
> + Status = PeiServicesGetBootMode (&BootMode); ASSERT_EFI_ERROR
> + (Status);
> +
> + if (BootMode != BOOT_ON_S3_RESUME) {
> + ResourceAttribute |= EFI_RESOURCE_ATTRIBUTE_TESTED; }
> +
> + Status = PeiServicesGetHobList ((VOID **) &Hob.Raw); while
> + (!END_OF_HOB_LIST (Hob)) {
> + if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {
> + if ((Hob.ResourceDescriptor->ResourceType ==
> EFI_RESOURCE_SYSTEM_MEMORY) ||
> + ((Hob.ResourceDescriptor->ResourceType ==
> EFI_RESOURCE_MEMORY_RESERVED) &&
> + (Hob.ResourceDescriptor->ResourceAttribute == ResourceAttribute))
> + ) {
> + if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000000ULL) {
> + HighMemoryLength += Hob.ResourceDescriptor->ResourceLength;
> + } else if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000) {
> + LowMemoryLength += Hob.ResourceDescriptor->ResourceLength;
> + }
> + }
> + }
> +
> + Hob.Raw = GET_NEXT_HOB (Hob);
> + }
> +
> + DEBUG ((DEBUG_INFO, "Memory Length (Below 4GB) = %lx.\n",
> + LowMemoryLength)); DEBUG ((DEBUG_INFO, "Memory Length (Above
> 4GB) =
> + %lx.\n", HighMemoryLength));
> +
> + ///
> + /// Assume size of main memory is multiple of 256MB ///
> + MemoryLength = (LowMemoryLength + 0xFFFFFFF) & 0xF0000000;
> MemoryBase
> + = 0;
> +
> + CacheMemoryLength = MemoryLength;
> + ///
> + /// Programming MTRRs to avoid override SPI region with UC when MAX
> + TOLUD Length >= 3.5GB /// if (MemoryLength > 0xDC000000) {
> + CacheMemoryLength = 0xC0000000;
> + Status = MtrrSetMemoryAttributeInMtrrSettings (
> + &MtrrSetting,
> + MemoryBase,
> + CacheMemoryLength,
> + CacheWriteBack
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + MemoryBase = 0xC0000000;
> + CacheMemoryLength = MemoryLength - 0xC0000000;
> + if (MemoryLength > 0xE0000000) {
> + CacheMemoryLength = 0x20000000;
> + Status = MtrrSetMemoryAttributeInMtrrSettings (
> + &MtrrSetting,
> + MemoryBase,
> + CacheMemoryLength,
> + CacheWriteBack
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + MemoryBase = 0xE0000000;
> + CacheMemoryLength = MemoryLength - 0xE0000000;
> + }
> + }
> +
> + Status = MtrrSetMemoryAttributeInMtrrSettings (
> + &MtrrSetting,
> + MemoryBase,
> + CacheMemoryLength,
> + CacheWriteBack
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + if (LowMemoryLength != MemoryLength) {
> + MemoryBase = LowMemoryLength;
> + MemoryLength -= LowMemoryLength;
> + Status = MtrrSetMemoryAttributeInMtrrSettings (
> + &MtrrSetting,
> + MemoryBase,
> + MemoryLength,
> + CacheUncacheable
> + );
> + ASSERT_EFI_ERROR (Status);
> + }
> +
> + ///
> + /// VGA-MMIO - 0xA0000 to 0xC0000 to be UC /// Status =
> + MtrrSetMemoryAttributeInMtrrSettings (
> + &MtrrSetting,
> + 0xA0000,
> + 0x20000,
> + CacheUncacheable
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + ///
> + /// Update MTRR setting from MTRR buffer /// MtrrSetAllMtrrs
> + (&MtrrSetting);
> +
> + return ;
> +}
> +
> +/**
> + Update MTRR setting and set write back as default memory attribute.
> +
> + @retval EFI_SUCCESS The function completes successfully.
> + @retval Others Some error occurs.
> +**/
> +EFI_STATUS
> +EFIAPI
> +SetCacheMtrrAfterEndOfPei (
> + VOID
> + )
> +{
> + EFI_STATUS Status;
> + MTRR_SETTINGS MtrrSetting;
> + EFI_PEI_HOB_POINTERS Hob;
> + UINT64 MemoryBase;
> + UINT64 MemoryLength;
> + UINT64 Power2Length;
> + EFI_BOOT_MODE BootMode;
> + UINTN Index;
> + UINT64 SmramSize;
> + UINT64 SmramBase;
> + EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock;
> + Status = PeiServicesGetBootMode (&BootMode);
> + ASSERT_EFI_ERROR (Status);
> +
> + if (BootMode == BOOT_ON_S3_RESUME) {
> + return EFI_SUCCESS;
> + }
> + //
> + // Clear the CAR Settings
> + //
> + ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS));
> +
> + //
> + // Default Cachable attribute will be set to WB to support large
> + memory size/hot plug memory // MtrrSetting.MtrrDefType &=
> + ~((UINT64)(0xFF)); MtrrSetting.MtrrDefType |= (UINT64)
> + CacheWriteBack;
> +
> + //
> + // Set fixed cache for memory range below 1MB // Status =
> + MtrrSetMemoryAttributeInMtrrSettings (
> + &MtrrSetting,
> + 0x0,
> + 0xA0000,
> + CacheWriteBack
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = MtrrSetMemoryAttributeInMtrrSettings (
> + &MtrrSetting,
> + 0xA0000,
> + 0x20000,
> + CacheUncacheable
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = MtrrSetMemoryAttributeInMtrrSettings (
> + &MtrrSetting,
> + 0xC0000,
> + 0x40000,
> + CacheWriteProtected
> + );
> + ASSERT_EFI_ERROR ( Status);
> +
> + //
> + // PI SMM IPL can't set SMRAM to WB because at that time CPU ARCH
> protocol is not available.
> + // Set cacheability of SMRAM to WB here to improve SMRAM initialization
> performance.
> + //
> + SmramSize = 0;
> + SmramBase = 0;
> + Status = PeiServicesGetHobList ((VOID **) &Hob.Raw); while
> + (!END_OF_HOB_LIST (Hob)) {
> + if (Hob.Header->HobType == EFI_HOB_TYPE_GUID_EXTENSION) {
> + if (CompareGuid (&Hob.Guid->Name, &gEfiSmmSmramMemoryGuid)) {
> + SmramHobDescriptorBlock = (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK
> *) (Hob.Guid + 1);
> + for (Index = 0; Index < SmramHobDescriptorBlock-
> >NumberOfSmmReservedRegions; Index++) {
> + if (SmramHobDescriptorBlock->Descriptor[Index].PhysicalStart >
> 0x100000) {
> + SmramSize += SmramHobDescriptorBlock-
> >Descriptor[Index].PhysicalSize;
> + if (SmramBase == 0 || SmramBase > SmramHobDescriptorBlock-
> >Descriptor[Index].CpuStart) {
> + SmramBase = SmramHobDescriptorBlock-
> >Descriptor[Index].CpuStart;
> + }
> + }
> + }
> + break;
> + }
> + }
> + Hob.Raw = GET_NEXT_HOB (Hob);
> + }
> +
> + //
> + // Set non system memory as UC
> + //
> + MemoryBase = 0x100000000;
> +
> + //
> + // Add IED size to set whole SMRAM as WB to save MTRR count //
> + MemoryLength = MemoryBase - (SmramBase + SmramSize); while
> + (MemoryLength != 0) {
> + Power2Length = GetPowerOfTwo64 (MemoryLength);
> + MemoryBase -= Power2Length;
> + Status = MtrrSetMemoryAttributeInMtrrSettings (
> + &MtrrSetting,
> + MemoryBase,
> + Power2Length,
> + CacheUncacheable
> + );
> + ASSERT_EFI_ERROR (Status);
> + MemoryLength -= Power2Length;
> + }
> +
> + DEBUG ((DEBUG_INFO, "PcdPciReservedMemAbove4GBLimit - 0x%lx\n",
> + PcdGet64 (PcdPciReservedMemAbove4GBLimit)));
> + DEBUG ((DEBUG_INFO, "PcdPciReservedMemAbove4GBBase - 0x%lx\n",
> + PcdGet64 (PcdPciReservedMemAbove4GBBase)));
> + if (PcdGet64 (PcdPciReservedMemAbove4GBLimit) > PcdGet64
> (PcdPciReservedMemAbove4GBBase)) {
> + Status = MtrrSetMemoryAttributeInMtrrSettings (
> + &MtrrSetting,
> + PcdGet64 (PcdPciReservedMemAbove4GBBase),
> + PcdGet64 (PcdPciReservedMemAbove4GBLimit) - PcdGet64
> (PcdPciReservedMemAbove4GBBase) + 1,
> + CacheUncacheable
> + );
> + ASSERT_EFI_ERROR ( Status);
> + }
> +
> + DEBUG ((DEBUG_INFO, "PcdPciReservedPMemAbove4GBLimit - 0x%lx\n",
> + PcdGet64 (PcdPciReservedPMemAbove4GBLimit)));
> + DEBUG ((DEBUG_INFO, "PcdPciReservedPMemAbove4GBBase - 0x%lx\n",
> + PcdGet64 (PcdPciReservedPMemAbove4GBBase)));
> + if (PcdGet64 (PcdPciReservedPMemAbove4GBLimit) > PcdGet64
> (PcdPciReservedPMemAbove4GBBase)) {
> + Status = MtrrSetMemoryAttributeInMtrrSettings (
> + &MtrrSetting,
> + PcdGet64 (PcdPciReservedPMemAbove4GBBase),
> + PcdGet64 (PcdPciReservedPMemAbove4GBLimit) - PcdGet64
> (PcdPciReservedPMemAbove4GBBase) + 1,
> + CacheUncacheable
> + );
> + ASSERT_EFI_ERROR ( Status);
> + }
> +
> + //
> + // Update MTRR setting from MTRR buffer // MtrrSetAllMtrrs
> + (&MtrrSetting);
> +
> + return Status;
> +}
> diff --git
> a/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib
> Null.c
> b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib
> Null.c
> new file mode 100644
> index 0000000000..4f40de35f4
> --- /dev/null
> +++
> b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrr
> +++ LibNull.c
> @@ -0,0 +1,37 @@
> +/** @file
> +
> +NULL instances of SetCacheMtrr library functions.
> +
> +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +#include <Uefi.h>
> +#include <Library/PcdLib.h>
> +#include <Library/DebugLib.h>
> +
> +/**
> + Set Cache Mtrr.
> +**/
> +VOID
> +EFIAPI
> +SetCacheMtrr (
> + VOID
> + )
> +{
> + return;
> +}
> +
> +/**
> + Update MTRR setting and set write back as default memory attribute.
> +
> + @retval EFI_SUCCESS The function completes successfully.
> +**/
> +EFI_STATUS
> +EFIAPI
> +SetCacheMtrrAfterEndOfPei (
> + VOID
> + )
> +{
> + return EFI_SUCCESS;
> +}
> diff --git
> a/Platform/Intel/MinPlatformPkg/Include/Library/SetCacheMtrrLib.h
> b/Platform/Intel/MinPlatformPkg/Include/Library/SetCacheMtrrLib.h
> new file mode 100644
> index 0000000000..0fb566dfcc
> --- /dev/null
> +++ b/Platform/Intel/MinPlatformPkg/Include/Library/SetCacheMtrrLib.h
> @@ -0,0 +1,34 @@
> +/** @file
> +
> +Header for SetCacheMtrr library functions.
> +
> +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef _SET_CACHE_MTRR_LIB_H_
> +#define _SET_CACHE_MTRR_LIB_H_
> +
> +/**
> + Set Cache Mtrr.
> +**/
> +VOID
> +EFIAPI
> +SetCacheMtrr (
> + VOID
> + );
> +
> +/**
> + Update MTRR setting and set write back as default memory attribute.
> +
> + @retval EFI_SUCCESS The function completes successfully.
> + @retval Others Some error occurs.
> +**/
> +EFI_STATUS
> +EFIAPI
> +SetCacheMtrrAfterEndOfPei (
> + VOID
> + );
> +
> +#endif
> diff --git
> a/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib
> .inf
> b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib
> .inf
> new file mode 100644
> index 0000000000..0cfdda414b
> --- /dev/null
> +++
> b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrr
> +++ Lib.inf
> @@ -0,0 +1,46 @@
> +## @file
> +# Component information file for Platform SetCacheMtrr Library.
> +# This library implementation is for typical platforms and may not be #
> +needed when cache MTRR will be initialized by FSP.
> +#
> +# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> # #
> +SPDX-License-Identifier: BSD-2-Clause-Patent # ##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = PeiSetCacheMtrrLib
> + FILE_GUID = 9F2A2899-3AD7-4176-9B89-33B3AC456A99
> + MODULE_TYPE = PEIM
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = SetCacheMtrrLib
> +
> +[LibraryClasses]
> + BaseLib
> + PcdLib
> + DebugLib
> + HobLib
> + MtrrLib
> + PeiServicesLib
> + BaseMemoryLib
> +
> +[Packages]
> + MinPlatformPkg/MinPlatformPkg.dec
> + MdePkg/MdePkg.dec
> + UefiCpuPkg/UefiCpuPkg.dec
> +
> +[Sources]
> + SetCacheMtrrLib.c
> +
> +[Guids]
> + gEfiSmmSmramMemoryGuid ## CONSUMES
> +
> +[Pcd]
> + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ##
> CONSUMES
> + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ##
> CONSUMES
> + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase
> ## CONSUMES
> + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit
> ##
> +CONSUMES
> + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBBase
> ##
> +CONSUMES
> + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBLimit
> ##
> +CONSUMES
> diff --git
> a/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib
> Null.inf
> b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib
> Null.inf
> new file mode 100644
> index 0000000000..433bd47331
> --- /dev/null
> +++
> b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrr
> +++ LibNull.inf
> @@ -0,0 +1,29 @@
> +## @file
> +# Component information file for Platform SetCacheMtrr Library.
> +#
> +# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> # #
> +SPDX-License-Identifier: BSD-2-Clause-Patent # ##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = BaseSetCacheMtrrLibNull
> + FILE_GUID = D1ED4CD7-AD20-4943-9192-3ABE766A9411
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = SetCacheMtrrLib
> +
> +[LibraryClasses]
> + BaseLib
> + PcdLib
> + DebugLib
> +
> +[Packages]
> + MinPlatformPkg/MinPlatformPkg.dec
> + MdePkg/MdePkg.dec
> +
> +[Sources]
> + SetCacheMtrrLibNull.c
> +
> diff --git a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> index d79f5ec1bd..a851021c0b 100644
> --- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> +++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> @@ -65,6 +65,8 @@ SecBoardInitLib|Include/Library/SecBoardInitLib.h
> TestPointLib|Include/Library/TestPointLib.h
> TestPointCheckLib|Include/Library/TestPointCheckLib.h
>
> +SetCacheMtrrLib|Include/Library/SetCacheMtrrLib.h
> +
> [PcdsFixedAtBuild, PcdsPatchableInModule]
>
>
> gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|FALSE|BOOLE
> AN|0x80000008
> @@ -204,11 +206,11 @@
> gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0|UINT32|0x90000
> 019
> gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemBase
> |0x90000000 |UINT32|0x40010043
> gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemLimit
> |0x00000000 |UINT32|0x40010044
> gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase
> |0xFFFFFFFFFFFFFFFF |UINT64|0x40010045
> - gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit
> |0x0000000000000000 |UINT64|0x40010046
> + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit
> + |0x0000000000000000 |UINT64|0x40010046
> gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemBase
> |0xFFFFFFFF |UINT32|0x40010047
> gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemLimit
> |0x00000000 |UINT32|0x40010048
> gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBBase
> |0xFFFFFFFFFFFFFFFF |UINT64|0x40010049
> -
> gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBLimit|0x
> 0000000000000000 |UINT64|0x4001004A
> +
> +
> gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBLimit|0x
> 000000
> + 0000000000 |UINT64|0x4001004A
> gMinPlatformPkgTokenSpaceGuid.PcdPciDmaAbove4G
> |FALSE|BOOLEAN|0x4001004B
> gMinPlatformPkgTokenSpaceGuid.PcdPciNoExtendedConfigSpace
> |FALSE|BOOLEAN|0x4001004C
> gMinPlatformPkgTokenSpaceGuid.PcdPciResourceAssigned
> |FALSE|BOOLEAN|0x4001004D
> --
> 2.13.3.windows.1
>
>
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [edk2-platforms: PATCH v3 6/6] SimicsOpenBoardPkg/BoardX58Ich10: Add SetCacheMtrrLib library class.
2019-10-31 10:28 ` [edk2-platforms: PATCH v3 6/6] SimicsOpenBoardPkg/BoardX58Ich10: " Chiu, Chasel
@ 2019-10-31 19:42 ` Agyeman, Prince
2019-11-01 18:29 ` [edk2-devel] " Nate DeSimone
1 sibling, 0 replies; 16+ messages in thread
From: Agyeman, Prince @ 2019-10-31 19:42 UTC (permalink / raw)
To: Chiu, Chasel, devel@edk2.groups.io; +Cc: Wei, David Y
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
-----Original Message-----
From: Chiu, Chasel <chasel.chiu@intel.com>
Sent: Thursday, October 31, 2019 3:28 AM
To: devel@edk2.groups.io
Cc: Wei, David Y <david.y.wei@intel.com>; Agyeman, Prince <prince.agyeman@intel.com>
Subject: [edk2-platforms: PATCH v3 6/6] SimicsOpenBoardPkg/BoardX58Ich10: Add SetCacheMtrrLib library class.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2314
Include SetCacheMtrrLib from MinPlatformPkg.
Cc: Wei David Y <david.y.wei@intel.com>
Cc: Agyeman Prince <prince.agyeman@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc | 1 +
1 file changed, 1 insertion(+)
diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc
index 4f8ab4170d..8cad7b5b69 100644
--- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc
+++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc
@@ -136,6 +136,7 @@
TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf
!endif
TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPointLib.inf
+ SetCacheMtrrLib|$(PLATFORM_PACKAGE)/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
[LibraryClasses.common.DXE_DRIVER]
#######################################
--
2.13.3.windows.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [edk2-devel] [edk2-platforms: PATCH v3 1/6] MinPlatformPkg: Add SetCacheMtrrLib library class.
2019-10-31 17:02 ` [edk2-devel] " Kubacki, Michael A
@ 2019-11-01 1:24 ` Chiu, Chasel
0 siblings, 0 replies; 16+ messages in thread
From: Chiu, Chasel @ 2019-11-01 1:24 UTC (permalink / raw)
To: Kubacki, Michael A, devel@edk2.groups.io
Cc: Desimone, Nathaniel L, Gao, Liming
Thanks Michael!
I will update function description.
> -----Original Message-----
> From: Kubacki, Michael A <michael.a.kubacki@intel.com>
> Sent: Friday, November 1, 2019 1:02 AM
> To: devel@edk2.groups.io; Chiu, Chasel <chasel.chiu@intel.com>
> Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Gao, Liming
> <liming.gao@intel.com>
> Subject: RE: [edk2-devel] [edk2-platforms: PATCH v3 1/6] MinPlatformPkg:
> Add SetCacheMtrrLib library class.
>
> Thanks for updating the name.
>
> Platform\Intel\MinPlatformPkg\Include\Library\SetCacheMtrrLib.h:
> * The function description for SetCacheMtrrAfterEndOfPei () is
> constraining the implementation in a way that I don't believe
> is required:
> /**
> Update MTRR setting and set write back as default memory attribute.
>
> @retval EFI_SUCCESS The function completes successfully.
> @retval Others Some error occurs.
> **/
>
> While it is typical to set the default memory type to WB, I don't
> think this API should care whether that is the case.
>
> * "SetCacheMtrrAtEndOfPei ()" better describes the way this
> is actually being used but I don't think it is a must change.
>
> With the function description updated:
> Reviewed-by: Michael Kubacki <michael.a.kubacki@intel.com>
>
> > -----Original Message-----
> > From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Chiu,
> > Chasel
> > Sent: Thursday, October 31, 2019 3:28 AM
> > To: devel@edk2.groups.io
> > Cc: Kubacki, Michael A <michael.a.kubacki@intel.com>; Desimone,
> > Nathaniel L <nathaniel.l.desimone@intel.com>; Gao, Liming
> > <liming.gao@intel.com>
> > Subject: [edk2-devel] [edk2-platforms: PATCH v3 1/6] MinPlatformPkg:
> > Add SetCacheMtrrLib library class.
> >
> > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2314
> >
> > MinPlatformPkg should contain the library class header (API) and the
> > NULL library class instance.
> >
> > Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> > Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> > Cc: Liming Gao <liming.gao@intel.com>
> > Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
> > ---
> >
> > Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.
> > c
> > | 327
> > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> > +++++++++++++++++++++++++++++++++++++
> >
> > Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLibN
> > ull.c | 37 +++++++++++++++++++++++++++++++++++++
> > Platform/Intel/MinPlatformPkg/Include/Library/SetCacheMtrrLib.h
> |
> > 34 ++++++++++++++++++++++++++++++++++
> >
> >
> Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.in
> > f | 46 ++++++++++++++++++++++++++++++++++++++++++++++
> >
> > Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLibN
> > ull.inf | 29 +++++++++++++++++++++++++++++
> > Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> | 6
> > ++++--
> > 6 files changed, 477 insertions(+), 2 deletions(-)
> >
> > diff --git
> > a/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLi
> > b
> > .c
> > b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLi
> > b
> > .c
> > new file mode 100644
> > index 0000000000..26f06321f7
> > --- /dev/null
> > +++
> > b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrr
> > +++ Lib.c
> > @@ -0,0 +1,327 @@
> > +/** @file
> > +
> > +SetCacheMtrr library functions.
> > +This implementation is for typical platforms and may not be needed
> > +when cache MTRR will be initialized by FSP.
> > +
> > +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> > +SPDX-License-Identifier: BSD-2-Clause-Patent
> > +
> > +**/
> > +
> > +#include <Uefi.h>
> > +#include <PiPei.h>
> > +#include <Library/HobLib.h>
> > +#include <Library/PcdLib.h>
> > +#include <Library/DebugLib.h>
> > +#include <Library/BaseMemoryLib.h>
> > +#include <Library/MtrrLib.h>
> > +#include <Library/PeiServicesLib.h>
> > +#include <Guid/SmramMemoryReserve.h>
> > +
> > +/**
> > + Set Cache Mtrr.
> > +**/
> > +VOID
> > +EFIAPI
> > +SetCacheMtrr (
> > + VOID
> > + )
> > +{
> > + EFI_STATUS Status;
> > + EFI_PEI_HOB_POINTERS Hob;
> > + MTRR_SETTINGS MtrrSetting;
> > + UINT64 MemoryBase;
> > + UINT64 MemoryLength;
> > + UINT64 LowMemoryLength;
> > + UINT64 HighMemoryLength;
> > + EFI_BOOT_MODE BootMode;
> > + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;
> > + UINT64 CacheMemoryLength;
> > +
> > + ///
> > + /// Reset all MTRR setting.
> > + ///
> > + ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS));
> > +
> > + ///
> > + /// Cache the Flash area as WP to boost performance /// Status =
> > + MtrrSetMemoryAttributeInMtrrSettings (
> > + &MtrrSetting,
> > + (UINTN) PcdGet32 (PcdFlashAreaBaseAddress),
> > + (UINTN) PcdGet32 (PcdFlashAreaSize),
> > + CacheWriteProtected
> > + );
> > + ASSERT_EFI_ERROR (Status);
> > +
> > + ///
> > + /// Update MTRR setting from MTRR buffer for Flash Region to be WP
> > + to boost performance /// MtrrSetAllMtrrs (&MtrrSetting);
> > +
> > + ///
> > + /// Set low to 1 MB. Since 1MB cacheability will always be set ///
> > + until override by CSM.
> > + /// Initialize high memory to 0.
> > + ///
> > + LowMemoryLength = 0x100000;
> > + HighMemoryLength = 0;
> > + ResourceAttribute = (
> > + EFI_RESOURCE_ATTRIBUTE_PRESENT |
> > + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> > + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
> > +
> EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
> > +
> EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
> > +
> EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
> > + );
> > +
> > + Status = PeiServicesGetBootMode (&BootMode); ASSERT_EFI_ERROR
> > + (Status);
> > +
> > + if (BootMode != BOOT_ON_S3_RESUME) {
> > + ResourceAttribute |= EFI_RESOURCE_ATTRIBUTE_TESTED; }
> > +
> > + Status = PeiServicesGetHobList ((VOID **) &Hob.Raw); while
> > + (!END_OF_HOB_LIST (Hob)) {
> > + if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR)
> {
> > + if ((Hob.ResourceDescriptor->ResourceType ==
> > EFI_RESOURCE_SYSTEM_MEMORY) ||
> > + ((Hob.ResourceDescriptor->ResourceType ==
> > EFI_RESOURCE_MEMORY_RESERVED) &&
> > + (Hob.ResourceDescriptor->ResourceAttribute ==
> ResourceAttribute))
> > + ) {
> > + if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000000ULL) {
> > + HighMemoryLength +=
> Hob.ResourceDescriptor->ResourceLength;
> > + } else if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000) {
> > + LowMemoryLength +=
> Hob.ResourceDescriptor->ResourceLength;
> > + }
> > + }
> > + }
> > +
> > + Hob.Raw = GET_NEXT_HOB (Hob);
> > + }
> > +
> > + DEBUG ((DEBUG_INFO, "Memory Length (Below 4GB) = %lx.\n",
> > + LowMemoryLength)); DEBUG ((DEBUG_INFO, "Memory Length (Above
> > 4GB) =
> > + %lx.\n", HighMemoryLength));
> > +
> > + ///
> > + /// Assume size of main memory is multiple of 256MB ///
> > + MemoryLength = (LowMemoryLength + 0xFFFFFFF) & 0xF0000000;
> > MemoryBase
> > + = 0;
> > +
> > + CacheMemoryLength = MemoryLength;
> > + ///
> > + /// Programming MTRRs to avoid override SPI region with UC when
> MAX
> > + TOLUD Length >= 3.5GB /// if (MemoryLength > 0xDC000000) {
> > + CacheMemoryLength = 0xC0000000;
> > + Status = MtrrSetMemoryAttributeInMtrrSettings (
> > + &MtrrSetting,
> > + MemoryBase,
> > + CacheMemoryLength,
> > + CacheWriteBack
> > + );
> > + ASSERT_EFI_ERROR (Status);
> > +
> > + MemoryBase = 0xC0000000;
> > + CacheMemoryLength = MemoryLength - 0xC0000000;
> > + if (MemoryLength > 0xE0000000) {
> > + CacheMemoryLength = 0x20000000;
> > + Status = MtrrSetMemoryAttributeInMtrrSettings (
> > + &MtrrSetting,
> > + MemoryBase,
> > + CacheMemoryLength,
> > + CacheWriteBack
> > + );
> > + ASSERT_EFI_ERROR (Status);
> > +
> > + MemoryBase = 0xE0000000;
> > + CacheMemoryLength = MemoryLength - 0xE0000000;
> > + }
> > + }
> > +
> > + Status = MtrrSetMemoryAttributeInMtrrSettings (
> > + &MtrrSetting,
> > + MemoryBase,
> > + CacheMemoryLength,
> > + CacheWriteBack
> > + );
> > + ASSERT_EFI_ERROR (Status);
> > +
> > + if (LowMemoryLength != MemoryLength) {
> > + MemoryBase = LowMemoryLength;
> > + MemoryLength -= LowMemoryLength;
> > + Status = MtrrSetMemoryAttributeInMtrrSettings (
> > + &MtrrSetting,
> > + MemoryBase,
> > + MemoryLength,
> > + CacheUncacheable
> > + );
> > + ASSERT_EFI_ERROR (Status);
> > + }
> > +
> > + ///
> > + /// VGA-MMIO - 0xA0000 to 0xC0000 to be UC /// Status =
> > + MtrrSetMemoryAttributeInMtrrSettings (
> > + &MtrrSetting,
> > + 0xA0000,
> > + 0x20000,
> > + CacheUncacheable
> > + );
> > + ASSERT_EFI_ERROR (Status);
> > +
> > + ///
> > + /// Update MTRR setting from MTRR buffer /// MtrrSetAllMtrrs
> > + (&MtrrSetting);
> > +
> > + return ;
> > +}
> > +
> > +/**
> > + Update MTRR setting and set write back as default memory attribute.
> > +
> > + @retval EFI_SUCCESS The function completes successfully.
> > + @retval Others Some error occurs.
> > +**/
> > +EFI_STATUS
> > +EFIAPI
> > +SetCacheMtrrAfterEndOfPei (
> > + VOID
> > + )
> > +{
> > + EFI_STATUS Status;
> > + MTRR_SETTINGS MtrrSetting;
> > + EFI_PEI_HOB_POINTERS Hob;
> > + UINT64 MemoryBase;
> > + UINT64 MemoryLength;
> > + UINT64 Power2Length;
> > + EFI_BOOT_MODE BootMode;
> > + UINTN Index;
> > + UINT64 SmramSize;
> > + UINT64 SmramBase;
> > + EFI_SMRAM_HOB_DESCRIPTOR_BLOCK
> *SmramHobDescriptorBlock;
> > + Status = PeiServicesGetBootMode (&BootMode);
> > + ASSERT_EFI_ERROR (Status);
> > +
> > + if (BootMode == BOOT_ON_S3_RESUME) {
> > + return EFI_SUCCESS;
> > + }
> > + //
> > + // Clear the CAR Settings
> > + //
> > + ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS));
> > +
> > + //
> > + // Default Cachable attribute will be set to WB to support large
> > + memory size/hot plug memory // MtrrSetting.MtrrDefType &=
> > + ~((UINT64)(0xFF)); MtrrSetting.MtrrDefType |= (UINT64)
> > + CacheWriteBack;
> > +
> > + //
> > + // Set fixed cache for memory range below 1MB // Status =
> > + MtrrSetMemoryAttributeInMtrrSettings (
> > + &MtrrSetting,
> > + 0x0,
> > + 0xA0000,
> > + CacheWriteBack
> > + );
> > + ASSERT_EFI_ERROR (Status);
> > +
> > + Status = MtrrSetMemoryAttributeInMtrrSettings (
> > + &MtrrSetting,
> > + 0xA0000,
> > + 0x20000,
> > + CacheUncacheable
> > + );
> > + ASSERT_EFI_ERROR (Status);
> > +
> > + Status = MtrrSetMemoryAttributeInMtrrSettings (
> > + &MtrrSetting,
> > + 0xC0000,
> > + 0x40000,
> > + CacheWriteProtected
> > + );
> > + ASSERT_EFI_ERROR ( Status);
> > +
> > + //
> > + // PI SMM IPL can't set SMRAM to WB because at that time CPU ARCH
> > protocol is not available.
> > + // Set cacheability of SMRAM to WB here to improve SMRAM
> > + initialization
> > performance.
> > + //
> > + SmramSize = 0;
> > + SmramBase = 0;
> > + Status = PeiServicesGetHobList ((VOID **) &Hob.Raw); while
> > + (!END_OF_HOB_LIST (Hob)) {
> > + if (Hob.Header->HobType == EFI_HOB_TYPE_GUID_EXTENSION) {
> > + if (CompareGuid (&Hob.Guid->Name,
> &gEfiSmmSmramMemoryGuid)) {
> > + SmramHobDescriptorBlock =
> (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK
> > *) (Hob.Guid + 1);
> > + for (Index = 0; Index < SmramHobDescriptorBlock-
> > >NumberOfSmmReservedRegions; Index++) {
> > + if
> > + (SmramHobDescriptorBlock->Descriptor[Index].PhysicalStart >
> > 0x100000) {
> > + SmramSize += SmramHobDescriptorBlock-
> > >Descriptor[Index].PhysicalSize;
> > + if (SmramBase == 0 || SmramBase >
> > + SmramHobDescriptorBlock-
> > >Descriptor[Index].CpuStart) {
> > + SmramBase = SmramHobDescriptorBlock-
> > >Descriptor[Index].CpuStart;
> > + }
> > + }
> > + }
> > + break;
> > + }
> > + }
> > + Hob.Raw = GET_NEXT_HOB (Hob);
> > + }
> > +
> > + //
> > + // Set non system memory as UC
> > + //
> > + MemoryBase = 0x100000000;
> > +
> > + //
> > + // Add IED size to set whole SMRAM as WB to save MTRR count //
> > + MemoryLength = MemoryBase - (SmramBase + SmramSize); while
> > + (MemoryLength != 0) {
> > + Power2Length = GetPowerOfTwo64 (MemoryLength);
> > + MemoryBase -= Power2Length;
> > + Status = MtrrSetMemoryAttributeInMtrrSettings (
> > + &MtrrSetting,
> > + MemoryBase,
> > + Power2Length,
> > + CacheUncacheable
> > + );
> > + ASSERT_EFI_ERROR (Status);
> > + MemoryLength -= Power2Length;
> > + }
> > +
> > + DEBUG ((DEBUG_INFO, "PcdPciReservedMemAbove4GBLimit - 0x%lx\n",
> > + PcdGet64 (PcdPciReservedMemAbove4GBLimit)));
> > + DEBUG ((DEBUG_INFO, "PcdPciReservedMemAbove4GBBase - 0x%lx\n",
> > + PcdGet64 (PcdPciReservedMemAbove4GBBase)));
> > + if (PcdGet64 (PcdPciReservedMemAbove4GBLimit) > PcdGet64
> > (PcdPciReservedMemAbove4GBBase)) {
> > + Status = MtrrSetMemoryAttributeInMtrrSettings (
> > + &MtrrSetting,
> > + PcdGet64
> (PcdPciReservedMemAbove4GBBase),
> > + PcdGet64
> (PcdPciReservedMemAbove4GBLimit)
> > + - PcdGet64
> > (PcdPciReservedMemAbove4GBBase) + 1,
> > + CacheUncacheable
> > + );
> > + ASSERT_EFI_ERROR ( Status);
> > + }
> > +
> > + DEBUG ((DEBUG_INFO, "PcdPciReservedPMemAbove4GBLimit -
> 0x%lx\n",
> > + PcdGet64 (PcdPciReservedPMemAbove4GBLimit)));
> > + DEBUG ((DEBUG_INFO, "PcdPciReservedPMemAbove4GBBase -
> 0x%lx\n",
> > + PcdGet64 (PcdPciReservedPMemAbove4GBBase)));
> > + if (PcdGet64 (PcdPciReservedPMemAbove4GBLimit) > PcdGet64
> > (PcdPciReservedPMemAbove4GBBase)) {
> > + Status = MtrrSetMemoryAttributeInMtrrSettings (
> > + &MtrrSetting,
> > + PcdGet64
> (PcdPciReservedPMemAbove4GBBase),
> > + PcdGet64
> (PcdPciReservedPMemAbove4GBLimit)
> > + - PcdGet64
> > (PcdPciReservedPMemAbove4GBBase) + 1,
> > + CacheUncacheable
> > + );
> > + ASSERT_EFI_ERROR ( Status);
> > + }
> > +
> > + //
> > + // Update MTRR setting from MTRR buffer // MtrrSetAllMtrrs
> > + (&MtrrSetting);
> > +
> > + return Status;
> > +}
> > diff --git
> > a/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLi
> > b
> > Null.c
> > b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLi
> > b
> > Null.c
> > new file mode 100644
> > index 0000000000..4f40de35f4
> > --- /dev/null
> > +++
> > b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrr
> > +++ LibNull.c
> > @@ -0,0 +1,37 @@
> > +/** @file
> > +
> > +NULL instances of SetCacheMtrr library functions.
> > +
> > +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> > +SPDX-License-Identifier: BSD-2-Clause-Patent
> > +
> > +**/
> > +#include <Uefi.h>
> > +#include <Library/PcdLib.h>
> > +#include <Library/DebugLib.h>
> > +
> > +/**
> > + Set Cache Mtrr.
> > +**/
> > +VOID
> > +EFIAPI
> > +SetCacheMtrr (
> > + VOID
> > + )
> > +{
> > + return;
> > +}
> > +
> > +/**
> > + Update MTRR setting and set write back as default memory attribute.
> > +
> > + @retval EFI_SUCCESS The function completes successfully.
> > +**/
> > +EFI_STATUS
> > +EFIAPI
> > +SetCacheMtrrAfterEndOfPei (
> > + VOID
> > + )
> > +{
> > + return EFI_SUCCESS;
> > +}
> > diff --git
> > a/Platform/Intel/MinPlatformPkg/Include/Library/SetCacheMtrrLib.h
> > b/Platform/Intel/MinPlatformPkg/Include/Library/SetCacheMtrrLib.h
> > new file mode 100644
> > index 0000000000..0fb566dfcc
> > --- /dev/null
> > +++ b/Platform/Intel/MinPlatformPkg/Include/Library/SetCacheMtrrLib.h
> > @@ -0,0 +1,34 @@
> > +/** @file
> > +
> > +Header for SetCacheMtrr library functions.
> > +
> > +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> > +SPDX-License-Identifier: BSD-2-Clause-Patent
> > +
> > +**/
> > +
> > +#ifndef _SET_CACHE_MTRR_LIB_H_
> > +#define _SET_CACHE_MTRR_LIB_H_
> > +
> > +/**
> > + Set Cache Mtrr.
> > +**/
> > +VOID
> > +EFIAPI
> > +SetCacheMtrr (
> > + VOID
> > + );
> > +
> > +/**
> > + Update MTRR setting and set write back as default memory attribute.
> > +
> > + @retval EFI_SUCCESS The function completes successfully.
> > + @retval Others Some error occurs.
> > +**/
> > +EFI_STATUS
> > +EFIAPI
> > +SetCacheMtrrAfterEndOfPei (
> > + VOID
> > + );
> > +
> > +#endif
> > diff --git
> > a/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLi
> > b
> > .inf
> > b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLi
> > b
> > .inf
> > new file mode 100644
> > index 0000000000..0cfdda414b
> > --- /dev/null
> > +++
> > b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrr
> > +++ Lib.inf
> > @@ -0,0 +1,46 @@
> > +## @file
> > +# Component information file for Platform SetCacheMtrr Library.
> > +# This library implementation is for typical platforms and may not be
> > +# needed when cache MTRR will be initialized by FSP.
> > +#
> > +# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> # #
> > +SPDX-License-Identifier: BSD-2-Clause-Patent # ##
> > +
> > +[Defines]
> > + INF_VERSION = 0x00010005
> > + BASE_NAME = PeiSetCacheMtrrLib
> > + FILE_GUID =
> 9F2A2899-3AD7-4176-9B89-33B3AC456A99
> > + MODULE_TYPE = PEIM
> > + VERSION_STRING = 1.0
> > + LIBRARY_CLASS = SetCacheMtrrLib
> > +
> > +[LibraryClasses]
> > + BaseLib
> > + PcdLib
> > + DebugLib
> > + HobLib
> > + MtrrLib
> > + PeiServicesLib
> > + BaseMemoryLib
> > +
> > +[Packages]
> > + MinPlatformPkg/MinPlatformPkg.dec
> > + MdePkg/MdePkg.dec
> > + UefiCpuPkg/UefiCpuPkg.dec
> > +
> > +[Sources]
> > + SetCacheMtrrLib.c
> > +
> > +[Guids]
> > + gEfiSmmSmramMemoryGuid ##
> CONSUMES
> > +
> > +[Pcd]
> > + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
> ##
> > CONSUMES
> > + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize
> ##
> > CONSUMES
> > + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase
> > ## CONSUMES
> > + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit
> > ##
> > +CONSUMES
> > + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBBase
> > ##
> > +CONSUMES
> > + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBLimit
> > ##
> > +CONSUMES
> > diff --git
> > a/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLi
> > b
> > Null.inf
> > b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLi
> > b
> > Null.inf
> > new file mode 100644
> > index 0000000000..433bd47331
> > --- /dev/null
> > +++
> > b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrr
> > +++ LibNull.inf
> > @@ -0,0 +1,29 @@
> > +## @file
> > +# Component information file for Platform SetCacheMtrr Library.
> > +#
> > +# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> # #
> > +SPDX-License-Identifier: BSD-2-Clause-Patent # ##
> > +
> > +[Defines]
> > + INF_VERSION = 0x00010005
> > + BASE_NAME = BaseSetCacheMtrrLibNull
> > + FILE_GUID =
> D1ED4CD7-AD20-4943-9192-3ABE766A9411
> > + MODULE_TYPE = BASE
> > + VERSION_STRING = 1.0
> > + LIBRARY_CLASS = SetCacheMtrrLib
> > +
> > +[LibraryClasses]
> > + BaseLib
> > + PcdLib
> > + DebugLib
> > +
> > +[Packages]
> > + MinPlatformPkg/MinPlatformPkg.dec
> > + MdePkg/MdePkg.dec
> > +
> > +[Sources]
> > + SetCacheMtrrLibNull.c
> > +
> > diff --git a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> > b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> > index d79f5ec1bd..a851021c0b 100644
> > --- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> > +++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> > @@ -65,6 +65,8 @@ SecBoardInitLib|Include/Library/SecBoardInitLib.h
> > TestPointLib|Include/Library/TestPointLib.h
> > TestPointCheckLib|Include/Library/TestPointCheckLib.h
> >
> > +SetCacheMtrrLib|Include/Library/SetCacheMtrrLib.h
> > +
> > [PcdsFixedAtBuild, PcdsPatchableInModule]
> >
> >
> > gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|FALSE|BOOLE
> > AN|0x80000008
> > @@ -204,11 +206,11 @@
> > gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0|UINT32|0x90000
> > 019
> > gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemBase
> > |0x90000000 |UINT32|0x40010043
> > gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemLimit
> > |0x00000000 |UINT32|0x40010044
> > gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase
> > |0xFFFFFFFFFFFFFFFF |UINT64|0x40010045
> > - gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit
> > |0x0000000000000000 |UINT64|0x40010046
> > + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit
> > + |0x0000000000000000 |UINT64|0x40010046
> > gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemBase
> > |0xFFFFFFFF |UINT32|0x40010047
> > gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemLimit
> > |0x00000000 |UINT32|0x40010048
> > gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBBase
> > |0xFFFFFFFFFFFFFFFF |UINT64|0x40010049
> > -
> > gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBLimit|0x
> > 0000000000000000 |UINT64|0x4001004A
> > +
> > +
> > gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBLimit|0x
> > 000000
> > + 0000000000 |UINT64|0x4001004A
> > gMinPlatformPkgTokenSpaceGuid.PcdPciDmaAbove4G
> > |FALSE|BOOLEAN|0x4001004B
> > gMinPlatformPkgTokenSpaceGuid.PcdPciNoExtendedConfigSpace
> > |FALSE|BOOLEAN|0x4001004C
> > gMinPlatformPkgTokenSpaceGuid.PcdPciResourceAssigned
> > |FALSE|BOOLEAN|0x4001004D
> > --
> > 2.13.3.windows.1
> >
> >
> >
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [edk2-devel] [edk2-platforms: PATCH v3 1/6] MinPlatformPkg: Add SetCacheMtrrLib library class.
2019-10-31 10:28 ` [edk2-platforms: PATCH v3 1/6] MinPlatformPkg: " Chiu, Chasel
2019-10-31 17:02 ` [edk2-devel] " Kubacki, Michael A
@ 2019-11-01 18:29 ` Nate DeSimone
1 sibling, 0 replies; 16+ messages in thread
From: Nate DeSimone @ 2019-11-01 18:29 UTC (permalink / raw)
To: devel@edk2.groups.io, Chiu, Chasel; +Cc: Kubacki, Michael A, Gao, Liming
With Michael's comments addressed...
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Chiu, Chasel
Sent: Thursday, October 31, 2019 3:28 AM
To: devel@edk2.groups.io
Cc: Kubacki, Michael A <michael.a.kubacki@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Gao, Liming <liming.gao@intel.com>
Subject: [edk2-devel] [edk2-platforms: PATCH v3 1/6] MinPlatformPkg: Add SetCacheMtrrLib library class.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2314
MinPlatformPkg should contain the library class header (API) and the NULL library class instance.
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c | 327 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLibNull.c | 37 +++++++++++++++++++++++++++++++++++++
Platform/Intel/MinPlatformPkg/Include/Library/SetCacheMtrrLib.h | 34 ++++++++++++++++++++++++++++++++++
Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf | 46 ++++++++++++++++++++++++++++++++++++++++++++++
Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLibNull.inf | 29 +++++++++++++++++++++++++++++
Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec | 6 ++++--
6 files changed, 477 insertions(+), 2 deletions(-)
diff --git a/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c
new file mode 100644
index 0000000000..26f06321f7
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrr
+++ Lib.c
@@ -0,0 +1,327 @@
+/** @file
+
+SetCacheMtrr library functions.
+This implementation is for typical platforms and may not be needed when
+cache MTRR will be initialized by FSP.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <PiPei.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MtrrLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Guid/SmramMemoryReserve.h>
+
+/**
+ Set Cache Mtrr.
+**/
+VOID
+EFIAPI
+SetCacheMtrr (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_HOB_POINTERS Hob;
+ MTRR_SETTINGS MtrrSetting;
+ UINT64 MemoryBase;
+ UINT64 MemoryLength;
+ UINT64 LowMemoryLength;
+ UINT64 HighMemoryLength;
+ EFI_BOOT_MODE BootMode;
+ EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;
+ UINT64 CacheMemoryLength;
+
+ ///
+ /// Reset all MTRR setting.
+ ///
+ ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS));
+
+ ///
+ /// Cache the Flash area as WP to boost performance /// Status =
+ MtrrSetMemoryAttributeInMtrrSettings (
+ &MtrrSetting,
+ (UINTN) PcdGet32 (PcdFlashAreaBaseAddress),
+ (UINTN) PcdGet32 (PcdFlashAreaSize),
+ CacheWriteProtected
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ ///
+ /// Update MTRR setting from MTRR buffer for Flash Region to be WP to
+ boost performance /// MtrrSetAllMtrrs (&MtrrSetting);
+
+ ///
+ /// Set low to 1 MB. Since 1MB cacheability will always be set ///
+ until override by CSM.
+ /// Initialize high memory to 0.
+ ///
+ LowMemoryLength = 0x100000;
+ HighMemoryLength = 0;
+ ResourceAttribute = (
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
+ );
+
+ Status = PeiServicesGetBootMode (&BootMode); ASSERT_EFI_ERROR
+ (Status);
+
+ if (BootMode != BOOT_ON_S3_RESUME) {
+ ResourceAttribute |= EFI_RESOURCE_ATTRIBUTE_TESTED; }
+
+ Status = PeiServicesGetHobList ((VOID **) &Hob.Raw); while
+ (!END_OF_HOB_LIST (Hob)) {
+ if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {
+ if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) ||
+ ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) &&
+ (Hob.ResourceDescriptor->ResourceAttribute == ResourceAttribute))
+ ) {
+ if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000000ULL) {
+ HighMemoryLength += Hob.ResourceDescriptor->ResourceLength;
+ } else if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000) {
+ LowMemoryLength += Hob.ResourceDescriptor->ResourceLength;
+ }
+ }
+ }
+
+ Hob.Raw = GET_NEXT_HOB (Hob);
+ }
+
+ DEBUG ((DEBUG_INFO, "Memory Length (Below 4GB) = %lx.\n",
+ LowMemoryLength)); DEBUG ((DEBUG_INFO, "Memory Length (Above 4GB) =
+ %lx.\n", HighMemoryLength));
+
+ ///
+ /// Assume size of main memory is multiple of 256MB ///
+ MemoryLength = (LowMemoryLength + 0xFFFFFFF) & 0xF0000000; MemoryBase
+ = 0;
+
+ CacheMemoryLength = MemoryLength;
+ ///
+ /// Programming MTRRs to avoid override SPI region with UC when MAX
+ TOLUD Length >= 3.5GB /// if (MemoryLength > 0xDC000000) {
+ CacheMemoryLength = 0xC0000000;
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ &MtrrSetting,
+ MemoryBase,
+ CacheMemoryLength,
+ CacheWriteBack
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ MemoryBase = 0xC0000000;
+ CacheMemoryLength = MemoryLength - 0xC0000000;
+ if (MemoryLength > 0xE0000000) {
+ CacheMemoryLength = 0x20000000;
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ &MtrrSetting,
+ MemoryBase,
+ CacheMemoryLength,
+ CacheWriteBack
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ MemoryBase = 0xE0000000;
+ CacheMemoryLength = MemoryLength - 0xE0000000;
+ }
+ }
+
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ &MtrrSetting,
+ MemoryBase,
+ CacheMemoryLength,
+ CacheWriteBack
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ if (LowMemoryLength != MemoryLength) {
+ MemoryBase = LowMemoryLength;
+ MemoryLength -= LowMemoryLength;
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ &MtrrSetting,
+ MemoryBase,
+ MemoryLength,
+ CacheUncacheable
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
+
+ ///
+ /// VGA-MMIO - 0xA0000 to 0xC0000 to be UC /// Status =
+ MtrrSetMemoryAttributeInMtrrSettings (
+ &MtrrSetting,
+ 0xA0000,
+ 0x20000,
+ CacheUncacheable
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ ///
+ /// Update MTRR setting from MTRR buffer /// MtrrSetAllMtrrs
+ (&MtrrSetting);
+
+ return ;
+}
+
+/**
+ Update MTRR setting and set write back as default memory attribute.
+
+ @retval EFI_SUCCESS The function completes successfully.
+ @retval Others Some error occurs.
+**/
+EFI_STATUS
+EFIAPI
+SetCacheMtrrAfterEndOfPei (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ MTRR_SETTINGS MtrrSetting;
+ EFI_PEI_HOB_POINTERS Hob;
+ UINT64 MemoryBase;
+ UINT64 MemoryLength;
+ UINT64 Power2Length;
+ EFI_BOOT_MODE BootMode;
+ UINTN Index;
+ UINT64 SmramSize;
+ UINT64 SmramBase;
+ EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock;
+ Status = PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+
+ if (BootMode == BOOT_ON_S3_RESUME) {
+ return EFI_SUCCESS;
+ }
+ //
+ // Clear the CAR Settings
+ //
+ ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS));
+
+ //
+ // Default Cachable attribute will be set to WB to support large
+ memory size/hot plug memory // MtrrSetting.MtrrDefType &=
+ ~((UINT64)(0xFF)); MtrrSetting.MtrrDefType |= (UINT64)
+ CacheWriteBack;
+
+ //
+ // Set fixed cache for memory range below 1MB // Status =
+ MtrrSetMemoryAttributeInMtrrSettings (
+ &MtrrSetting,
+ 0x0,
+ 0xA0000,
+ CacheWriteBack
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ &MtrrSetting,
+ 0xA0000,
+ 0x20000,
+ CacheUncacheable
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ &MtrrSetting,
+ 0xC0000,
+ 0x40000,
+ CacheWriteProtected
+ );
+ ASSERT_EFI_ERROR ( Status);
+
+ //
+ // PI SMM IPL can't set SMRAM to WB because at that time CPU ARCH protocol is not available.
+ // Set cacheability of SMRAM to WB here to improve SMRAM initialization performance.
+ //
+ SmramSize = 0;
+ SmramBase = 0;
+ Status = PeiServicesGetHobList ((VOID **) &Hob.Raw); while
+ (!END_OF_HOB_LIST (Hob)) {
+ if (Hob.Header->HobType == EFI_HOB_TYPE_GUID_EXTENSION) {
+ if (CompareGuid (&Hob.Guid->Name, &gEfiSmmSmramMemoryGuid)) {
+ SmramHobDescriptorBlock = (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *) (Hob.Guid + 1);
+ for (Index = 0; Index < SmramHobDescriptorBlock->NumberOfSmmReservedRegions; Index++) {
+ if (SmramHobDescriptorBlock->Descriptor[Index].PhysicalStart > 0x100000) {
+ SmramSize += SmramHobDescriptorBlock->Descriptor[Index].PhysicalSize;
+ if (SmramBase == 0 || SmramBase > SmramHobDescriptorBlock->Descriptor[Index].CpuStart) {
+ SmramBase = SmramHobDescriptorBlock->Descriptor[Index].CpuStart;
+ }
+ }
+ }
+ break;
+ }
+ }
+ Hob.Raw = GET_NEXT_HOB (Hob);
+ }
+
+ //
+ // Set non system memory as UC
+ //
+ MemoryBase = 0x100000000;
+
+ //
+ // Add IED size to set whole SMRAM as WB to save MTRR count //
+ MemoryLength = MemoryBase - (SmramBase + SmramSize); while
+ (MemoryLength != 0) {
+ Power2Length = GetPowerOfTwo64 (MemoryLength);
+ MemoryBase -= Power2Length;
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ &MtrrSetting,
+ MemoryBase,
+ Power2Length,
+ CacheUncacheable
+ );
+ ASSERT_EFI_ERROR (Status);
+ MemoryLength -= Power2Length;
+ }
+
+ DEBUG ((DEBUG_INFO, "PcdPciReservedMemAbove4GBLimit - 0x%lx\n",
+ PcdGet64 (PcdPciReservedMemAbove4GBLimit)));
+ DEBUG ((DEBUG_INFO, "PcdPciReservedMemAbove4GBBase - 0x%lx\n",
+ PcdGet64 (PcdPciReservedMemAbove4GBBase)));
+ if (PcdGet64 (PcdPciReservedMemAbove4GBLimit) > PcdGet64 (PcdPciReservedMemAbove4GBBase)) {
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ &MtrrSetting,
+ PcdGet64 (PcdPciReservedMemAbove4GBBase),
+ PcdGet64 (PcdPciReservedMemAbove4GBLimit) - PcdGet64 (PcdPciReservedMemAbove4GBBase) + 1,
+ CacheUncacheable
+ );
+ ASSERT_EFI_ERROR ( Status);
+ }
+
+ DEBUG ((DEBUG_INFO, "PcdPciReservedPMemAbove4GBLimit - 0x%lx\n",
+ PcdGet64 (PcdPciReservedPMemAbove4GBLimit)));
+ DEBUG ((DEBUG_INFO, "PcdPciReservedPMemAbove4GBBase - 0x%lx\n",
+ PcdGet64 (PcdPciReservedPMemAbove4GBBase)));
+ if (PcdGet64 (PcdPciReservedPMemAbove4GBLimit) > PcdGet64 (PcdPciReservedPMemAbove4GBBase)) {
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ &MtrrSetting,
+ PcdGet64 (PcdPciReservedPMemAbove4GBBase),
+ PcdGet64 (PcdPciReservedPMemAbove4GBLimit) - PcdGet64 (PcdPciReservedPMemAbove4GBBase) + 1,
+ CacheUncacheable
+ );
+ ASSERT_EFI_ERROR ( Status);
+ }
+
+ //
+ // Update MTRR setting from MTRR buffer // MtrrSetAllMtrrs
+ (&MtrrSetting);
+
+ return Status;
+}
diff --git a/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLibNull.c b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLibNull.c
new file mode 100644
index 0000000000..4f40de35f4
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrr
+++ LibNull.c
@@ -0,0 +1,37 @@
+/** @file
+
+NULL instances of SetCacheMtrr library functions.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include <Uefi.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+/**
+ Set Cache Mtrr.
+**/
+VOID
+EFIAPI
+SetCacheMtrr (
+ VOID
+ )
+{
+ return;
+}
+
+/**
+ Update MTRR setting and set write back as default memory attribute.
+
+ @retval EFI_SUCCESS The function completes successfully.
+**/
+EFI_STATUS
+EFIAPI
+SetCacheMtrrAfterEndOfPei (
+ VOID
+ )
+{
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/MinPlatformPkg/Include/Library/SetCacheMtrrLib.h b/Platform/Intel/MinPlatformPkg/Include/Library/SetCacheMtrrLib.h
new file mode 100644
index 0000000000..0fb566dfcc
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/Include/Library/SetCacheMtrrLib.h
@@ -0,0 +1,34 @@
+/** @file
+
+Header for SetCacheMtrr library functions.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _SET_CACHE_MTRR_LIB_H_
+#define _SET_CACHE_MTRR_LIB_H_
+
+/**
+ Set Cache Mtrr.
+**/
+VOID
+EFIAPI
+SetCacheMtrr (
+ VOID
+ );
+
+/**
+ Update MTRR setting and set write back as default memory attribute.
+
+ @retval EFI_SUCCESS The function completes successfully.
+ @retval Others Some error occurs.
+**/
+EFI_STATUS
+EFIAPI
+SetCacheMtrrAfterEndOfPei (
+ VOID
+ );
+
+#endif
diff --git a/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
new file mode 100644
index 0000000000..0cfdda414b
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrr
+++ Lib.inf
@@ -0,0 +1,46 @@
+## @file
+# Component information file for Platform SetCacheMtrr Library.
+# This library implementation is for typical platforms and may not be #
+needed when cache MTRR will be initialized by FSP.
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> # #
+SPDX-License-Identifier: BSD-2-Clause-Patent # ##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiSetCacheMtrrLib
+ FILE_GUID = 9F2A2899-3AD7-4176-9B89-33B3AC456A99
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SetCacheMtrrLib
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ DebugLib
+ HobLib
+ MtrrLib
+ PeiServicesLib
+ BaseMemoryLib
+
+[Packages]
+ MinPlatformPkg/MinPlatformPkg.dec
+ MdePkg/MdePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+[Sources]
+ SetCacheMtrrLib.c
+
+[Guids]
+ gEfiSmmSmramMemoryGuid ## CONSUMES
+
+[Pcd]
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit ##
+CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBBase ##
+CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBLimit ##
+CONSUMES
diff --git a/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLibNull.inf b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLibNull.inf
new file mode 100644
index 0000000000..433bd47331
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrr
+++ LibNull.inf
@@ -0,0 +1,29 @@
+## @file
+# Component information file for Platform SetCacheMtrr Library.
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> # #
+SPDX-License-Identifier: BSD-2-Clause-Patent # ##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BaseSetCacheMtrrLibNull
+ FILE_GUID = D1ED4CD7-AD20-4943-9192-3ABE766A9411
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SetCacheMtrrLib
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ DebugLib
+
+[Packages]
+ MinPlatformPkg/MinPlatformPkg.dec
+ MdePkg/MdePkg.dec
+
+[Sources]
+ SetCacheMtrrLibNull.c
+
diff --git a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
index d79f5ec1bd..a851021c0b 100644
--- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
+++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
@@ -65,6 +65,8 @@ SecBoardInitLib|Include/Library/SecBoardInitLib.h
TestPointLib|Include/Library/TestPointLib.h
TestPointCheckLib|Include/Library/TestPointCheckLib.h
+SetCacheMtrrLib|Include/Library/SetCacheMtrrLib.h
+
[PcdsFixedAtBuild, PcdsPatchableInModule]
gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|FALSE|BOOLEAN|0x80000008
@@ -204,11 +206,11 @@ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0|UINT32|0x90000019
gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemBase |0x90000000 |UINT32|0x40010043
gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemLimit |0x00000000 |UINT32|0x40010044
gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase |0xFFFFFFFFFFFFFFFF |UINT64|0x40010045
- gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit |0x0000000000000000 |UINT64|0x40010046
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit
+ |0x0000000000000000 |UINT64|0x40010046
gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemBase |0xFFFFFFFF |UINT32|0x40010047
gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemLimit |0x00000000 |UINT32|0x40010048
gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBBase |0xFFFFFFFFFFFFFFFF |UINT64|0x40010049
- gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBLimit|0x0000000000000000 |UINT64|0x4001004A
+
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBLimit|0x000000
+ 0000000000 |UINT64|0x4001004A
gMinPlatformPkgTokenSpaceGuid.PcdPciDmaAbove4G |FALSE|BOOLEAN|0x4001004B
gMinPlatformPkgTokenSpaceGuid.PcdPciNoExtendedConfigSpace |FALSE|BOOLEAN|0x4001004C
gMinPlatformPkgTokenSpaceGuid.PcdPciResourceAssigned |FALSE|BOOLEAN|0x4001004D
--
2.13.3.windows.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [edk2-devel] [edk2-platforms: PATCH v3 2/6] MinPlatformPkg: Add SetCacheMtrrLib library class.
2019-10-31 10:28 ` [edk2-platforms: PATCH v3 2/6] " Chiu, Chasel
@ 2019-11-01 18:29 ` Nate DeSimone
0 siblings, 0 replies; 16+ messages in thread
From: Nate DeSimone @ 2019-11-01 18:29 UTC (permalink / raw)
To: devel@edk2.groups.io, Chiu, Chasel; +Cc: Kubacki, Michael A, Gao, Liming
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Chiu, Chasel
Sent: Thursday, October 31, 2019 3:28 AM
To: devel@edk2.groups.io
Cc: Kubacki, Michael A <michael.a.kubacki@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Gao, Liming <liming.gao@intel.com>
Subject: [edk2-devel] [edk2-platforms: PATCH v3 2/6] MinPlatformPkg: Add SetCacheMtrrLib library class.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2314
MinPlatformPkg PlatformInit modules to consume SetCacheMtrrLib.
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.c | 151 ++-----------------------------------------------------------------------------------------------------------------------------------------------------
Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c | 164 ++------------------------------------------------------------------------------------------------------------------------------------------------------------------
Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf | 11 +----------
Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf | 7 ++-----
4 files changed, 7 insertions(+), 326 deletions(-)
diff --git a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.c b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.c
index 70e6b9a495..1b00d1dd6a 100644
--- a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.c
+++ b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/Platfor
+++ mInitPostMem.c
@@ -13,8 +13,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Library/PeiServicesLib.h> #include <IndustryStandard/Pci30.h> #include <Ppi/EndOfPeiPhase.h> -#include <Library/MtrrLib.h> -#include <Guid/SmramMemoryReserve.h>
#include <Guid/FirmwareFileSystem2.h>
#include <Protocol/FirmwareVolumeBlock.h> @@ -22,6 +20,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Library/TimerLib.h> #include <Library/BoardInitLib.h> #include <Library/TestPointCheckLib.h>
+#include <Library/SetCacheMtrrLib.h>
EFI_STATUS
EFIAPI
@@ -38,152 +37,6 @@ static EFI_PEI_NOTIFY_DESCRIPTOR mEndOfPeiNotifyList = { };
/**
- Update MTRR setting and set write back as default memory attribute.
-
- @retval EFI_SUCCESS The function completes successfully.
- @retval Others Some error occurs.
-**/
-EFI_STATUS
-EFIAPI
-SetCacheMtrrAfterEndOfPei (
- VOID
- )
-{
- EFI_STATUS Status;
- MTRR_SETTINGS MtrrSetting;
- EFI_PEI_HOB_POINTERS Hob;
- UINT64 MemoryBase;
- UINT64 MemoryLength;
- UINT64 Power2Length;
- EFI_BOOT_MODE BootMode;
- UINTN Index;
- UINT64 SmramSize;
- UINT64 SmramBase;
- EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock;
- Status = PeiServicesGetBootMode (&BootMode);
- ASSERT_EFI_ERROR (Status);
-
- if (BootMode == BOOT_ON_S3_RESUME) {
- return EFI_SUCCESS;
- }
- //
- // Clear the CAR Settings
- //
- ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS));
-
- //
- // Default Cachable attribute will be set to WB to support large memory size/hot plug memory
- //
- MtrrSetting.MtrrDefType &= ~((UINT64)(0xFF));
- MtrrSetting.MtrrDefType |= (UINT64) CacheWriteBack;
-
- //
- // Set fixed cache for memory range below 1MB
- //
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- 0x0,
- 0xA0000,
- CacheWriteBack
- );
- ASSERT_EFI_ERROR (Status);
-
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- 0xA0000,
- 0x20000,
- CacheUncacheable
- );
- ASSERT_EFI_ERROR (Status);
-
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- 0xC0000,
- 0x40000,
- CacheWriteProtected
- );
- ASSERT_EFI_ERROR ( Status);
-
- //
- // PI SMM IPL can't set SMRAM to WB because at that time CPU ARCH protocol is not available.
- // Set cacheability of SMRAM to WB here to improve SMRAM initialization performance.
- //
- SmramSize = 0;
- SmramBase = 0;
- Status = PeiServicesGetHobList ((VOID **) &Hob.Raw);
- while (!END_OF_HOB_LIST (Hob)) {
- if (Hob.Header->HobType == EFI_HOB_TYPE_GUID_EXTENSION) {
- if (CompareGuid (&Hob.Guid->Name, &gEfiSmmSmramMemoryGuid)) {
- SmramHobDescriptorBlock = (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *) (Hob.Guid + 1);
- for (Index = 0; Index < SmramHobDescriptorBlock->NumberOfSmmReservedRegions; Index++) {
- if (SmramHobDescriptorBlock->Descriptor[Index].PhysicalStart > 0x100000) {
- SmramSize += SmramHobDescriptorBlock->Descriptor[Index].PhysicalSize;
- if (SmramBase == 0 || SmramBase > SmramHobDescriptorBlock->Descriptor[Index].CpuStart) {
- SmramBase = SmramHobDescriptorBlock->Descriptor[Index].CpuStart;
- }
- }
- }
- break;
- }
- }
- Hob.Raw = GET_NEXT_HOB (Hob);
- }
-
- //
- // Set non system memory as UC
- //
- MemoryBase = 0x100000000;
-
- //
- // Add IED size to set whole SMRAM as WB to save MTRR count
- //
- MemoryLength = MemoryBase - (SmramBase + SmramSize);
- while (MemoryLength != 0) {
- Power2Length = GetPowerOfTwo64 (MemoryLength);
- MemoryBase -= Power2Length;
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- MemoryBase,
- Power2Length,
- CacheUncacheable
- );
- ASSERT_EFI_ERROR (Status);
- MemoryLength -= Power2Length;
- }
-
- DEBUG ((DEBUG_INFO, "PcdPciReservedMemAbove4GBLimit - 0x%lx\n", PcdGet64 (PcdPciReservedMemAbove4GBLimit)));
- DEBUG ((DEBUG_INFO, "PcdPciReservedMemAbove4GBBase - 0x%lx\n", PcdGet64 (PcdPciReservedMemAbove4GBBase)));
- if (PcdGet64 (PcdPciReservedMemAbove4GBLimit) > PcdGet64 (PcdPciReservedMemAbove4GBBase)) {
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- PcdGet64 (PcdPciReservedMemAbove4GBBase),
- PcdGet64 (PcdPciReservedMemAbove4GBLimit) - PcdGet64 (PcdPciReservedMemAbove4GBBase) + 1,
- CacheUncacheable
- );
- ASSERT_EFI_ERROR ( Status);
- }
-
- DEBUG ((DEBUG_INFO, "PcdPciReservedPMemAbove4GBLimit - 0x%lx\n", PcdGet64 (PcdPciReservedPMemAbove4GBLimit)));
- DEBUG ((DEBUG_INFO, "PcdPciReservedPMemAbove4GBBase - 0x%lx\n", PcdGet64 (PcdPciReservedPMemAbove4GBBase)));
- if (PcdGet64 (PcdPciReservedPMemAbove4GBLimit) > PcdGet64 (PcdPciReservedPMemAbove4GBBase)) {
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- PcdGet64 (PcdPciReservedPMemAbove4GBBase),
- PcdGet64 (PcdPciReservedPMemAbove4GBLimit) - PcdGet64 (PcdPciReservedPMemAbove4GBBase) + 1,
- CacheUncacheable
- );
- ASSERT_EFI_ERROR ( Status);
- }
-
- //
- // Update MTRR setting from MTRR buffer
- //
- MtrrSetAllMtrrs (&MtrrSetting);
-
- return Status;
-}
-
-/**
This function handles PlatformInit task at the end of PEI
@param[in] PeiServices Pointer to PEI Services Table.
@@ -203,7 +56,7 @@ PlatformInitEndOfPei (
)
{
EFI_STATUS Status;
-
+
Status = BoardInitAfterSiliconInit ();
ASSERT_EFI_ERROR (Status);
diff --git a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c
index 2690511abe..c579ff008e 100644
--- a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c
+++ b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/Platfor
+++ mInitPreMem.c
@@ -1,7 +1,7 @@
/** @file
Source code file for Platform Init Pre-Memory PEI module
-Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -15,7 +15,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Library/TimerLib.h> #include <Library/BaseMemoryLib.h> #include <Library/PeiServicesLib.h> -#include <Library/MtrrLib.h> #include <Library/ReportFvLib.h> #include <Ppi/ReadOnlyVariable2.h> #include <Ppi/MemoryDiscovered.h> @@ -26,6 +25,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Library/PeiServicesTablePointerLib.h>
#include <Library/BoardInitLib.h>
#include <Library/TestPointCheckLib.h>
+#include <Library/SetCacheMtrrLib.h>
#include <Guid/MemoryTypeInformation.h> #include <Ppi/PlatformMemorySize.h> #include <Ppi/BaseMemoryTest.h> @@ -319,166 +319,6 @@ Done:
return EFI_SUCCESS;
}
-/**
- Set Cache Mtrr.
-**/
-VOID
-SetCacheMtrr (
- VOID
- )
-{
- EFI_STATUS Status;
- EFI_PEI_HOB_POINTERS Hob;
- MTRR_SETTINGS MtrrSetting;
- UINT64 MemoryBase;
- UINT64 MemoryLength;
- UINT64 LowMemoryLength;
- UINT64 HighMemoryLength;
- EFI_BOOT_MODE BootMode;
- EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;
- UINT64 CacheMemoryLength;
-
- ///
- /// Reset all MTRR setting.
- ///
- ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS));
-
- ///
- /// Cache the Flash area as WP to boost performance
- ///
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- (UINTN) PcdGet32 (PcdFlashAreaBaseAddress),
- (UINTN) PcdGet32 (PcdFlashAreaSize),
- CacheWriteProtected
- );
- ASSERT_EFI_ERROR (Status);
-
- ///
- /// Update MTRR setting from MTRR buffer for Flash Region to be WP to boost performance
- ///
- MtrrSetAllMtrrs (&MtrrSetting);
-
- ///
- /// Set low to 1 MB. Since 1MB cacheability will always be set
- /// until override by CSM.
- /// Initialize high memory to 0.
- ///
- LowMemoryLength = 0x100000;
- HighMemoryLength = 0;
- ResourceAttribute = (
- EFI_RESOURCE_ATTRIBUTE_PRESENT |
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
- );
-
- Status = PeiServicesGetBootMode (&BootMode);
- ASSERT_EFI_ERROR (Status);
-
- if (BootMode != BOOT_ON_S3_RESUME) {
- ResourceAttribute |= EFI_RESOURCE_ATTRIBUTE_TESTED;
- }
-
- Status = PeiServicesGetHobList ((VOID **) &Hob.Raw);
- while (!END_OF_HOB_LIST (Hob)) {
- if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {
- if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) ||
- ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) &&
- (Hob.ResourceDescriptor->ResourceAttribute == ResourceAttribute))
- ) {
- if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000000ULL) {
- HighMemoryLength += Hob.ResourceDescriptor->ResourceLength;
- } else if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000) {
- LowMemoryLength += Hob.ResourceDescriptor->ResourceLength;
- }
- }
- }
-
- Hob.Raw = GET_NEXT_HOB (Hob);
- }
-
- DEBUG ((DEBUG_INFO, "Memory Length (Below 4GB) = %lx.\n", LowMemoryLength));
- DEBUG ((DEBUG_INFO, "Memory Length (Above 4GB) = %lx.\n", HighMemoryLength));
-
- ///
- /// Assume size of main memory is multiple of 256MB
- ///
- MemoryLength = (LowMemoryLength + 0xFFFFFFF) & 0xF0000000;
- MemoryBase = 0;
-
- CacheMemoryLength = MemoryLength;
- ///
- /// Programming MTRRs to avoid override SPI region with UC when MAX TOLUD Length >= 3.5GB
- ///
- if (MemoryLength > 0xDC000000) {
- CacheMemoryLength = 0xC0000000;
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- MemoryBase,
- CacheMemoryLength,
- CacheWriteBack
- );
- ASSERT_EFI_ERROR (Status);
-
- MemoryBase = 0xC0000000;
- CacheMemoryLength = MemoryLength - 0xC0000000;
- if (MemoryLength > 0xE0000000) {
- CacheMemoryLength = 0x20000000;
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- MemoryBase,
- CacheMemoryLength,
- CacheWriteBack
- );
- ASSERT_EFI_ERROR (Status);
-
- MemoryBase = 0xE0000000;
- CacheMemoryLength = MemoryLength - 0xE0000000;
- }
- }
-
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- MemoryBase,
- CacheMemoryLength,
- CacheWriteBack
- );
- ASSERT_EFI_ERROR (Status);
-
- if (LowMemoryLength != MemoryLength) {
- MemoryBase = LowMemoryLength;
- MemoryLength -= LowMemoryLength;
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- MemoryBase,
- MemoryLength,
- CacheUncacheable
- );
- ASSERT_EFI_ERROR (Status);
- }
-
- ///
- /// VGA-MMIO - 0xA0000 to 0xC0000 to be UC
- ///
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- 0xA0000,
- 0x20000,
- CacheUncacheable
- );
- ASSERT_EFI_ERROR (Status);
-
- ///
- /// Update MTRR setting from MTRR buffer
- ///
- MtrrSetAllMtrrs (&MtrrSetting);
-
- return ;
-}
-
VOID
ReportCpuHob (
VOID
diff --git a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf
index 0736c8d494..74a9b91540 100644
--- a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf
+++ b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/Platfor
+++ mInitPostMem.inf
@@ -23,15 +23,14 @@
BaseMemoryLib
HobLib
PeiServicesLib
- MtrrLib
BoardInitLib
TestPointCheckLib
+ SetCacheMtrrLib
[Packages]
MinPlatformPkg/MinPlatformPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- UefiCpuPkg/UefiCpuPkg.dec
[Sources]
PlatformInitPostMem.c
@@ -44,14 +43,6 @@
[Protocols]
-[Guids]
- gEfiSmmSmramMemoryGuid ## CONSUMES
-
[Depex]
gEfiPeiMemoryDiscoveredPpiGuid
-[Pcd]
- gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase
- gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit
- gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBBase
- gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBLimit
diff --git a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
index 2c3a13106e..af5dbe8772 100644
--- a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
+++ b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/Platfor
+++ mInitPreMem.inf
@@ -1,7 +1,7 @@
### @file
# Component information file for the Platform Init Pre-Memory PEI module.
#
-# Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights
+reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -22,23 +22,20 @@
HobLib
IoLib
MemoryAllocationLib
- MtrrLib
PeimEntryPoint
PeiServicesLib
ReportFvLib
TestPointCheckLib
TimerLib
+ SetCacheMtrrLib
[Packages]
MinPlatformPkg/MinPlatformPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- UefiCpuPkg/UefiCpuPkg.dec
[Pcd]
gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode ## CONSUMES
- gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSUMES
- gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## CONSUMES
gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit ## CONSUMES
gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit ## CONSUMES
--
2.13.3.windows.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [edk2-devel] [edk2-platforms: PATCH v3 3/6] KabylakeOpenBoardPkg: Add SetCacheMtrrLib library class.
2019-10-31 10:28 ` [edk2-platforms: PATCH v3 3/6] KabylakeOpenBoardPkg: " Chiu, Chasel
@ 2019-11-01 18:29 ` Nate DeSimone
0 siblings, 0 replies; 16+ messages in thread
From: Nate DeSimone @ 2019-11-01 18:29 UTC (permalink / raw)
To: devel@edk2.groups.io, Chiu, Chasel
Cc: Kubacki, Michael A, Gao, Liming, Jeremy Soller
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Chiu, Chasel
Sent: Thursday, October 31, 2019 3:28 AM
To: devel@edk2.groups.io
Cc: Kubacki, Michael A <michael.a.kubacki@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Gao, Liming <liming.gao@intel.com>; Jeremy Soller <jeremy@system76.com>
Subject: [edk2-devel] [edk2-platforms: PATCH v3 3/6] KabylakeOpenBoardPkg: Add SetCacheMtrrLib library class.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2314
Kabylake boards are relying on FSP to configure MTRRs so they can include SetCacheMtrrLibNull.
Test: internal platform can boot with FSP API and Dispatch modes.
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c | 640 ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc | 3 ++-
Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf | 2 +-
Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf | 67 -------------------------------------------------------------------
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc | 1 +
5 files changed, 4 insertions(+), 709 deletions(-)
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c
deleted file mode 100644
index b784026c1b..0000000000
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c
+++ /dev/null
@@ -1,640 +0,0 @@
-/** @file
- Source code file for Platform Init Pre-Memory PEI module
-
-Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <Base.h>
-#include <IndustryStandard/Pci30.h>
-#include <Library/IoLib.h>
-#include <Library/DebugLib.h>
-#include <Library/HobLib.h>
-#include <Library/PcdLib.h>
-#include <Library/TimerLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/PeiServicesLib.h>
-#include <Library/MtrrLib.h>
-#include <Library/ReportFvLib.h>
-#include <Ppi/ReadOnlyVariable2.h>
-#include <Ppi/MemoryDiscovered.h>
-#include <Ppi/FirmwareVolumeInfo.h>
-#include <Ppi/BootInRecoveryMode.h>
-#include <Ppi/MasterBootMode.h>
-#include <Guid/FirmwareFileSystem2.h>
-#include <Library/PeiServicesTablePointerLib.h>
-#include <Library/BoardInitLib.h>
-#include <Library/TestPointCheckLib.h>
-#include <Guid/MemoryTypeInformation.h> -#include <Ppi/PlatformMemorySize.h> -#include <Ppi/BaseMemoryTest.h>
-
-EFI_STATUS
-EFIAPI
-MemoryDiscoveredPpiNotifyCallback (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
- IN VOID *Ppi
- );
-
-EFI_STATUS
-EFIAPI
-GetPlatformMemorySize (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_PLATFORM_MEMORY_SIZE_PPI *This,
- IN OUT UINT64 *MemorySize
- );
-
-/**
-
- This function checks the memory range in PEI.
-
- @param PeiServices Pointer to PEI Services.
- @param This Pei memory test PPI pointer.
- @param BeginAddress Beginning of the memory address to be checked.
- @param MemoryLength Bytes of memory range to be checked.
- @param Operation Type of memory check operation to be performed.
- @param ErrorAddress Return the address of the error memory address.
-
- @retval EFI_SUCCESS The operation completed successfully.
- @retval EFI_DEVICE_ERROR Memory test failed. It's not safe to use this range of memory.
-
-**/
-EFI_STATUS
-EFIAPI
-BaseMemoryTest (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_BASE_MEMORY_TEST_PPI *This,
- IN EFI_PHYSICAL_ADDRESS BeginAddress,
- IN UINT64 MemoryLength,
- IN PEI_MEMORY_TEST_OP Operation,
- OUT EFI_PHYSICAL_ADDRESS *ErrorAddress
- );
-
-static EFI_PEI_NOTIFY_DESCRIPTOR mMemDiscoveredNotifyList = {
- (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
- &gEfiPeiMemoryDiscoveredPpiGuid,
- (EFI_PEIM_NOTIFY_ENTRY_POINT) MemoryDiscoveredPpiNotifyCallback -};
-
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mPpiListRecoveryBootMode = {
- (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
- &gEfiPeiBootInRecoveryModePpiGuid,
- NULL
-};
-
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mPpiBootMode = {
- (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
- &gEfiPeiMasterBootModePpiGuid,
- NULL
-};
-
-static PEI_BASE_MEMORY_TEST_PPI mPeiBaseMemoryTestPpi = { BaseMemoryTest };
-
-static PEI_PLATFORM_MEMORY_SIZE_PPI mMemoryMemorySizePpi = { GetPlatformMemorySize };
-
-static EFI_PEI_PPI_DESCRIPTOR mMemPpiList[] = {
- {
- EFI_PEI_PPI_DESCRIPTOR_PPI,
- &gPeiBaseMemoryTestPpiGuid,
- &mPeiBaseMemoryTestPpi
- },
- {
- (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
- &gPeiPlatformMemorySizePpiGuid,
- &mMemoryMemorySizePpi
- },
-};
-
-///
-/// Memory Reserved should be between 125% to 150% of the Current required memory -/// otherwise BdsMisc.c would do a reset to make it 125% to avoid s4 resume issues.
-///
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
- { EfiACPIReclaimMemory, FixedPcdGet32 (PcdPlatformEfiAcpiReclaimMemorySize) }, // ASL
- { EfiACPIMemoryNVS, FixedPcdGet32 (PcdPlatformEfiAcpiNvsMemorySize) }, // ACPI NVS (including S3 related)
- { EfiReservedMemoryType, FixedPcdGet32 (PcdPlatformEfiReservedMemorySize) }, // BIOS Reserved (including S3 related)
- { EfiRuntimeServicesData, FixedPcdGet32 (PcdPlatformEfiRtDataMemorySize) }, // Runtime Service Data
- { EfiRuntimeServicesCode, FixedPcdGet32 (PcdPlatformEfiRtCodeMemorySize) }, // Runtime Service Code
- { EfiMaxMemoryType, 0 }
-};
-
-VOID
-BuildMemoryTypeInformation (
- VOID
- )
-{
- EFI_STATUS Status;
- EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
- UINTN DataSize;
- EFI_MEMORY_TYPE_INFORMATION MemoryData[EfiMaxMemoryType + 1];
-
- //
- // Locate system configuration variable
- //
- Status = PeiServicesLocatePpi(
- &gEfiPeiReadOnlyVariable2PpiGuid, // GUID
- 0, // INSTANCE
- NULL, // EFI_PEI_PPI_DESCRIPTOR
- (VOID **) &VariableServices // PPI
- );
- ASSERT_EFI_ERROR(Status);
-
- DataSize = sizeof (MemoryData);
- Status = VariableServices->GetVariable (
- VariableServices,
- EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME,
- &gEfiMemoryTypeInformationGuid,
- NULL,
- &DataSize,
- &MemoryData
- );
- if (EFI_ERROR(Status)) {
- DataSize = sizeof (mDefaultMemoryTypeInformation);
- CopyMem(MemoryData, mDefaultMemoryTypeInformation, DataSize);
- }
-
- ///
- /// Build the GUID'd HOB for DXE
- ///
- BuildGuidDataHob (
- &gEfiMemoryTypeInformationGuid,
- MemoryData,
- DataSize
- );
-}
-
-EFI_STATUS
-EFIAPI
-GetPlatformMemorySize (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_PLATFORM_MEMORY_SIZE_PPI *This,
- IN OUT UINT64 *MemorySize
- )
-{
- EFI_STATUS Status;
- EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable;
- UINTN DataSize;
- EFI_MEMORY_TYPE_INFORMATION MemoryData[EfiMaxMemoryType + 1];
- UINTN Index;
- EFI_BOOT_MODE BootMode;
- UINTN IndexNumber;
-
-#define PEI_MIN_MEMORY_SIZE (EFI_PHYSICAL_ADDRESS) ((320 * 0x100000))
-
- *MemorySize = PEI_MIN_MEMORY_SIZE;
- Status = PeiServicesLocatePpi (
- &gEfiPeiReadOnlyVariable2PpiGuid,
- 0,
- NULL,
- (VOID **)&Variable
- );
-
- ASSERT_EFI_ERROR (Status);
-
- Status = PeiServicesGetBootMode (&BootMode);
- ASSERT_EFI_ERROR (Status);
-
- DataSize = sizeof (MemoryData);
-
- Status = Variable->GetVariable (
- Variable,
- EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME,
- &gEfiMemoryTypeInformationGuid,
- NULL,
- &DataSize,
- &MemoryData
- );
- IndexNumber = sizeof (mDefaultMemoryTypeInformation) / sizeof (EFI_MEMORY_TYPE_INFORMATION);
-
- //
- // Accumulate maximum amount of memory needed
- //
-
- DEBUG((DEBUG_ERROR, "PEI_MIN_MEMORY_SIZE:%dKB \n", DivU64x32(*MemorySize,1024)));
- DEBUG((DEBUG_ERROR, "IndexNumber:%d MemoryDataNumber%d \n", IndexNumber,DataSize/ sizeof (EFI_MEMORY_TYPE_INFORMATION)));
- if (EFI_ERROR (Status)) {
- //
- // Start with minimum memory
- //
- for (Index = 0; Index < IndexNumber; Index++) {
- DEBUG((DEBUG_ERROR, "Index[%d].Type = %d .NumberOfPages=0x%x\n", Index,mDefaultMemoryTypeInformation[Index].Type,mDefaultMemoryTypeInformation[Index].NumberOfPages));
- *MemorySize += mDefaultMemoryTypeInformation[Index].NumberOfPages * EFI_PAGE_SIZE;
- }
- DEBUG((DEBUG_ERROR, "No memory type, Total platform memory:%dKB \n", DivU64x32(*MemorySize,1024)));
- } else {
- //
- // Start with at least 0x200 pages of memory for the DXE Core and the DXE Stack
- //
- for (Index = 0; Index < IndexNumber; Index++) {
- DEBUG((DEBUG_ERROR, "Index[%d].Type = %d .NumberOfPages=0x%x\n", Index,MemoryData[Index].Type,MemoryData[Index].NumberOfPages));
- *MemorySize += MemoryData[Index].NumberOfPages * EFI_PAGE_SIZE;
-
- }
- DEBUG((DEBUG_ERROR, "has memory type, Total platform memory:%dKB \n", DivU64x32(*MemorySize,1024)));
- }
-
- return EFI_SUCCESS;
-}
-
-/**
-
- This function checks the memory range in PEI.
-
- @param PeiServices Pointer to PEI Services.
- @param This Pei memory test PPI pointer.
- @param BeginAddress Beginning of the memory address to be checked.
- @param MemoryLength Bytes of memory range to be checked.
- @param Operation Type of memory check operation to be performed.
- @param ErrorAddress Return the address of the error memory address.
-
- @retval EFI_SUCCESS The operation completed successfully.
- @retval EFI_DEVICE_ERROR Memory test failed. It's not safe to use this range of memory.
-
-**/
-EFI_STATUS
-EFIAPI
-BaseMemoryTest (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_BASE_MEMORY_TEST_PPI *This,
- IN EFI_PHYSICAL_ADDRESS BeginAddress,
- IN UINT64 MemoryLength,
- IN PEI_MEMORY_TEST_OP Operation,
- OUT EFI_PHYSICAL_ADDRESS *ErrorAddress
- )
-{
- UINT32 TestPattern;
- UINT32 SpanSize;
- EFI_PHYSICAL_ADDRESS TempAddress;
-
-#define MEMORY_TEST_PATTERN 0x5A5A5A5A
-#define MEMORY_TEST_COVER_SPAN 0x40000
-
- TestPattern = MEMORY_TEST_PATTERN;
- SpanSize = 0;
-
- //
- // Make sure we don't try and test anything above the max physical address range
- //
- ASSERT (BeginAddress + MemoryLength < MAX_ADDRESS);
-
- switch (Operation) {
- case Extensive:
- SpanSize = 0x4;
- break;
-
- case Sparse:
- case Quick:
- SpanSize = MEMORY_TEST_COVER_SPAN;
- break;
-
- case Ignore:
- goto Done;
- break;
- }
- //
- // Write the test pattern into memory range
- //
- TempAddress = BeginAddress;
- while (TempAddress < BeginAddress + MemoryLength) {
- (*(UINT32 *) (UINTN) TempAddress) = TestPattern;
- TempAddress += SpanSize;
- }
- //
- // Read pattern from memory and compare it
- //
- TempAddress = BeginAddress;
- while (TempAddress < BeginAddress + MemoryLength) {
- if ((*(UINT32 *) (UINTN) TempAddress) != TestPattern) {
- *ErrorAddress = TempAddress;
- return EFI_DEVICE_ERROR;
- }
-
- TempAddress += SpanSize;
- }
-
-Done:
-
- return EFI_SUCCESS;
-}
-
-/**
- Set Cache Mtrr.
-**/
-VOID
-SetCacheMtrr (
- VOID
- )
-{
- EFI_STATUS Status;
- EFI_PEI_HOB_POINTERS Hob;
- MTRR_SETTINGS MtrrSetting;
- UINT64 MemoryBase;
- UINT64 MemoryLength;
- UINT64 LowMemoryLength;
- UINT64 HighMemoryLength;
- EFI_BOOT_MODE BootMode;
- EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;
- UINT64 CacheMemoryLength;
-
- ///
- /// Reset all MTRR setting.
- ///
- ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS));
-
- ///
- /// Cache the Flash area as WP to boost performance
- ///
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- (UINTN) PcdGet32 (PcdFlashAreaBaseAddress),
- (UINTN) PcdGet32 (PcdFlashAreaSize),
- CacheWriteProtected
- );
- ASSERT_EFI_ERROR (Status);
-
- ///
- /// Update MTRR setting from MTRR buffer for Flash Region to be WP to boost performance
- ///
- MtrrSetAllMtrrs (&MtrrSetting);
-
- ///
- /// Set low to 1 MB. Since 1MB cacheability will always be set
- /// until override by CSM.
- /// Initialize high memory to 0.
- ///
- LowMemoryLength = 0x100000;
- HighMemoryLength = 0;
- ResourceAttribute = (
- EFI_RESOURCE_ATTRIBUTE_PRESENT |
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
- );
-
- Status = PeiServicesGetBootMode (&BootMode);
- ASSERT_EFI_ERROR (Status);
-
- if (BootMode != BOOT_ON_S3_RESUME) {
- ResourceAttribute |= EFI_RESOURCE_ATTRIBUTE_TESTED;
- }
-
- Status = PeiServicesGetHobList ((VOID **) &Hob.Raw);
- while (!END_OF_HOB_LIST (Hob)) {
- if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {
- if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) ||
- ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) &&
- (Hob.ResourceDescriptor->ResourceAttribute == ResourceAttribute))
- ) {
- if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000000ULL) {
- HighMemoryLength += Hob.ResourceDescriptor->ResourceLength;
- } else if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000) {
- LowMemoryLength += Hob.ResourceDescriptor->ResourceLength;
- }
- }
- }
-
- Hob.Raw = GET_NEXT_HOB (Hob);
- }
-
- DEBUG ((DEBUG_INFO, "Memory Length (Below 4GB) = %lx.\n", LowMemoryLength));
- DEBUG ((DEBUG_INFO, "Memory Length (Above 4GB) = %lx.\n", HighMemoryLength));
-
- ///
- /// Assume size of main memory is multiple of 256MB
- ///
- MemoryLength = (LowMemoryLength + 0xFFFFFFF) & 0xF0000000;
- MemoryBase = 0;
-
- CacheMemoryLength = MemoryLength;
- ///
- /// Programming MTRRs to avoid override SPI region with UC when MAX TOLUD Length >= 3.5GB
- ///
- if (MemoryLength > 0xDC000000) {
- CacheMemoryLength = 0xC0000000;
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- MemoryBase,
- CacheMemoryLength,
- CacheWriteBack
- );
- ASSERT_EFI_ERROR (Status);
-
- MemoryBase = 0xC0000000;
- CacheMemoryLength = MemoryLength - 0xC0000000;
- if (MemoryLength > 0xE0000000) {
- CacheMemoryLength = 0x20000000;
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- MemoryBase,
- CacheMemoryLength,
- CacheWriteBack
- );
- ASSERT_EFI_ERROR (Status);
-
- MemoryBase = 0xE0000000;
- CacheMemoryLength = MemoryLength - 0xE0000000;
- }
- }
-
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- MemoryBase,
- CacheMemoryLength,
- CacheWriteBack
- );
- ASSERT_EFI_ERROR (Status);
-
- if (LowMemoryLength != MemoryLength) {
- MemoryBase = LowMemoryLength;
- MemoryLength -= LowMemoryLength;
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- MemoryBase,
- MemoryLength,
- CacheUncacheable
- );
- ASSERT_EFI_ERROR (Status);
- }
-
- ///
- /// VGA-MMIO - 0xA0000 to 0xC0000 to be UC
- ///
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- 0xA0000,
- 0x20000,
- CacheUncacheable
- );
- ASSERT_EFI_ERROR (Status);
-
- ///
- /// Update MTRR setting from MTRR buffer
- ///
- MtrrSetAllMtrrs (&MtrrSetting);
-
- return ;
-}
-
-VOID
-ReportCpuHob (
- VOID
- )
-{
- UINT8 PhysicalAddressBits;
- UINT32 RegEax;
-
- AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
- if (RegEax >= 0x80000008) {
- AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
- PhysicalAddressBits = (UINT8) RegEax;
- } else {
- PhysicalAddressBits = 36;
- }
-
- ///
- /// Create a CPU hand-off information
- ///
- BuildCpuHob (PhysicalAddressBits, 16); -}
-
-/**
- Install Firmware Volume Hob's once there is main memory
-
- @param[in] PeiServices General purpose services available to every PEIM.
- @param[in] NotifyDescriptor Notify that this module published.
- @param[in] Ppi PPI that was installed.
-
- @retval EFI_SUCCESS The function completed successfully.
-**/
-EFI_STATUS
-EFIAPI
-MemoryDiscoveredPpiNotifyCallback (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
- IN VOID *Ppi
- )
-{
- EFI_STATUS Status;
- EFI_BOOT_MODE BootMode;
-
- Status = BoardInitAfterMemoryInit ();
- ASSERT_EFI_ERROR (Status);
-
- Status = PeiServicesGetBootMode (&BootMode);
- ASSERT_EFI_ERROR (Status);
-
-
- ReportCpuHob ();
-
- TestPointMemoryDiscoveredMtrrFunctional ();
-
- TestPointMemoryDiscoveredMemoryResourceFunctional ();
-
- ///
- /// If S3 resume, then we are done
- ///
- if (BootMode == BOOT_ON_S3_RESUME) {
- return EFI_SUCCESS;
- }
-
- TestPointMemoryDiscoveredDmaProtectionEnabled ();
-
- if (PcdGetBool (PcdStopAfterMemInit)) {
- CpuDeadLoop ();
- }
-
- return Status;
-}
-
-
-/**
- This function handles PlatformInit task after PeiReadOnlyVariable2 PPI produced
-
- @param[in] PeiServices Pointer to PEI Services Table.
-
- @retval EFI_SUCCESS The function completes successfully
- @retval others
-**/
-EFI_STATUS
-EFIAPI
-PlatformInitPreMem (
- IN CONST EFI_PEI_SERVICES **PeiServices
- )
-{
- EFI_STATUS Status;
- EFI_BOOT_MODE BootMode;
-
- //
- // Start board detection
- //
- BoardDetect ();
-
- BoardDebugInit ();
-
- TestPointDebugInitDone ();
-
- if (PcdGetBool (PcdStopAfterDebugInit)) {
- CpuDeadLoop ();
- }
-
- BootMode = BoardBootModeDetect ();
- Status = PeiServicesSetBootMode (BootMode);
- ASSERT_EFI_ERROR (Status);
- if (BootMode == BOOT_IN_RECOVERY_MODE) {
- Status = PeiServicesInstallPpi (&mPpiListRecoveryBootMode);
- }
- ///
- /// Signal possible dependent modules that there has been a
- /// final boot mode determination, it is used to build BIST
- /// Hob for Dxe use.
- ///
- Status = PeiServicesInstallPpi (&mPpiBootMode);
- ASSERT_EFI_ERROR (Status);
-
- BuildMemoryTypeInformation ();
-
- if (!PcdGetBool(PcdFspWrapperBootMode)) {
- Status = PeiServicesInstallPpi (mMemPpiList);
- ASSERT_EFI_ERROR (Status);
- }
-
- Status = BoardInitBeforeMemoryInit ();
- ASSERT_EFI_ERROR (Status);
-
- return Status;
-}
-
-
-/**
- Platform Init before memory PEI module entry point
-
- @param[in] FileHandle Not used.
- @param[in] PeiServices General purpose services available to every PEIM.
-
- @retval EFI_SUCCESS The function completes successfully
- @retval EFI_OUT_OF_RESOURCES Insufficient resources to create database
-**/
-EFI_STATUS
-EFIAPI
-PlatformInitPreMemEntryPoint (
- IN EFI_PEI_FILE_HANDLE FileHandle,
- IN CONST EFI_PEI_SERVICES **PeiServices
- )
-{
- EFI_STATUS Status;
-
- Status = PlatformInitPreMem (PeiServices);
-
- ///
- /// After code reorangized, memorycallback will run because the PPI is already
- /// installed when code run to here, it is supposed that the InstallEfiMemory is
- /// done before.
- ///
- Status = PeiServicesNotifyPpi (&mMemDiscoveredNotifyList);
-
- return Status;
-}
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
index f59248bba4..000cf2be4c 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
@@ -159,6 +159,7 @@
#######################################
DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
+
+ SetCacheMtrrLib|$(PLATFORM_PACKAGE)/Library/SetCacheMtrrLib/SetCacheMt
+ rrLibNull.inf
#######################################
# Platform Package
@@ -260,7 +261,7 @@
# Platform Package
#######################################
$(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf
- $(PROJECT)/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf {
+
+ $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.in
+ f {
<LibraryClasses>
!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport == FALSE
BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf
index 80efab1aad..6827019c25 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf
@@ -237,7 +237,7 @@ INF MdeModulePkg/Core/Pei/PeiMain.inf !include $(PLATFORM_PACKAGE)/Include/Fdf/CorePreMemoryInclude.fdf
INF $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf
-INF $(PROJECT)/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
+INF
+$(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf
INF $(PLATFORM_BOARD_PACKAGE)/BiosInfo/BiosInfo.inf
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
deleted file mode 100644
index 76dd67d1a8..0000000000
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
+++ /dev/null
@@ -1,67 +0,0 @@
-### @file
-# Component information file for the Platform Init Pre-Memory PEI module.
-#
-# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -###
-
-[Defines]
- INF_VERSION = 0x00010017
- BASE_NAME = PlatformInitPreMem
- FILE_GUID = EEEE611D-F78F-4FB9-B868-55907F169280
- VERSION_STRING = 1.0
- MODULE_TYPE = PEIM
- ENTRY_POINT = PlatformInitPreMemEntryPoint
-
-[LibraryClasses]
- BaseMemoryLib
- BoardInitLib
- DebugLib
- HobLib
- IoLib
- MemoryAllocationLib
- MtrrLib
- PeimEntryPoint
- PeiServicesLib
- ReportFvLib
- TestPointCheckLib
- TimerLib
-
-[Packages]
- MinPlatformPkg/MinPlatformPkg.dec
- MdeModulePkg/MdeModulePkg.dec
- MdePkg/MdePkg.dec
- UefiCpuPkg/UefiCpuPkg.dec
-
-[Pcd]
- gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode ## CONSUMES
- gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSUMES
- gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## CONSUMES
- gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit ## CONSUMES
- gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit ## CONSUMES
-
-[FixedPcd]
- gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize ## CONSUMES
- gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize ## CONSUMES
- gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize ## CONSUMES
- gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize ## CONSUMES
- gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize ## CONSUMES
-
-[Sources]
- PlatformInitPreMem.c
-
-[Ppis]
- gEfiPeiMemoryDiscoveredPpiGuid
- gEfiPeiMasterBootModePpiGuid ## PRODUCES
- gEfiPeiBootInRecoveryModePpiGuid ## PRODUCES
- gEfiPeiReadOnlyVariable2PpiGuid
- gPeiBaseMemoryTestPpiGuid
- gPeiPlatformMemorySizePpiGuid
-
-[Guids]
- gEfiMemoryTypeInformationGuid
-
-[Depex]
- gEfiPeiReadOnlyVariable2PpiGuid
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
index 7e65eeda6f..8178604554 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
@@ -208,6 +208,7 @@
!if $(TARGET) == DEBUG
TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf
!endif
+
+ SetCacheMtrrLib|$(PLATFORM_PACKAGE)/Library/SetCacheMtrrLib/SetCacheMt
+ rrLibNull.inf
#######################################
# Board Package
--
2.13.3.windows.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [edk2-devel] [edk2-platforms: PATCH v3 4/6] WhiskeylakeOpenBoardPkg: Add SetCacheMtrrLib library class.
2019-10-31 10:28 ` [edk2-platforms: PATCH v3 4/6] WhiskeylakeOpenBoardPkg: " Chiu, Chasel
@ 2019-11-01 18:29 ` Nate DeSimone
0 siblings, 0 replies; 16+ messages in thread
From: Nate DeSimone @ 2019-11-01 18:29 UTC (permalink / raw)
To: devel@edk2.groups.io, Chiu, Chasel; +Cc: Kubacki, Michael A
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Chiu, Chasel
Sent: Thursday, October 31, 2019 3:28 AM
To: devel@edk2.groups.io
Cc: Kubacki, Michael A <michael.a.kubacki@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
Subject: [edk2-devel] [edk2-platforms: PATCH v3 4/6] WhiskeylakeOpenBoardPkg: Add SetCacheMtrrLib library class.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2314
Whiskeylake board relying on FSP to configure MTRRs so it can include SetCacheMtrrLibNull.
Test: internal platform can boot with FSP API modes.
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc | 1 +
1 file changed, 1 insertion(+)
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc
index 8e0ea2d5ce..20b16fd7ef 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPk
+++ g.dsc
@@ -164,6 +164,7 @@
!if $(TARGET) == DEBUG
TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf
!endif
+
+ SetCacheMtrrLib|$(PLATFORM_PACKAGE)/Library/SetCacheMtrrLib/SetCacheMt
+ rrLibNull.inf
#######################################
# Board Package
--
2.13.3.windows.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [edk2-devel] [edk2-platforms: PATCH v3 5/6] PurleyOpenBoardPkg/BoardMtOlympus: Add SetCacheMtrrLib library class.
2019-10-31 10:28 ` [edk2-platforms: PATCH v3 5/6] PurleyOpenBoardPkg/BoardMtOlympus: " Chiu, Chasel
@ 2019-11-01 18:29 ` Nate DeSimone
0 siblings, 0 replies; 16+ messages in thread
From: Nate DeSimone @ 2019-11-01 18:29 UTC (permalink / raw)
To: devel@edk2.groups.io, Chiu, Chasel
Cc: Lu, Shifei A, Zhou, Bowen, Oram, Isaac W
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Chiu, Chasel
Sent: Thursday, October 31, 2019 3:28 AM
To: devel@edk2.groups.io
Cc: Lu, Shifei A <shifei.a.lu@intel.com>; Zhou, Bowen <bowen.zhou@intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>
Subject: [edk2-devel] [edk2-platforms: PATCH v3 5/6] PurleyOpenBoardPkg/BoardMtOlympus: Add SetCacheMtrrLib library class.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2314
Include SetCacheMtrrLib from MinPlatformPkg.
Cc: Shifei A Lu <shifei.a.lu@intel.com>
Cc: Xiaohu Zhou <bowen.zhou@intel.com>
Cc: Isaac W Oram <isaac.w.oram@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkg.dsc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkg.dsc b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkg.dsc
index 595ffd4144..488243081f 100644
--- a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkg.dsc
+++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkg.dsc
@@ -1,6 +1,6 @@
### @file
#
-# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2018 - 2019, Intel Corporation. All rights
+reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -135,6 +135,7 @@ !include $(RC_PKG)/RcDxeLib.dsc !include $(SKT_PKG)/SktDxeLib.dsc !include $(PCH_PKG)/PchDxeLib.dsc
+
+ SetCacheMtrrLib|MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib
+ .inf
[LibraryClasses.X64]
BoardAcpiTableLib|$(BOARD_PKG)/$(BOARD_NAME)/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf
--
2.13.3.windows.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [edk2-devel] [edk2-platforms: PATCH v3 6/6] SimicsOpenBoardPkg/BoardX58Ich10: Add SetCacheMtrrLib library class.
2019-10-31 10:28 ` [edk2-platforms: PATCH v3 6/6] SimicsOpenBoardPkg/BoardX58Ich10: " Chiu, Chasel
2019-10-31 19:42 ` Agyeman, Prince
@ 2019-11-01 18:29 ` Nate DeSimone
1 sibling, 0 replies; 16+ messages in thread
From: Nate DeSimone @ 2019-11-01 18:29 UTC (permalink / raw)
To: devel@edk2.groups.io, Chiu, Chasel; +Cc: Wei, David Y, Agyeman, Prince
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Chiu, Chasel
Sent: Thursday, October 31, 2019 3:28 AM
To: devel@edk2.groups.io
Cc: Wei, David Y <david.y.wei@intel.com>; Agyeman, Prince <prince.agyeman@intel.com>
Subject: [edk2-devel] [edk2-platforms: PATCH v3 6/6] SimicsOpenBoardPkg/BoardX58Ich10: Add SetCacheMtrrLib library class.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2314
Include SetCacheMtrrLib from MinPlatformPkg.
Cc: Wei David Y <david.y.wei@intel.com>
Cc: Agyeman Prince <prince.agyeman@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc | 1 +
1 file changed, 1 insertion(+)
diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc
index 4f8ab4170d..8cad7b5b69 100644
--- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc
+++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc
@@ -136,6 +136,7 @@
TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf
!endif
TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPointLib.inf
+ SetCacheMtrrLib|$(PLATFORM_PACKAGE)/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
[LibraryClasses.common.DXE_DRIVER]
#######################################
--
2.13.3.windows.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
end of thread, other threads:[~2019-11-01 18:29 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-10-31 10:28 [edk2-platforms: PATCH v3 0/6] Add SetCacheMtrrLib library class Chiu, Chasel
2019-10-31 10:28 ` [edk2-platforms: PATCH v3 1/6] MinPlatformPkg: " Chiu, Chasel
2019-10-31 17:02 ` [edk2-devel] " Kubacki, Michael A
2019-11-01 1:24 ` Chiu, Chasel
2019-11-01 18:29 ` Nate DeSimone
2019-10-31 10:28 ` [edk2-platforms: PATCH v3 2/6] " Chiu, Chasel
2019-11-01 18:29 ` [edk2-devel] " Nate DeSimone
2019-10-31 10:28 ` [edk2-platforms: PATCH v3 3/6] KabylakeOpenBoardPkg: " Chiu, Chasel
2019-11-01 18:29 ` [edk2-devel] " Nate DeSimone
2019-10-31 10:28 ` [edk2-platforms: PATCH v3 4/6] WhiskeylakeOpenBoardPkg: " Chiu, Chasel
2019-11-01 18:29 ` [edk2-devel] " Nate DeSimone
2019-10-31 10:28 ` [edk2-platforms: PATCH v3 5/6] PurleyOpenBoardPkg/BoardMtOlympus: " Chiu, Chasel
2019-11-01 18:29 ` [edk2-devel] " Nate DeSimone
2019-10-31 10:28 ` [edk2-platforms: PATCH v3 6/6] SimicsOpenBoardPkg/BoardX58Ich10: " Chiu, Chasel
2019-10-31 19:42 ` Agyeman, Prince
2019-11-01 18:29 ` [edk2-devel] " Nate DeSimone
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