From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qt0-x22c.google.com (mail-qt0-x22c.google.com [IPv6:2607:f8b0:400d:c0d::22c]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E80C420084747 for ; Mon, 27 Mar 2017 04:58:57 -0700 (PDT) Received: by mail-qt0-x22c.google.com with SMTP id r45so34714732qte.3 for ; Mon, 27 Mar 2017 04:58:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=If0t4BWTFxlyaX3WfHszc4vqizkD/NOeeu249GJfaUw=; b=LQ7UIM43jYx0osZyHiaNrS/DbPvAHwJ4hoF1qBnlBJH0/3Tg2+Qgk3LM5jQztA4Wh0 jBGL+PZTVv8ItGRPFyx4UOBMTkeI0qpsnaY/TM3LcPsooHjvJC79EBZU0r54EcrPYv9R oBNe5rteEZv5ScQztqMrxjySihFWcogWvO6WZC3fockQ6HvcuR/CUaI85+hkFsfl8i+/ H0G40h7Ex68CGBtRUkvc0cgoHx/vcS2p/PdUWMmGaFCK+Go+EzmxWUEpGN5PD/rHHyHS a7h+VOk2SCQ/pTL0I/mw/NA3bGjoLukC6zkcowj5rsz4TyKY1Flokwii0daDu7ZCoKBz w7Mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=If0t4BWTFxlyaX3WfHszc4vqizkD/NOeeu249GJfaUw=; b=OoZl6hqPWnG7dhchX7f1Dx2W7qT22bAO535oKjnjS6D9odhX9JKEYluIhi1lWNagNa 2rVi9hZx7tkOWJDb50UDvLvlSu2sUVjxD4Lj/CTukQgiGBEs98HDhFWkCl2VM0FEKOtw 65dodt5G2VW+A/n75e5w7PqGjFw91jnh1VeOajUjZjP/adZ2IerSVvw9aSjv9xr99PTz s88wGauSpL++dVUK296XPPq9xD0AU4s6AT5N/EoNVzSreLxn3O8zyV1rQCOdIJTTJLC3 6IVAKzWMo5DBwewgCzHgivlakxCJ0/Zc++j6d/5c6SzjORYvYFiKHMuK6WzZOskdZDnq 5ieA== X-Gm-Message-State: AFeK/H1VdXLlhyeyUQE++Fv3IkdtWzYjIlPFCjaeEVEOvCQFrS5dx5w+GMeg8EL99GK4a2GD/ov5kf0pckmigA== X-Received: by 10.200.47.161 with SMTP id l30mr20671435qta.248.1490615936765; Mon, 27 Mar 2017 04:58:56 -0700 (PDT) MIME-Version: 1.0 Received: by 10.12.182.65 with HTTP; Mon, 27 Mar 2017 04:58:56 -0700 (PDT) In-Reply-To: <542CF652F8836A4AB8DBFAAD40ED192A4C57C672@shsmsx102.ccr.corp.intel.com> References: <149013076154.27235.10725020825643505862.stgit@brijesh-build-machine> <149013076888.27235.3173588515291478806.stgit@brijesh-build-machine> <542CF652F8836A4AB8DBFAAD40ED192A4C569A29@shsmsx102.ccr.corp.intel.com> <542CF652F8836A4AB8DBFAAD40ED192A4C57C672@shsmsx102.ccr.corp.intel.com> From: Brijesh Singh Date: Mon, 27 Mar 2017 06:58:56 -0500 Message-ID: To: "Fan, Jeff" Cc: Laszlo Ersek , "Kinney, Michael D" , "Justen, Jordan L" , "edk2-devel@ml01.01.org" , "Gao, Liming" , "leo.duran@amd.com" , "brijesh.singh@amd.com" , "Thomas.Lendacky@amd.com" X-Content-Filtered-By: Mailman/MimeDel 2.1.22 Subject: Re: [RFC PATCH v2 01/10] OvmfPkg/Include: Define SEV specific CPUID and MSR X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 27 Mar 2017 11:58:58 -0000 Content-Type: text/plain; charset=UTF-8 On Mon, Mar 27, 2017 at 2:57 AM, Fan, Jeff wrote: > Laszlo, > > One Amd directory under UefiCpuPkg/Include/Register is better. > > Does Brijesh/Leo have any comments, or have other suggestions? > > I am not sure if creating a new UefiCpuPkg/Include/Register/Amd/Cpuid is a good idea, CPUID Fn8000_001F leaf can go in UefiCpuPkg/Include/Register/Cpuid.h. Looking at UefiCpuPkg/Include/Register/Cpuid.h indicates that this file defines the standard x86 CPUID's. The definition of CPUID's listed in this file are same on both Intel and AMD platforms. I was told by our architecture team that if Intel ever decides to support the new leaf then it will comply to the exact same bit definition. I am a bit unsure about where the MSR_SEV_STATUS should go, one part of me thinks that this MSR should be defined in OvmfPkg and other part thinks that it can go into UefiCpuPkg/Include/Amd/Msr.h. It is a read-only MSR and has meaning in a virtualization context hence I was more inclined towards defining into OvmfPkg instead of UefiCpuPkg. Leo, any comments/suggestions ? -Brijesh > -----Original Message----- > From: Laszlo Ersek [mailto:lersek@redhat.com] > Sent: Thursday, March 23, 2017 5:20 PM > To: Fan, Jeff; Brijesh Singh; Kinney, Michael D; Justen, Jordan L; > edk2-devel@ml01.01.org; Gao, Liming > Cc: leo.duran@amd.com; brijesh.singh@amd.com; Thomas.Lendacky@amd.com > Subject: Re: [edk2] [RFC PATCH v2 01/10] OvmfPkg/Include: Define SEV > specific CPUID and MSR > > On 03/23/17 08:42, Fan, Jeff wrote: > > Laszlo, > > > > UefiCpuPkg/Include/Register/Cpuid.h defined the CPUID only described in > IA32 SDM. > > UefiCpuPkg/Include/Register/ArchitecturalMsr.h defined the IA32 > > Architectural MSRs in IA32 SDM UefiCpuPkg/Include/Register/Msr/xxxxMsr.h > defined the IA32 Model-specific MSRs in IA32 SDM. > > > > I am not sure if Brijesh/Leo has some idea to place SEV specific > CPUID/MSRs definitions. > > I think one new file or new folder is better. > > I agree, both would work for me. My main point is that this feature > depends on physical processor attributes, not on emulated (virtual) > hardware or on various hypervisors, plus it is defined in a public industry > spec, so it seems to belong under UefiCpuPkg, not OvmfPkg. > > How about > > UefiCpuPkg/Include/AmdRegister/Cpuid.h > UefiCpuPkg/Include/AmdRegister/ArchitecturalMsr.h > UefiCpuPkg/Include/AmdRegister/Msr/xxxxMsr.h > > or else: > > UefiCpuPkg/Include/Register/Amd/Cpuid.h > UefiCpuPkg/Include/Register/Amd/ArchitecturalMsr.h > UefiCpuPkg/Include/Register/Amd/Msr/xxxxMsr.h > > (as appropriate -- I'm not saying that this patch should create all of > these files / subdirectories at once). > > Thanks > Laszlo > > > > -----Original Message----- > > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of > > Laszlo Ersek > > Sent: Thursday, March 23, 2017 12:04 AM > > To: Brijesh Singh; Kinney, Michael D; Justen, Jordan L; > > edk2-devel@ml01.01.org; Gao, Liming; Fan, Jeff > > Cc: leo.duran@amd.com; brijesh.singh@amd.com; Thomas.Lendacky@amd.com > > Subject: Re: [edk2] [RFC PATCH v2 01/10] OvmfPkg/Include: Define SEV > > specific CPUID and MSR > > > > Adding Jeff > > > > On 03/21/17 22:12, Brijesh Singh wrote: > >> The patch defines AMD's Memory Encryption Information CPUID leaf > (0x8000_001F). > >> The complete description for this CPUID leaf is available in APM > >> volume 2 [1] Section 15.34 (Secure Encrypted Virtualization). > >> > >> [1] http://support.amd.com/TechDocs/24593.pdf > >> > >> Signed-off-by: Brijesh Singh > >> --- > >> OvmfPkg/Include/Register/AmdSevMap.h | 133 > >> ++++++++++++++++++++++++++++++++++ > >> 1 file changed, 133 insertions(+) > >> create mode 100644 OvmfPkg/Include/Register/AmdSevMap.h > >> > >> diff --git a/OvmfPkg/Include/Register/AmdSevMap.h > >> b/OvmfPkg/Include/Register/AmdSevMap.h > >> new file mode 100644 > >> index 0000000..de80f39 > >> --- /dev/null > >> +++ b/OvmfPkg/Include/Register/AmdSevMap.h > >> @@ -0,0 +1,133 @@ > >> +/** @file > >> + > >> +AMD Secure Encrypted Virtualization (SEV) specific CPUID and MSR > >> +definitions > >> + > >> +The complete description for this CPUID leaf is available in APM > >> +volume 2 (Section 15.34) http://support.amd.com/TechDocs/24593.pdf > >> + > >> +Copyright (c) 2017, Advanced Micro Devices. All rights reserved.
> >> + > >> +This program and the accompanying materials are licensed and made > >> +available under the terms and conditions of the BSD License which > >> +accompanies this distribution. The full text of the license may be > >> +found at http://opensource.org/licenses/bsd-license.php > >> + > >> +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" > >> +BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER > EXPRESS OR IMPLIED. > >> + > >> +**/ > >> + > >> +#ifndef __AMD_SEV_MAP_H__ > >> +#define __AMD_SEV_MAP_H__ > >> + > >> +#pragma pack (1) > >> + > >> +#define CPUID_MEMORY_ENCRYPTION_INFO 0x8000001F > >> + > >> +/** > >> + CPUID Memory Encryption support information EAX for CPUID leaf > >> + #CPUID_MEMORY_ENCRYPTION_INFO. > >> +**/ > >> +typedef union { > >> + /// > >> + /// Individual bit fields > >> + /// > >> + struct { > >> + /// > >> + /// [Bit 0] Secure Memory Encryption (Sme) Support > >> + /// > >> + UINT32 SmeBit:1; > >> + > >> + /// > >> + /// [Bit 1] Secure Encrypted Virtualization (Sev) Support > >> + /// > >> + UINT32 SevBit:1; > >> + > >> + /// > >> + /// [Bit 2] Page flush MSR support > >> + /// > >> + UINT32 PageFlushMsrBit:1; > >> + > >> + /// > >> + /// [Bit 3] Encrypted state support > >> + /// > >> + UINT32 SevEsBit:1; > >> + > >> + /// > >> + /// [Bit 4:31] Reserved > >> + /// > >> + UINT32 ReservedBits:28; > >> + } Bits; > >> + /// > >> + /// All bit fields as a 32-bit value > >> + /// > >> + UINT32 Uint32; > >> +} CPUID_MEMORY_ENCRYPTION_INFO_EAX; > >> + > >> +/** > >> + CPUID Memory Encryption support information EBX for CPUID leaf > >> + #CPUID_MEMORY_ENCRYPTION_INFO. > >> +**/ > >> +typedef union { > >> + /// > >> + /// Individual bit fields > >> + /// > >> + struct { > >> + /// > >> + /// [Bit 0:5] Page table bit number used to enable memory > encryption > >> + /// > >> + UINT32 PtePosBits:6; > >> + > >> + /// > >> + /// [Bit 6:11] Reduction of system physical address space bits > when memory encryption is enabled > >> + /// > >> + UINT32 ReducedPhysBits:5; > >> + > >> + /// > >> + /// [Bit 12:31] Reserved > >> + /// > >> + UINT32 ReservedBits:21; > >> + } Bits; > >> + /// > >> + /// All bit fields as a 32-bit value > >> + /// > >> + UINT32 Uint32; > >> +} CPUID_MEMORY_ENCRYPTION_INFO_EBX; > >> + > >> +/** > >> + Secure Encrypted Virtualization (SEV) status register > >> + > >> +**/ > >> +#define MSR_SEV_STATUS 0xc0010131 > >> + > >> +/** > >> + MSR information returned for #MSR_SEV_STATUS **/ typedef union { > >> + /// > >> + /// Individual bit fields > >> + /// > >> + struct { > >> + /// > >> + /// [Bit 0] Secure Encrypted Virtualization (Sev) is enabled > >> + /// > >> + UINT32 SevBit:1; > >> + > >> + /// > >> + /// [Bit 1] Secure Encrypted Virtualization Encrypted State > (SevEs) is enabled > >> + /// > >> + UINT32 SevEsBit:1; > >> + > >> + UINT32 Reserved:30; > >> + } Bits; > >> + /// > >> + /// All bit fields as a 32-bit value > >> + /// > >> + UINT32 Uint32; > >> + /// > >> + /// All bit fields as a 64-bit value > >> + /// > >> + UINT64 Uint64; > >> +} MSR_SEV_STATUS_REGISTER; > >> + > >> +#endif > >> > >> _______________________________________________ > >> edk2-devel mailing list > >> edk2-devel@lists.01.org > >> https://lists.01.org/mailman/listinfo/edk2-devel > >> > > > > I feel that these definitions should be added to > "UefiCpuPkg/Include/Register/Cpuid.h", or else to another (new) header > file in that directory. > > > > Jeff, what do you think? > > > > Thanks! > > Laszlo > > _______________________________________________ > > edk2-devel mailing list > > edk2-devel@lists.01.org > > https://lists.01.org/mailman/listinfo/edk2-devel > > > >