From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qk0-x242.google.com (mail-qk0-x242.google.com [IPv6:2607:f8b0:400d:c09::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id EC9C980350 for ; Tue, 7 Mar 2017 10:43:26 -0800 (PST) Received: by mail-qk0-x242.google.com with SMTP id o135so3458350qke.2 for ; Tue, 07 Mar 2017 10:43:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=8CM71E8XwfXiUvtt/0EYSR9j6J7Xo4ZM9KtIPJGoMzU=; b=ulRmGsn1yGvA8qa55KzuGrFkZXjAKpeP9OfuUhiV2ZBBUiYIigbecsqFqtfF2VRSJ3 sHg4nud3gCVVkhLEQgO/1lD6ApnBqhPyUcORuz5DCMdK/P9RKB848FLEW7SraQEr+Kks YNXbFAx2bjnoYVJSrPgTYAA8ekl4BkHZtCKLqTMNIn2GFL68Su7Ol11U/JUw1dSJWT0K 3YeBXgyEl8Ljv1td0UZM0Q7P9XIT1sUC1aN6Lk75M2CI2Ho3de6u+tPAUOMvQuCMTyDN P4aN8o+8++91PDk1DKXs9KCE6D9RthRREhCuJlARuFCdpTZR+tbgW27GGL0iwLxfguQR a+2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=8CM71E8XwfXiUvtt/0EYSR9j6J7Xo4ZM9KtIPJGoMzU=; b=A6ANFZ93oiw7MnwZwBLME7Bg6WlXRsBGn0bu6d5CyPh1obsSdix5CLrxK4XeTNfpGZ y/f5GGMb5BHUTMVNQjls3JQsLEAi7ptlNJ5dL2tYGkq/pIdmifTVypoobnKa7fRbYs2Y kEUqMflw+Dc4geVDV2BYbfFXI1+t1ZCsiQ/MNXNDmlR7KGwtBsKnmzUcGIasMAHjZ09J DfOYc904j9oi73zr23ZChzWKTkELTbivC/oq2K6JSD1HuyCcdcRI5fzZzZFSRPYH97CE r15KkhUZjbE0YYWMVsYaeS3k4SbaQtaTGoRKYQLWC1z2MiY1LKAQPsl9e7PC6GI0S8Fc T0AQ== X-Gm-Message-State: AMke39mKayAwL2sibmaYzGHajxjOc0IZrjlqUHL2Csxr27WaPDqVbOm/J9E43kuohd5YX5GUf1650EZZ2mSWNw== X-Received: by 10.200.48.171 with SMTP id v40mr2428089qta.80.1488912205984; Tue, 07 Mar 2017 10:43:25 -0800 (PST) MIME-Version: 1.0 Received: by 10.12.182.65 with HTTP; Tue, 7 Mar 2017 10:43:25 -0800 (PST) In-Reply-To: <5a66f334-27e1-3b49-150e-c01209ecb2f6@amd.com> References: <148884284887.29188.7643544710695103939.stgit@brijesh-build-machine> <148884288152.29188.17347075963122121328.stgit@brijesh-build-machine> <5a66f334-27e1-3b49-150e-c01209ecb2f6@amd.com> From: Brijesh Singh Date: Tue, 7 Mar 2017 12:43:25 -0600 Message-ID: To: Tom Lendacky Cc: jordan.l.justen@intel.com, edk2-devel@ml01.01.org, lersek@redhat.com, Leo Duran , brijesh.singh@amd.com X-Content-Filtered-By: Mailman/MimeDel 2.1.21 Subject: Re: [RFC PATCH v1 5/5] OvmfPkg/BaseIoLibIntrinsic: Unroll String I/O when SEV is active X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 07 Mar 2017 18:43:27 -0000 Content-Type: text/plain; charset=UTF-8 On Tue, Mar 7, 2017 at 10:49 AM, Tom Lendacky wrote: > On 3/6/2017 5:28 PM, Brijesh Singh wrote: > >> Secure Encrypted Virtualization (SEV) does not support string I/O, so >> unroll the string I/O operation into a loop operating on one element at >> a time. >> >> Contributed-under: TianoCore Contribution Agreement 1.0 >> Signed-off-by: Brijesh Singh >> --- >> .../BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf | 3 >> .../Library/BaseIoLibIntrinsic/Ia32/IoFifo.nasm | 19 +++ >> .../Library/BaseIoLibIntrinsic/Ia32/SevIoFifo.nasm | 141 >> ++++++++++++++++++++ >> OvmfPkg/Library/BaseIoLibIntrinsic/X64/IoFifo.nasm | 19 +++ >> .../Library/BaseIoLibIntrinsic/X64/SevIoFifo.nasm | 143 >> ++++++++++++++++++++ >> 5 files changed, 324 insertions(+), 1 deletion(-) >> create mode 100644 OvmfPkg/Library/BaseIoLibIntri >> nsic/Ia32/SevIoFifo.nasm >> create mode 100644 OvmfPkg/Library/BaseIoLibIntrinsic/X64/SevIoFifo.nasm >> >> diff --git a/OvmfPkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf >> b/OvmfPkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf >> index 8844b1c..e7eeb59 100644 >> --- a/OvmfPkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf >> +++ b/OvmfPkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf >> @@ -28,7 +28,6 @@ >> VERSION_STRING = 1.0 >> LIBRARY_CLASS = IoLib >> >> - >> # >> # VALID_ARCHITECTURES = IA32 X64 EBC IPF ARM AARCH64 >> # >> @@ -45,6 +44,7 @@ >> IoLib.c >> Ia32/IoFifo.nasm >> Ia32/IoFifo.asm >> + Ia32/SevIoFifo.nasm >> >> [Sources.X64] >> IoLibGcc.c | GCC >> @@ -53,6 +53,7 @@ >> IoLib.c >> X64/IoFifo.nasm >> X64/IoFifo.asm >> + X64/SevIoFifo.nasm >> >> [Sources.EBC] >> IoLibEbc.c >> diff --git a/OvmfPkg/Library/BaseIoLibIntrinsic/Ia32/IoFifo.nasm >> b/OvmfPkg/Library/BaseIoLibIntrinsic/Ia32/IoFifo.nasm >> index bcaa743..fb585e6 100644 >> --- a/OvmfPkg/Library/BaseIoLibIntrinsic/Ia32/IoFifo.nasm >> +++ b/OvmfPkg/Library/BaseIoLibIntrinsic/Ia32/IoFifo.nasm >> @@ -13,6 +13,10 @@ >> ; >> ;---------------------------------------------------------- >> -------------------- >> >> + EXTERN ASM_PFX(SevIoReadFifo8) >> + EXTERN ASM_PFX(SevIoReadFifo16) >> + EXTERN ASM_PFX(SevIoReadFifo32) >> + >> SECTION .text >> >> ;---------------------------------------------------------- >> -------------------- >> @@ -31,7 +35,12 @@ ASM_PFX(IoReadFifo8): >> mov dx, [esp + 8] >> mov ecx, [esp + 12] >> mov edi, [esp + 16] >> + call SevIoReadFifo8 >> > > Maybe just add a comment here (and in the other places) that if SEV > isn't active we drop through and perform the "rep" form of the > instruction. > > Thanks, I will add comments in next rev.