From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-qk1-f177.google.com (mail-qk1-f177.google.com [209.85.222.177]) by mx.groups.io with SMTP id smtpd.web11.7303.1625809009646493066 for ; Thu, 08 Jul 2021 22:36:49 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=fGWwbTzc; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.222.177, mailfrom: gjb@semihalf.com) Received: by mail-qk1-f177.google.com with SMTP id b18so8233266qkc.5 for ; Thu, 08 Jul 2021 22:36:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=CSgrEi7oPRPh62+KRaJSKRjyrBA616zyghKCiiupPzU=; b=fGWwbTzcXpGaxTTcypDcaCHDL9TGOcfq4j3igWW3bP1TdKT8jhJQI2DPbBv3t8z9D/ xUHVvs+uJ30iMUm9JM7vAJv9O3f9gdXbvnw37jC0irAVs9k7yeS9Lv3XXBJacgRM38hs JydHQsu6gIuhFjX6vsZhYn+Oe8rcqHsf9LYKwcw83d53S3G6V8xGxPzz8orXuauDlhXS UEOE1ZVH96X6Q9rQUmz96JWsDHqVy6w5PBOX2vgTbfOfgXER4aHjWrqpcLlTDbZww+Mu mUNphedMP403X5aHxkGlBE+vBK0Wm5Buc7F6j1Jed+bSaNzKg21QPAbQ47HsgRJ9U748 mKDA== X-Google-DKIM-Signature: v=1; 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Tested-by: Grzegorz Bernacki regards, greg niedz., 13 cze 2021 o 20:17 Marcin Wojtas napisa=C5=82(a)= : > > As the MDIO ACPI binding in DSDT is now established, > add description for the SMI controller, along with the 1G PHYs. > Add also a missing 'managed' property to the 10G ports. > > Signed-off-by: Marcin Wojtas > --- > Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl | 1 + > Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 24 ++++++++= ++++++++++++ > 2 files changed, 25 insertions(+) > > diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl b= /Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl > index 691a709c18..8377b13763 100644 > --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl > +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl > @@ -91,6 +91,7 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU= ", "CN9131", 3) > Package () { "port-id", 0 }, > Package () { "gop-port-id", 0 }, > Package () { "phy-mode", "10gbase-kr"}, > + Package () { "managed", "in-band-status"}, > } > }) > } > diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl b= /Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl > index 30de868907..d76a2a902b 100644 > --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl > +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl > @@ -185,6 +185,27 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "C= N9130", 3) > }) > } > > + Device (SMI0) > + { > + Name (_HID, "MRVL0100") // _HID:= Hardware ID > + Name (_UID, 0x00) // _UID:= Unique ID > + Name (_CRS, ResourceTemplate () > + { > + Memory32Fixed (ReadWrite, > + 0xf212a200, // Addre= ss Base > + 0x00000010, // Addre= ss Length > + ) > + }) > + Device (PHY0) > + { > + Name (_ADR, 0x0) > + } > + Device (PHY1) > + { > + Name (_ADR, 0x1) > + } > + } > + > Device (PP20) > { > Name (_HID, "MRVL0110") // _HID:= Hardware ID > @@ -218,6 +239,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN= 9130", 3) > Package () { "port-id", 0 }, > Package () { "gop-port-id", 0 }, > Package () { "phy-mode", "10gbase-kr"}, > + Package () { "managed", "in-band-status"}, > } > }) > } > @@ -237,6 +259,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN= 9130", 3) > Package () { "port-id", 1 }, > Package () { "gop-port-id", 2 }, > Package () { "phy-mode", "rgmii-id"}, > + Package () { "phy-handle", \_SB.SMI0.PHY0}, > } > }) > } > @@ -256,6 +279,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN= 9130", 3) > Package () { "port-id", 2 }, > Package () { "gop-port-id", 3 }, > Package () { "phy-mode", "rgmii-id"}, > + Package () { "phy-handle", \_SB.SMI0.PHY1}, > } > }) > } > -- > 2.29.0 >