From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-qk1-f172.google.com (mail-qk1-f172.google.com [209.85.222.172]) by mx.groups.io with SMTP id smtpd.web10.42370.1675089202487161323 for ; Mon, 30 Jan 2023 06:33:22 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@rivosinc-com.20210112.gappssmtp.com header.s=20210112 header.b=dshix0eh; spf=pass (domain: rivosinc.com, ip: 209.85.222.172, mailfrom: dhaval@rivosinc.com) Received: by mail-qk1-f172.google.com with SMTP id l1so5229524qkg.11 for ; Mon, 30 Jan 2023 06:33:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=pdwATXikNjoWkLs+yZU/TBA/3mKuwdGjeb2FQaNzl4k=; b=dshix0ehWr3SWxPGEr/1i+fAFdiS9Mjg4ob3KAwjB1B/HnisHnLeHijrW5wIxbOabg c8dQ/ZQ5UTQzrGZo7ExVZIB2XGVosfvy16xK4W28RrTtUtkNzkDRTwi8Nk6pClkSGv/E UfqJ8piFGNvG4xNXjvXhn8tNfwB6zhVHT+DUzoJshD7r7of/j62cHaW9Z39KmF1/iT+x XkCRlFwnpdGeTQW2mu9GTR4+g1MSELt9PexcYW+kDEAn5fU0UXQKI7CC6Q8owPxRua/Z Dk+ul+qYUebSyzX15wq0ynLbkjg0IRlh+wBH4c/BiulhVVZXCc4Fi0dLYbaiBtgfPKwO azQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=pdwATXikNjoWkLs+yZU/TBA/3mKuwdGjeb2FQaNzl4k=; b=CgrIS0JdYnfD7tNgiryu8v/JNjgLIO/J0Od2ow8+srx3BNwlePgPYV6LCkpIfMdWM8 5+RhaqVQAJBWnhynBVeF16HozwDxvtNfBQfl6E1j6X9q+pjV7bJ95eV0JmZkAIu0jKw/ OD0U02kj6XuEGpSMpPXbmqTKnxEmyOHT1YEwbW8YOMy9U6hVBXTXWRmIlxWznLsKSxG3 fDuifvgaGMS6IHyOnXq1uVxxrvCD//VwIfO6B75ylA7H+FhQIl17TzIFMxp2liKRy82p KrMLjaw47mlqHtLfx/jclAj6RX4Gf5KaWxGn8bonjQXkKb6bcgkhhNop/RyT/ogUVACr nM6A== X-Gm-Message-State: AO0yUKV8rPBR4ScgYXmir1W6IE4b8wU9GvFNyrf1tJ2qsUNWhoUMdBa7 qUXdcoMsvymfi2Lsja3vxNp5iKqChpN9n+1rRzz67tCI2zukiRJl X-Google-Smtp-Source: AK7set9IyJstJ3o7WEI7gwzFln/z0pga5js8d0VMf5o83iKEYsPQoJmyjl7n2YiXaPjOzs9Q3SNWqtWPbamSGNKMGco= X-Received: by 2002:a05:620a:458f:b0:71d:a728:9d1d with SMTP id bp15-20020a05620a458f00b0071da7289d1dmr382233qkb.243.1675089201425; Mon, 30 Jan 2023 06:33:21 -0800 (PST) MIME-Version: 1.0 References: <20230128191807.2080547-18-sunilvl@ventanamicro.com> <26729.1675073578100850032@groups.io> In-Reply-To: From: dhaval@rivosinc.com Date: Mon, 30 Jan 2023 20:03:10 +0530 Message-ID: Subject: Re: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V7 17/20] OvmfPkg/RiscVVirt: Add PciCpuIo2Dxe module To: Sunil V L Cc: devel@edk2.groups.io Content-Type: multipart/alternative; boundary="000000000000d1866a05f37c1874" --000000000000d1866a05f37c1874 Content-Type: text/plain; charset="UTF-8" Okay. So I am fine with that stepped approach- let us please make a list of such items that we are deciding on doing in the next version so that we can track them? On Mon, Jan 30, 2023 at 6:35 PM Sunil V L wrote: > On Mon, Jan 30, 2023 at 02:12:58AM -0800, dhaval@rivosinc.com wrote: > > What I see in the current implementation is: > > > > * UEFICpuPkg implements gEfiCpuIo2ProtocolGuid which does not seem to be > generic. > > * ARMPkg implements it which seems similar to what RV needs. > > > Yes, this is exact copy of the ArmPkg version. I guess Loongarch also will > need the same. > > > Do we really expect this to be platform specific implementation and > hence it should be in respective platform folders? Neither x86/ARM seem to > follow this model? > > Correct. Both real and virtual platforms would need it. But adding > inside UefiCpuPkg/CpuI02Dxe looked bit messy which needs bit more > discussion and not sure whether it is a good idea to create parallel to > CpuIo2Dxe. So, I thought it is better to add it in RiscVVirt for now > instead of delaying the virt support even further. Let us take that as a > separate activity after this series with inputs from different CPU > architectures. > > Thanks > Sunil > > > -- Thanks! =D --000000000000d1866a05f37c1874 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Okay. So I am fine with that stepped approach- let us plea= se make a list of such items that we are deciding on doing in the next vers= ion so that we can track them?

On Mon, Jan 30, 2023 at 6:35 PM Sunil V L <= ;sunilvl@ventanamicro.com&g= t; wrote:
On Mon= , Jan 30, 2023 at 02:12:58AM -0800, dhaval@rivosinc.com wrote:
> What I see in the current implementation is:
>
> * UEFICpuPkg implements gEfiCpuIo2ProtocolGuid which does not seem to = be generic.
> * ARMPkg implements it which seems similar to what RV needs.
>
Yes, this is exact copy of the ArmPkg version. I guess Loongarch also will = need the same.

> Do we really expect this to be platform specific implementation and he= nce it should be in respective platform folders? Neither x86/ARM seem to fo= llow this model?

Correct. Both real and virtual platforms would need it. But adding
inside UefiCpuPkg/CpuI02Dxe looked bit messy which needs bit more
discussion and not sure whether it is a good idea to create parallel to
CpuIo2Dxe. So, I thought it is better to add it in RiscVVirt for now
instead of delaying the virt support even further. Let us take that as a separate activity after this series with inputs from different CPU
architectures.

Thanks
Sunil




--
Thanks!
=3DD
--000000000000d1866a05f37c1874--