* [edk2-devel] [PATCH v6 0/5] Cache Management Operations Support For RISC-V
@ 2023-10-21 17:33 Dhaval Sharma
2023-10-21 17:33 ` [edk2-devel] [PATCH v6 1/5] MdePkg: Move RISC-V Cache Management Declarations Into BaseLib Dhaval Sharma
` (4 more replies)
0 siblings, 5 replies; 13+ messages in thread
From: Dhaval Sharma @ 2023-10-21 17:33 UTC (permalink / raw)
To: devel
Cc: Ard Biesheuvel, Jiewen Yao, Jordan Justen, Gerd Hoffmann,
Sunil V L, Andrei Warkentin, Laszlo Ersek, Michael D Kinney,
Liming Gao, Zhiguang Liu, Daniel Schaefer
Implementing code to support Cache Management Operations (CMO) defined by
RISC-V CMO instructions.https://github.com/riscv/riscv-CMOs
This is a re-write of original series v5.
The patchset contains 5 patches- created based on V5 feedback.
1. Restructuring of existing code and move instruction declarations into BaseLib
2. Renaming existing functions to denote type of instruction used to maanage cache.
This is useful for further patches where more cache management instructions are added.
3. Add the new cache maintenance operations to BaseLib, including the
new assembly instruction encodings.
4. Update BaseCacheMaintenanceLib (utilizing the new BaseLib primitives)
5. Add platform level PCD to allow overriding of RISC-V features.
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Andrei Warkentin <andrei.warkentin@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Daniel Schaefer <git@danielschaefer.me>
Dhaval (5):
MdePkg: Move RISC-V Cache Management Declarations Into BaseLib
MdePkg: Rename Cache Management Function To Clarify Fence Based Op
MdePkg: Implement RISC-V Cache Management Operations
MdePkg: Utilize Cache Management Operations Implementation For RISC-V
OvmfPkg/RiscVVirt: Override for RV CPU Features
MdePkg/MdePkg.dec | 8 +
OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 +
MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf | 2 +
MdePkg/Library/BaseLib/BaseLib.inf | 2 +-
MdePkg/Include/Library/BaseLib.h | 53 +++++++
MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 163 ++++++++++++++++----
MdePkg/Include/RiscV64/RiscVasm.inc | 19 +++
MdePkg/Library/BaseLib/RiscV64/FlushCache.S | 21 ---
MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S | 38 +++++
MdePkg/MdePkg.uni | 4 +
10 files changed, 258 insertions(+), 53 deletions(-)
create mode 100644 MdePkg/Include/RiscV64/RiscVasm.inc
delete mode 100644 MdePkg/Library/BaseLib/RiscV64/FlushCache.S
create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S
--
2.39.2
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* [edk2-devel] [PATCH v6 1/5] MdePkg: Move RISC-V Cache Management Declarations Into BaseLib
2023-10-21 17:33 [edk2-devel] [PATCH v6 0/5] Cache Management Operations Support For RISC-V Dhaval Sharma
@ 2023-10-21 17:33 ` Dhaval Sharma
2023-10-24 12:32 ` Laszlo Ersek
2023-10-21 17:33 ` [edk2-devel] [PATCH v6 2/5] MdePkg: Rename Cache Management Function To Clarify Fence Based Op Dhaval Sharma
` (3 subsequent siblings)
4 siblings, 1 reply; 13+ messages in thread
From: Dhaval Sharma @ 2023-10-21 17:33 UTC (permalink / raw)
To: devel; +Cc: Michael D Kinney, Liming Gao, Zhiguang Liu, Laszlo Ersek
The declarations for cache Management functions belong to BaseLib
instead of instance source file. This helps with further restructuring
of cache management code for RISC-V.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
---
Notes:
V5:
- Move cache management function declaration in baselib where it belongs
MdePkg/Include/Library/BaseLib.h | 20 ++++++++++++++++++++
MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 20 --------------------
2 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 5d7067ee854e..7142bbfa42f2 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -206,6 +206,26 @@ RiscVClearPendingTimerInterrupt (
VOID
);
+/**
+ RISC-V invalidate instruction cache.
+
+**/
+VOID
+EFIAPI
+RiscVInvalidateInstCacheAsm (
+ VOID
+ );
+
+/**
+ RISC-V invalidate data cache.
+
+**/
+VOID
+EFIAPI
+RiscVInvalidateDataCacheAsm (
+ VOID
+ );
+
#endif // defined (MDE_CPU_RISCV64)
#if defined (MDE_CPU_LOONGARCH64)
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
index d08fb9f193ca..d5efcf49a4bf 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
@@ -10,26 +10,6 @@
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
-/**
- RISC-V invalidate instruction cache.
-
-**/
-VOID
-EFIAPI
-RiscVInvalidateInstCacheAsm (
- VOID
- );
-
-/**
- RISC-V invalidate data cache.
-
-**/
-VOID
-EFIAPI
-RiscVInvalidateDataCacheAsm (
- VOID
- );
-
/**
Invalidates the entire instruction cache in cache coherency domain of the
calling CPU.
--
2.39.2
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* [edk2-devel] [PATCH v6 2/5] MdePkg: Rename Cache Management Function To Clarify Fence Based Op
2023-10-21 17:33 [edk2-devel] [PATCH v6 0/5] Cache Management Operations Support For RISC-V Dhaval Sharma
2023-10-21 17:33 ` [edk2-devel] [PATCH v6 1/5] MdePkg: Move RISC-V Cache Management Declarations Into BaseLib Dhaval Sharma
@ 2023-10-21 17:33 ` Dhaval Sharma
2023-10-24 12:34 ` Laszlo Ersek
2023-10-21 17:33 ` [edk2-devel] [PATCH v6 3/5] MdePkg: Implement RISC-V Cache Management Operations Dhaval Sharma
` (2 subsequent siblings)
4 siblings, 1 reply; 13+ messages in thread
From: Dhaval Sharma @ 2023-10-21 17:33 UTC (permalink / raw)
To: devel
Cc: Michael D Kinney, Liming Gao, Zhiguang Liu, Sunil V L,
Daniel Schaefer, Laszlo Ersek
There are different ways to manage cache on RISC-V Processors.
One way is to use fence instruction. Another way is to use CPU
specific cache management operation instructions ratified as
per RISC-V ISA specifications to be introduced in future
patches. Current method is fence instruction based, rename the
function accordingly to add that clarity.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <git@danielschaefer.me>
Cc: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
---
Notes:
V6:
- As part of restructuring, adding cache instruction differentiation
in function naming
MdePkg/Include/Library/BaseLib.h | 4 ++--
MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 4 ++--
MdePkg/Library/BaseLib/RiscV64/FlushCache.S | 8 ++++----
3 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 7142bbfa42f2..d4b56a9601da 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -212,7 +212,7 @@ RiscVClearPendingTimerInterrupt (
**/
VOID
EFIAPI
-RiscVInvalidateInstCacheAsm (
+RiscVInvalidateInstCacheAsmFence (
VOID
);
@@ -222,7 +222,7 @@ RiscVInvalidateInstCacheAsm (
**/
VOID
EFIAPI
-RiscVInvalidateDataCacheAsm (
+RiscVInvalidateDataCacheAsmFence (
VOID
);
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
index d5efcf49a4bf..4eb18edb9aa7 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
@@ -21,7 +21,7 @@ InvalidateInstructionCache (
VOID
)
{
- RiscVInvalidateInstCacheAsm ();
+ RiscVInvalidateInstCacheAsmFence ();
}
/**
@@ -193,7 +193,7 @@ InvalidateDataCache (
VOID
)
{
- RiscVInvalidateDataCacheAsm ();
+ RiscVInvalidateDataCacheAsmFence ();
}
/**
diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
index 7c10fdd268af..e0eea0b5fb25 100644
--- a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
+++ b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
@@ -9,13 +9,13 @@
//------------------------------------------------------------------------------
.align 3
-ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsm)
-ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsm)
+ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsmFence)
+ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsmFence)
-ASM_PFX(RiscVInvalidateInstCacheAsm):
+ASM_PFX(RiscVInvalidateInstCacheAsmFence):
fence.i
ret
-ASM_PFX(RiscVInvalidateDataCacheAsm):
+ASM_PFX(RiscVInvalidateDataCacheAsmFence):
fence
ret
--
2.39.2
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* [edk2-devel] [PATCH v6 3/5] MdePkg: Implement RISC-V Cache Management Operations
2023-10-21 17:33 [edk2-devel] [PATCH v6 0/5] Cache Management Operations Support For RISC-V Dhaval Sharma
2023-10-21 17:33 ` [edk2-devel] [PATCH v6 1/5] MdePkg: Move RISC-V Cache Management Declarations Into BaseLib Dhaval Sharma
2023-10-21 17:33 ` [edk2-devel] [PATCH v6 2/5] MdePkg: Rename Cache Management Function To Clarify Fence Based Op Dhaval Sharma
@ 2023-10-21 17:33 ` Dhaval Sharma
2023-10-24 12:39 ` Laszlo Ersek
2023-10-21 17:33 ` [edk2-devel] [PATCH v6 4/5] MdePkg: Utilize Cache Management Operations Implementation For RISC-V Dhaval Sharma
2023-10-21 17:33 ` [edk2-devel] [PATCH v6 5/5] OvmfPkg/RiscVVirt: Override for RV CPU Features Dhaval Sharma
4 siblings, 1 reply; 13+ messages in thread
From: Dhaval Sharma @ 2023-10-21 17:33 UTC (permalink / raw)
To: devel
Cc: Michael D Kinney, Liming Gao, Zhiguang Liu, Sunil V L,
Daniel Schaefer, Laszlo Ersek
Implement Cache Management Operations (CMO) defined by
RISC-V spec https://github.com/riscv/riscv-CMOs.
Notes:
1. CMO only supports block based Operations. Meaning cache
flush/invd/clean Operations are not available for the entire
range. In that case we fallback on fence.i instructions.
2. Operations are implemented using Opcodes to make them compiler
independent. binutils 2.39+ compilers support CMO instructions.
Test:
1. Ensured correct instructions are refelecting in asm
2. Not able to verify actual instruction in HW as Qemu ignores
any actual cache operations.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <git@danielschaefer.me>
Cc: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
---
Notes:
V1:
- Implement Cache management instructions in Baselib
MdePkg/Library/BaseLib/BaseLib.inf | 2 +-
MdePkg/Include/Library/BaseLib.h | 33 ++++++++++++++++++++
MdePkg/Include/RiscV64/RiscVasm.inc | 19 +++++++++++
MdePkg/Library/BaseLib/RiscV64/{FlushCache.S => RiscVCacheMgmt.S} | 17 ++++++++++
4 files changed, 70 insertions(+), 1 deletion(-)
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index 03c7b02e828b..53389389448c 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -400,7 +400,7 @@ [Sources.RISCV64]
RiscV64/RiscVCpuBreakpoint.S | GCC
RiscV64/RiscVCpuPause.S | GCC
RiscV64/RiscVInterrupt.S | GCC
- RiscV64/FlushCache.S | GCC
+ RiscV64/RiscVCacheMgmt.S | GCC
RiscV64/CpuScratch.S | GCC
RiscV64/ReadTimer.S | GCC
RiscV64/RiscVMmu.S | GCC
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index d4b56a9601da..60d60602b876 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -226,6 +226,39 @@ RiscVInvalidateDataCacheAsmFence (
VOID
);
+/**
+ RISC-V flush cache block. Atomically perform a clean operation
+ followed by an invalidate operation
+
+**/
+VOID
+EFIAPI
+RiscVCpuCacheFlushAsmCbo (
+ IN UINTN
+ );
+
+/**
+Perform a write transfer to another cache or to memory if the
+data in the copy of the cache block have been modified by a store
+operation
+
+**/
+VOID
+EFIAPI
+RiscVCpuCacheCleanAsmCbo (
+ IN UINTN
+ );
+
+/**
+Deallocate the copy of the cache block
+
+**/
+VOID
+EFIAPI
+RiscVCpuCacheInvalAsmCbo (
+ IN UINTN
+ );
+
#endif // defined (MDE_CPU_RISCV64)
#if defined (MDE_CPU_LOONGARCH64)
diff --git a/MdePkg/Include/RiscV64/RiscVasm.inc b/MdePkg/Include/RiscV64/RiscVasm.inc
new file mode 100644
index 000000000000..6f418232d507
--- /dev/null
+++ b/MdePkg/Include/RiscV64/RiscVasm.inc
@@ -0,0 +1,19 @@
+/*
+ *
+ * RISC-V cache operation encoding.
+ * Copyright (c) 2023, Rivos Inc. All rights reserved.<BR>
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ */
+
+.macro RISCVCBOFLSH
+ .word 0x25200f
+.endm
+
+.macro RISCVCBOINVD
+ .word 0x05200f
+.endm
+
+.macro RISCVCBOCLEN
+ .word 0x15200f
+.endm
diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S b/MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S
similarity index 57%
rename from MdePkg/Library/BaseLib/RiscV64/FlushCache.S
rename to MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S
index e0eea0b5fb25..fe3943ae3f7c 100644
--- a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
+++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S
@@ -3,10 +3,12 @@
// RISC-V cache operation.
//
// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+// Copyright (c) 2023, Rivos Inc. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
//------------------------------------------------------------------------------
+.include "RiscVasm.inc"
.align 3
ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsmFence)
@@ -19,3 +21,18 @@ ASM_PFX(RiscVInvalidateInstCacheAsmFence):
ASM_PFX(RiscVInvalidateDataCacheAsmFence):
fence
ret
+
+ASM_GLOBAL ASM_PFX (RiscVCpuCacheFlushAsmCbo)
+ASM_PFX (RiscVCpuCacheFlushAsmCbo):
+ RISCVCBOFLSH
+ ret
+
+ASM_GLOBAL ASM_PFX (RiscVCpuCacheCleanAsmCbo)
+ASM_PFX (RiscVCpuCacheCleanAsmCbo):
+ RISCVCBOCLEN
+ ret
+
+ASM_GLOBAL ASM_PFX (RiscVCpuCacheInvalAsmCbo)
+ASM_PFX (RiscVCpuCacheInvalAsmCbo):
+ RISCVCBOINVD
+ ret
--
2.39.2
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* [edk2-devel] [PATCH v6 4/5] MdePkg: Utilize Cache Management Operations Implementation For RISC-V
2023-10-21 17:33 [edk2-devel] [PATCH v6 0/5] Cache Management Operations Support For RISC-V Dhaval Sharma
` (2 preceding siblings ...)
2023-10-21 17:33 ` [edk2-devel] [PATCH v6 3/5] MdePkg: Implement RISC-V Cache Management Operations Dhaval Sharma
@ 2023-10-21 17:33 ` Dhaval Sharma
2023-10-24 12:45 ` Laszlo Ersek
2023-10-24 20:09 ` Pedro Falcato
2023-10-21 17:33 ` [edk2-devel] [PATCH v6 5/5] OvmfPkg/RiscVVirt: Override for RV CPU Features Dhaval Sharma
4 siblings, 2 replies; 13+ messages in thread
From: Dhaval Sharma @ 2023-10-21 17:33 UTC (permalink / raw)
To: devel; +Cc: Michael D Kinney, Liming Gao, Zhiguang Liu, Laszlo Ersek
Use newly defined cache management operations for RISC-V where possible
It builds up on the support added for RISC-V cache management
instructions in BaseLib.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
---
Notes:
V1:
- Utilize cache management instructions if HW supports it
This patch is part of restructuring on top of v5
MdePkg/MdePkg.dec | 8 +
MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf | 2 +
MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 159 +++++++++++++++++---
MdePkg/MdePkg.uni | 4 +
4 files changed, 154 insertions(+), 19 deletions(-)
diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index ac54338089e8..fa92673ff633 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -2399,6 +2399,14 @@ [PcdsFixedAtBuild.AARCH64, PcdsPatchableInModule.AARCH64]
# @Prompt CPU Rng algorithm's GUID.
gEfiMdePkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm|{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}|VOID*|0x00000037
+[PcdsFixedAtBuild.RISCV64, PcdsPatchableInModule.RISCV64]
+ #
+ # Configurability to override RISC-V CPU Features
+ # BIT 0 = Cache Management Operations. This bit is relevant only if
+ # previous stage has feature enabled and user wants to disable it.
+ #
+ gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFF|UINT64|0x69
+
[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
## This value is used to set the base address of PCI express hierarchy.
# @Prompt PCI Express Base Address.
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
index 6fd9cbe5f6c9..39a7fb963b49 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
@@ -56,3 +56,5 @@ [LibraryClasses]
BaseLib
DebugLib
+[Pcd.RISCV64]
+ gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride ## CONSUMES
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
index 4eb18edb9aa7..6851970c9e16 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
@@ -1,7 +1,8 @@
/** @file
- RISC-V specific functionality for cache.
+ Implement Risc-V Cache Management Operations
Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2023, Rivos Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -9,10 +10,111 @@
#include <Base.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+
+// TODO: This will be removed once RISC-V CPU HOB is available
+#define RISCV_CACHE_BLOCK_SIZE 64
+#define RISCV_CPU_FEATURE_CMO_BITMASK 0x1
+
+typedef enum {
+ Clean,
+ Flush,
+ Invld,
+} CACHE_OP;
+
+/**
+Verify CBOs are supported by this HW
+TODO: Use RISC-V CPU HOB once available.
+
+**/
+STATIC
+BOOLEAN
+RiscVIsCMOEnabled (
+ VOID
+ )
+{
+ // TODO: Add check for CMO from CPU HOB.
+ // If CMO is disabled in HW, skip Override check
+ // Otherwise this PCD can override settings
+ return ((PcdGet64 (PcdRiscVFeatureOverride) & RISCV_CPU_FEATURE_CMO_BITMASK) != 0);
+}
+
+/**
+ Performs required opeartion on cache lines in the cache coherency domain
+ of the calling CPU. If Address is not aligned on a cache line boundary,
+ then entire cache line containing Address is operated. If Address + Length
+ is not aligned on a cache line boundary, then the entire cache line
+ containing Address + Length -1 is operated.
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+ @param Address The base address of the cache lines to
+ invalidate.
+ @param Length The number of bytes to invalidate from the instruction
+ cache.
+ @param Op Type of CMO operation to be performed
+ @return Address.
+
+**/
+STATIC
+VOID
+CacheOpCacheRange (
+ IN VOID *Address,
+ IN UINTN Length,
+ IN CACHE_OP Op
+ )
+{
+ UINTN CacheLineSize;
+ UINTN Start;
+ UINTN End;
+
+ if (Length == 0) {
+ return;
+ }
+
+ if ((Op != Invld) && (Op != Flush) && (Op != Clean)) {
+ return;
+ }
+
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Address));
+
+ CacheLineSize = RISCV_CACHE_BLOCK_SIZE;
+
+ Start = (UINTN)Address;
+ //
+ // Calculate the cache line alignment
+ //
+ End = (Start + Length + (CacheLineSize - 1)) & ~(CacheLineSize - 1);
+ Start &= ~((UINTN)CacheLineSize - 1);
+
+ DEBUG (
+ (DEBUG_INFO,
+ "%a Performing Cache Management Operation %d \n", __func__, Op)
+ );
+
+ do {
+ switch (Op) {
+ case Invld:
+ RiscVCpuCacheInvalAsmCbo (Start);
+ break;
+ case Flush:
+ RiscVCpuCacheFlushAsmCbo (Start);
+ break;
+ case Clean:
+ RiscVCpuCacheCleanAsmCbo (Start);
+ break;
+ default:
+ break;
+ }
+
+ Start = Start + CacheLineSize;
+ } while (Start != End);
+}
/**
Invalidates the entire instruction cache in cache coherency domain of the
- calling CPU.
+ calling CPU. Risc-V does not have currently an CBO implementation which can
+ invalidate entire I-cache. Hence using Fence instruction for now. P.S. Fence
+ instruction may or may not implement full I-cache invd functionality on all
+ implementations.
**/
VOID
@@ -56,12 +158,17 @@ InvalidateInstructionCacheRange (
IN UINTN Length
)
{
- DEBUG (
- (DEBUG_WARN,
- "%a:RISC-V unsupported function.\n"
- "Invalidating the whole instruction cache instead.\n", __func__)
- );
- InvalidateInstructionCache ();
+ if (RiscVIsCMOEnabled ()) {
+ CacheOpCacheRange (Address, Length, Invld);
+ } else {
+ DEBUG (
+ (DEBUG_WARN,
+ "%a:RISC-V unsupported function.\n"
+ "Invalidating the whole instruction cache instead.\n", __func__)
+ );
+ InvalidateInstructionCache ();
+ }
+
return Address;
}
@@ -117,7 +224,12 @@ WriteBackInvalidateDataCacheRange (
IN UINTN Length
)
{
- DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));
+ if (RiscVIsCMOEnabled ()) {
+ CacheOpCacheRange (Address, Length, Flush);
+ } else {
+ DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));
+ }
+
return Address;
}
@@ -156,10 +268,7 @@ WriteBackDataCache (
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
- @param Address The base address of the data cache lines to write back. If
- the CPU is in a physical addressing mode, then Address is a
- physical address. If the CPU is in a virtual addressing
- mode, then Address is a virtual address.
+ @param Address The base address of the data cache lines to write back.
@param Length The number of bytes to write back from the data cache.
@return Address of cache written in main memory.
@@ -172,7 +281,12 @@ WriteBackDataCacheRange (
IN UINTN Length
)
{
- DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));
+ if (RiscVIsCMOEnabled ()) {
+ CacheOpCacheRange (Address, Length, Clean);
+ } else {
+ DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));
+ }
+
return Address;
}
@@ -214,10 +328,7 @@ InvalidateDataCache (
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
- @param Address The base address of the data cache lines to invalidate. If
- the CPU is in a physical addressing mode, then Address is a
- physical address. If the CPU is in a virtual addressing mode,
- then Address is a virtual address.
+ @param Address The base address of the data cache lines to invalidate.
@param Length The number of bytes to invalidate from the data cache.
@return Address.
@@ -230,6 +341,16 @@ InvalidateDataCacheRange (
IN UINTN Length
)
{
- DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));
+ if (RiscVIsCMOEnabled ()) {
+ CacheOpCacheRange (Address, Length, Invld);
+ } else {
+ DEBUG (
+ (DEBUG_WARN,
+ "%a:RISC-V unsupported function.\n"
+ "Invalidating the whole Data cache instead.\n", __func__)
+ );
+ InvalidateDataCache ();
+ }
+
return Address;
}
diff --git a/MdePkg/MdePkg.uni b/MdePkg/MdePkg.uni
index 5c1fa24065c7..f49c33191054 100644
--- a/MdePkg/MdePkg.uni
+++ b/MdePkg/MdePkg.uni
@@ -287,6 +287,10 @@
#string STR_gEfiMdePkgTokenSpaceGuid_PcdGuidedExtractHandlerTableAddress_HELP #language en-US "This value is used to set the available memory address to store Guided Extract Handlers. The required memory space is decided by the value of PcdMaximumGuidedExtractHandler."
+#string STR_gEfiMdePkgTokenSpaceGuid_PcdRiscVFeatureOverride_PROMPT #language en-US "RISC-V Feature Override"
+
+#string STR_gEfiMdePkgTokenSpaceGuid_PcdRiscVFeatureOverride_HELP #language en-US "This value is used to Override Any RISC-V specific features supported by this PCD"
+
#string STR_gEfiMdePkgTokenSpaceGuid_PcdPciExpressBaseAddress_PROMPT #language en-US "PCI Express Base Address"
#string STR_gEfiMdePkgTokenSpaceGuid_PcdPciExpressBaseAddress_HELP #language en-US "This value is used to set the base address of PCI express hierarchy."
--
2.39.2
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* [edk2-devel] [PATCH v6 5/5] OvmfPkg/RiscVVirt: Override for RV CPU Features
2023-10-21 17:33 [edk2-devel] [PATCH v6 0/5] Cache Management Operations Support For RISC-V Dhaval Sharma
` (3 preceding siblings ...)
2023-10-21 17:33 ` [edk2-devel] [PATCH v6 4/5] MdePkg: Utilize Cache Management Operations Implementation For RISC-V Dhaval Sharma
@ 2023-10-21 17:33 ` Dhaval Sharma
2023-10-24 12:45 ` Laszlo Ersek
4 siblings, 1 reply; 13+ messages in thread
From: Dhaval Sharma @ 2023-10-21 17:33 UTC (permalink / raw)
To: devel
Cc: Ard Biesheuvel, Jiewen Yao, Jordan Justen, Gerd Hoffmann,
Sunil V L, Andrei Warkentin, Laszlo Ersek
This PCD provides a way for platform to override any
HW features that are default enabled by previous stages
of FW (like OpenSBI). For the case where previous/prev
stage has disabled the feature, this override is not
useful and its usage should be avoided.
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Andrei Warkentin <andrei.warkentin@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
---
Notes:
v2:
- Modify PCD name according to changes made in Baselib implementation
V1:
- Introduce PCD for platform
OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 +
1 file changed, 1 insertion(+)
diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
index fe320525153f..5d66f7fe6ae6 100644
--- a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
+++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
@@ -203,6 +203,7 @@ [PcdsFeatureFlag]
gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
[PcdsFixedAtBuild.common]
+ gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0
gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|0
--
2.39.2
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* Re: [edk2-devel] [PATCH v6 1/5] MdePkg: Move RISC-V Cache Management Declarations Into BaseLib
2023-10-21 17:33 ` [edk2-devel] [PATCH v6 1/5] MdePkg: Move RISC-V Cache Management Declarations Into BaseLib Dhaval Sharma
@ 2023-10-24 12:32 ` Laszlo Ersek
0 siblings, 0 replies; 13+ messages in thread
From: Laszlo Ersek @ 2023-10-24 12:32 UTC (permalink / raw)
To: devel, dhaval; +Cc: Michael D Kinney, Liming Gao, Zhiguang Liu
On 10/21/23 19:33, Dhaval Sharma wrote:
> The declarations for cache Management functions belong to BaseLib
> instead of instance source file. This helps with further restructuring
> of cache management code for RISC-V.
>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Liming Gao <gaoliming@byosoft.com.cn>
> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
>
> Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
> ---
>
> Notes:
> V5:
> - Move cache management function declaration in baselib where it belongs
>
> MdePkg/Include/Library/BaseLib.h | 20 ++++++++++++++++++++
> MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 20 --------------------
> 2 files changed, 20 insertions(+), 20 deletions(-)
>
> diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
> index 5d7067ee854e..7142bbfa42f2 100644
> --- a/MdePkg/Include/Library/BaseLib.h
> +++ b/MdePkg/Include/Library/BaseLib.h
> @@ -206,6 +206,26 @@ RiscVClearPendingTimerInterrupt (
> VOID
> );
>
> +/**
> + RISC-V invalidate instruction cache.
> +
> +**/
> +VOID
> +EFIAPI
> +RiscVInvalidateInstCacheAsm (
> + VOID
> + );
> +
> +/**
> + RISC-V invalidate data cache.
> +
> +**/
> +VOID
> +EFIAPI
> +RiscVInvalidateDataCacheAsm (
> + VOID
> + );
> +
> #endif // defined (MDE_CPU_RISCV64)
>
> #if defined (MDE_CPU_LOONGARCH64)
> diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> index d08fb9f193ca..d5efcf49a4bf 100644
> --- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> @@ -10,26 +10,6 @@
> #include <Library/BaseLib.h>
> #include <Library/DebugLib.h>
>
> -/**
> - RISC-V invalidate instruction cache.
> -
> -**/
> -VOID
> -EFIAPI
> -RiscVInvalidateInstCacheAsm (
> - VOID
> - );
> -
> -/**
> - RISC-V invalidate data cache.
> -
> -**/
> -VOID
> -EFIAPI
> -RiscVInvalidateDataCacheAsm (
> - VOID
> - );
> -
> /**
> Invalidates the entire instruction cache in cache coherency domain of the
> calling CPU.
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
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* Re: [edk2-devel] [PATCH v6 2/5] MdePkg: Rename Cache Management Function To Clarify Fence Based Op
2023-10-21 17:33 ` [edk2-devel] [PATCH v6 2/5] MdePkg: Rename Cache Management Function To Clarify Fence Based Op Dhaval Sharma
@ 2023-10-24 12:34 ` Laszlo Ersek
0 siblings, 0 replies; 13+ messages in thread
From: Laszlo Ersek @ 2023-10-24 12:34 UTC (permalink / raw)
To: devel, dhaval
Cc: Michael D Kinney, Liming Gao, Zhiguang Liu, Sunil V L,
Daniel Schaefer
On 10/21/23 19:33, Dhaval Sharma wrote:
> There are different ways to manage cache on RISC-V Processors.
> One way is to use fence instruction. Another way is to use CPU
> specific cache management operation instructions ratified as
> per RISC-V ISA specifications to be introduced in future
> patches. Current method is fence instruction based, rename the
> function accordingly to add that clarity.
>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Liming Gao <gaoliming@byosoft.com.cn>
> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
> Cc: Sunil V L <sunilvl@ventanamicro.com>
> Cc: Daniel Schaefer <git@danielschaefer.me>
> Cc: Laszlo Ersek <lersek@redhat.com>
>
> Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
> ---
>
> Notes:
> V6:
> - As part of restructuring, adding cache instruction differentiation
> in function naming
>
> MdePkg/Include/Library/BaseLib.h | 4 ++--
> MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 4 ++--
> MdePkg/Library/BaseLib/RiscV64/FlushCache.S | 8 ++++----
> 3 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
> index 7142bbfa42f2..d4b56a9601da 100644
> --- a/MdePkg/Include/Library/BaseLib.h
> +++ b/MdePkg/Include/Library/BaseLib.h
> @@ -212,7 +212,7 @@ RiscVClearPendingTimerInterrupt (
> **/
> VOID
> EFIAPI
> -RiscVInvalidateInstCacheAsm (
> +RiscVInvalidateInstCacheAsmFence (
> VOID
> );
>
> @@ -222,7 +222,7 @@ RiscVInvalidateInstCacheAsm (
> **/
> VOID
> EFIAPI
> -RiscVInvalidateDataCacheAsm (
> +RiscVInvalidateDataCacheAsmFence (
> VOID
> );
>
> diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> index d5efcf49a4bf..4eb18edb9aa7 100644
> --- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> @@ -21,7 +21,7 @@ InvalidateInstructionCache (
> VOID
> )
> {
> - RiscVInvalidateInstCacheAsm ();
> + RiscVInvalidateInstCacheAsmFence ();
> }
>
> /**
> @@ -193,7 +193,7 @@ InvalidateDataCache (
> VOID
> )
> {
> - RiscVInvalidateDataCacheAsm ();
> + RiscVInvalidateDataCacheAsmFence ();
> }
>
> /**
> diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
> index 7c10fdd268af..e0eea0b5fb25 100644
> --- a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
> +++ b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
> @@ -9,13 +9,13 @@
> //------------------------------------------------------------------------------
>
> .align 3
> -ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsm)
> -ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsm)
> +ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsmFence)
> +ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsmFence)
>
> -ASM_PFX(RiscVInvalidateInstCacheAsm):
> +ASM_PFX(RiscVInvalidateInstCacheAsmFence):
> fence.i
> ret
>
> -ASM_PFX(RiscVInvalidateDataCacheAsm):
> +ASM_PFX(RiscVInvalidateDataCacheAsmFence):
> fence
> ret
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
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* Re: [edk2-devel] [PATCH v6 3/5] MdePkg: Implement RISC-V Cache Management Operations
2023-10-21 17:33 ` [edk2-devel] [PATCH v6 3/5] MdePkg: Implement RISC-V Cache Management Operations Dhaval Sharma
@ 2023-10-24 12:39 ` Laszlo Ersek
0 siblings, 0 replies; 13+ messages in thread
From: Laszlo Ersek @ 2023-10-24 12:39 UTC (permalink / raw)
To: devel, dhaval
Cc: Michael D Kinney, Liming Gao, Zhiguang Liu, Sunil V L,
Daniel Schaefer
On 10/21/23 19:33, Dhaval Sharma wrote:
> Implement Cache Management Operations (CMO) defined by
> RISC-V spec https://github.com/riscv/riscv-CMOs.
>
> Notes:
> 1. CMO only supports block based Operations. Meaning cache
> flush/invd/clean Operations are not available for the entire
> range. In that case we fallback on fence.i instructions.
> 2. Operations are implemented using Opcodes to make them compiler
> independent. binutils 2.39+ compilers support CMO instructions.
>
> Test:
> 1. Ensured correct instructions are refelecting in asm
> 2. Not able to verify actual instruction in HW as Qemu ignores
> any actual cache operations.
>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Liming Gao <gaoliming@byosoft.com.cn>
> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
> Cc: Sunil V L <sunilvl@ventanamicro.com>
> Cc: Daniel Schaefer <git@danielschaefer.me>
> Cc: Laszlo Ersek <lersek@redhat.com>
>
> Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
> ---
>
> Notes:
> V1:
> - Implement Cache management instructions in Baselib
>
> MdePkg/Library/BaseLib/BaseLib.inf | 2 +-
> MdePkg/Include/Library/BaseLib.h | 33 ++++++++++++++++++++
> MdePkg/Include/RiscV64/RiscVasm.inc | 19 +++++++++++
> MdePkg/Library/BaseLib/RiscV64/{FlushCache.S => RiscVCacheMgmt.S} | 17 ++++++++++
> 4 files changed, 70 insertions(+), 1 deletion(-)
>
> diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
> index 03c7b02e828b..53389389448c 100644
> --- a/MdePkg/Library/BaseLib/BaseLib.inf
> +++ b/MdePkg/Library/BaseLib/BaseLib.inf
> @@ -400,7 +400,7 @@ [Sources.RISCV64]
> RiscV64/RiscVCpuBreakpoint.S | GCC
> RiscV64/RiscVCpuPause.S | GCC
> RiscV64/RiscVInterrupt.S | GCC
> - RiscV64/FlushCache.S | GCC
> + RiscV64/RiscVCacheMgmt.S | GCC
> RiscV64/CpuScratch.S | GCC
> RiscV64/ReadTimer.S | GCC
> RiscV64/RiscVMmu.S | GCC
> diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
> index d4b56a9601da..60d60602b876 100644
> --- a/MdePkg/Include/Library/BaseLib.h
> +++ b/MdePkg/Include/Library/BaseLib.h
> @@ -226,6 +226,39 @@ RiscVInvalidateDataCacheAsmFence (
> VOID
> );
>
> +/**
> + RISC-V flush cache block. Atomically perform a clean operation
> + followed by an invalidate operation
> +
> +**/
> +VOID
> +EFIAPI
> +RiscVCpuCacheFlushAsmCbo (
> + IN UINTN
> + );
> +
> +/**
> +Perform a write transfer to another cache or to memory if the
> +data in the copy of the cache block have been modified by a store
> +operation
> +
> +**/
> +VOID
> +EFIAPI
> +RiscVCpuCacheCleanAsmCbo (
> + IN UINTN
> + );
> +
> +/**
> +Deallocate the copy of the cache block
> +
> +**/
> +VOID
> +EFIAPI
> +RiscVCpuCacheInvalAsmCbo (
> + IN UINTN
> + );
> +
> #endif // defined (MDE_CPU_RISCV64)
>
> #if defined (MDE_CPU_LOONGARCH64)
> diff --git a/MdePkg/Include/RiscV64/RiscVasm.inc b/MdePkg/Include/RiscV64/RiscVasm.inc
> new file mode 100644
> index 000000000000..6f418232d507
> --- /dev/null
> +++ b/MdePkg/Include/RiscV64/RiscVasm.inc
> @@ -0,0 +1,19 @@
> +/*
> + *
> + * RISC-V cache operation encoding.
> + * Copyright (c) 2023, Rivos Inc. All rights reserved.<BR>
> + * SPDX-License-Identifier: BSD-2-Clause-Patent
> + *
> + */
> +
> +.macro RISCVCBOFLSH
> + .word 0x25200f
> +.endm
> +
> +.macro RISCVCBOINVD
> + .word 0x05200f
> +.endm
> +
> +.macro RISCVCBOCLEN
> + .word 0x15200f
> +.endm
> diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S b/MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S
> similarity index 57%
> rename from MdePkg/Library/BaseLib/RiscV64/FlushCache.S
> rename to MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S
> index e0eea0b5fb25..fe3943ae3f7c 100644
> --- a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
> +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S
> @@ -3,10 +3,12 @@
> // RISC-V cache operation.
> //
> // Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +// Copyright (c) 2023, Rivos Inc. All rights reserved.<BR>
> //
> // SPDX-License-Identifier: BSD-2-Clause-Patent
> //
> //------------------------------------------------------------------------------
> +.include "RiscVasm.inc"
>
> .align 3
> ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsmFence)
> @@ -19,3 +21,18 @@ ASM_PFX(RiscVInvalidateInstCacheAsmFence):
> ASM_PFX(RiscVInvalidateDataCacheAsmFence):
> fence
> ret
> +
> +ASM_GLOBAL ASM_PFX (RiscVCpuCacheFlushAsmCbo)
> +ASM_PFX (RiscVCpuCacheFlushAsmCbo):
> + RISCVCBOFLSH
> + ret
> +
> +ASM_GLOBAL ASM_PFX (RiscVCpuCacheCleanAsmCbo)
> +ASM_PFX (RiscVCpuCacheCleanAsmCbo):
> + RISCVCBOCLEN
> + ret
> +
> +ASM_GLOBAL ASM_PFX (RiscVCpuCacheInvalAsmCbo)
> +ASM_PFX (RiscVCpuCacheInvalAsmCbo):
> + RISCVCBOINVD
> + ret
I've not validated the assembly insn encodings.
I also think that *FLSH, *CLEN, and *INVD could just as well be FLUSH,
CLEAN, and INVALIDATE.
But those are really minor IMO.
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
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* Re: [edk2-devel] [PATCH v6 5/5] OvmfPkg/RiscVVirt: Override for RV CPU Features
2023-10-21 17:33 ` [edk2-devel] [PATCH v6 5/5] OvmfPkg/RiscVVirt: Override for RV CPU Features Dhaval Sharma
@ 2023-10-24 12:45 ` Laszlo Ersek
0 siblings, 0 replies; 13+ messages in thread
From: Laszlo Ersek @ 2023-10-24 12:45 UTC (permalink / raw)
To: devel, dhaval
Cc: Ard Biesheuvel, Jiewen Yao, Jordan Justen, Gerd Hoffmann,
Sunil V L, Andrei Warkentin
On 10/21/23 19:33, Dhaval Sharma wrote:
> This PCD provides a way for platform to override any
> HW features that are default enabled by previous stages
> of FW (like OpenSBI). For the case where previous/prev
> stage has disabled the feature, this override is not
> useful and its usage should be avoided.
>
> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
> Cc: Jiewen Yao <jiewen.yao@intel.com>
> Cc: Jordan Justen <jordan.l.justen@intel.com>
> Cc: Gerd Hoffmann <kraxel@redhat.com>
> Cc: Sunil V L <sunilvl@ventanamicro.com>
> Cc: Andrei Warkentin <andrei.warkentin@intel.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
>
> Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
> ---
>
> Notes:
> v2:
> - Modify PCD name according to changes made in Baselib implementation
> V1:
> - Introduce PCD for platform
>
> OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
> index fe320525153f..5d66f7fe6ae6 100644
> --- a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
> +++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
> @@ -203,6 +203,7 @@ [PcdsFeatureFlag]
> gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
>
> [PcdsFixedAtBuild.common]
> + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0
> gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
> gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
> gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|0
I propose to only clear the least significant bit in the PCD -- that is,
say 0xFFFFFFFFFFFFFFFE here.
But, it's up to you. Either way:
Acked-by: Laszlo Ersek <lersek@redhat.com>
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* Re: [edk2-devel] [PATCH v6 4/5] MdePkg: Utilize Cache Management Operations Implementation For RISC-V
2023-10-21 17:33 ` [edk2-devel] [PATCH v6 4/5] MdePkg: Utilize Cache Management Operations Implementation For RISC-V Dhaval Sharma
@ 2023-10-24 12:45 ` Laszlo Ersek
2023-10-24 20:09 ` Pedro Falcato
1 sibling, 0 replies; 13+ messages in thread
From: Laszlo Ersek @ 2023-10-24 12:45 UTC (permalink / raw)
To: devel, dhaval; +Cc: Michael D Kinney, Liming Gao, Zhiguang Liu
On 10/21/23 19:33, Dhaval Sharma wrote:
> Use newly defined cache management operations for RISC-V where possible
> It builds up on the support added for RISC-V cache management
> instructions in BaseLib.
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Liming Gao <gaoliming@byosoft.com.cn>
> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
>
> Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
> ---
>
> Notes:
> V1:
> - Utilize cache management instructions if HW supports it
> This patch is part of restructuring on top of v5
>
> MdePkg/MdePkg.dec | 8 +
> MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf | 2 +
> MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 159 +++++++++++++++++---
> MdePkg/MdePkg.uni | 4 +
> 4 files changed, 154 insertions(+), 19 deletions(-)
>
> diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
> index ac54338089e8..fa92673ff633 100644
> --- a/MdePkg/MdePkg.dec
> +++ b/MdePkg/MdePkg.dec
> @@ -2399,6 +2399,14 @@ [PcdsFixedAtBuild.AARCH64, PcdsPatchableInModule.AARCH64]
> # @Prompt CPU Rng algorithm's GUID.
> gEfiMdePkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm|{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}|VOID*|0x00000037
>
> +[PcdsFixedAtBuild.RISCV64, PcdsPatchableInModule.RISCV64]
> + #
> + # Configurability to override RISC-V CPU Features
> + # BIT 0 = Cache Management Operations. This bit is relevant only if
> + # previous stage has feature enabled and user wants to disable it.
> + #
> + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFF|UINT64|0x69
> +
> [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
> ## This value is used to set the base address of PCI express hierarchy.
> # @Prompt PCI Express Base Address.
> diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
> index 6fd9cbe5f6c9..39a7fb963b49 100644
> --- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
> +++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
> @@ -56,3 +56,5 @@ [LibraryClasses]
> BaseLib
> DebugLib
>
> +[Pcd.RISCV64]
> + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride ## CONSUMES
> diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> index 4eb18edb9aa7..6851970c9e16 100644
> --- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> @@ -1,7 +1,8 @@
> /** @file
> - RISC-V specific functionality for cache.
> + Implement Risc-V Cache Management Operations
>
> Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> + Copyright (c) 2023, Rivos Inc. All rights reserved.<BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
> **/
> @@ -9,10 +10,111 @@
> #include <Base.h>
> #include <Library/BaseLib.h>
> #include <Library/DebugLib.h>
> +#include <Library/PcdLib.h>
One nit: given that we're introducing a PcdLib dependency here, we
should also add the following to the library instance INF file:
[LibraryClasses.RISCV64]
PcdLib
I've not deeply verified the implementation in this patch, but
structurally it looks OK to me. So you can add:
Acked-by: Laszlo Ersek <lersek@redhat.com>
to the next version (with the LibraryClasses addition).
Thanks
Laszlo
> +
> +// TODO: This will be removed once RISC-V CPU HOB is available
> +#define RISCV_CACHE_BLOCK_SIZE 64
> +#define RISCV_CPU_FEATURE_CMO_BITMASK 0x1
> +
> +typedef enum {
> + Clean,
> + Flush,
> + Invld,
> +} CACHE_OP;
> +
> +/**
> +Verify CBOs are supported by this HW
> +TODO: Use RISC-V CPU HOB once available.
> +
> +**/
> +STATIC
> +BOOLEAN
> +RiscVIsCMOEnabled (
> + VOID
> + )
> +{
> + // TODO: Add check for CMO from CPU HOB.
> + // If CMO is disabled in HW, skip Override check
> + // Otherwise this PCD can override settings
> + return ((PcdGet64 (PcdRiscVFeatureOverride) & RISCV_CPU_FEATURE_CMO_BITMASK) != 0);
> +}
> +
> +/**
> + Performs required opeartion on cache lines in the cache coherency domain
> + of the calling CPU. If Address is not aligned on a cache line boundary,
> + then entire cache line containing Address is operated. If Address + Length
> + is not aligned on a cache line boundary, then the entire cache line
> + containing Address + Length -1 is operated.
> + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
> + @param Address The base address of the cache lines to
> + invalidate.
> + @param Length The number of bytes to invalidate from the instruction
> + cache.
> + @param Op Type of CMO operation to be performed
> + @return Address.
> +
> +**/
> +STATIC
> +VOID
> +CacheOpCacheRange (
> + IN VOID *Address,
> + IN UINTN Length,
> + IN CACHE_OP Op
> + )
> +{
> + UINTN CacheLineSize;
> + UINTN Start;
> + UINTN End;
> +
> + if (Length == 0) {
> + return;
> + }
> +
> + if ((Op != Invld) && (Op != Flush) && (Op != Clean)) {
> + return;
> + }
> +
> + ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Address));
> +
> + CacheLineSize = RISCV_CACHE_BLOCK_SIZE;
> +
> + Start = (UINTN)Address;
> + //
> + // Calculate the cache line alignment
> + //
> + End = (Start + Length + (CacheLineSize - 1)) & ~(CacheLineSize - 1);
> + Start &= ~((UINTN)CacheLineSize - 1);
> +
> + DEBUG (
> + (DEBUG_INFO,
> + "%a Performing Cache Management Operation %d \n", __func__, Op)
> + );
> +
> + do {
> + switch (Op) {
> + case Invld:
> + RiscVCpuCacheInvalAsmCbo (Start);
> + break;
> + case Flush:
> + RiscVCpuCacheFlushAsmCbo (Start);
> + break;
> + case Clean:
> + RiscVCpuCacheCleanAsmCbo (Start);
> + break;
> + default:
> + break;
> + }
> +
> + Start = Start + CacheLineSize;
> + } while (Start != End);
> +}
>
> /**
> Invalidates the entire instruction cache in cache coherency domain of the
> - calling CPU.
> + calling CPU. Risc-V does not have currently an CBO implementation which can
> + invalidate entire I-cache. Hence using Fence instruction for now. P.S. Fence
> + instruction may or may not implement full I-cache invd functionality on all
> + implementations.
>
> **/
> VOID
> @@ -56,12 +158,17 @@ InvalidateInstructionCacheRange (
> IN UINTN Length
> )
> {
> - DEBUG (
> - (DEBUG_WARN,
> - "%a:RISC-V unsupported function.\n"
> - "Invalidating the whole instruction cache instead.\n", __func__)
> - );
> - InvalidateInstructionCache ();
> + if (RiscVIsCMOEnabled ()) {
> + CacheOpCacheRange (Address, Length, Invld);
> + } else {
> + DEBUG (
> + (DEBUG_WARN,
> + "%a:RISC-V unsupported function.\n"
> + "Invalidating the whole instruction cache instead.\n", __func__)
> + );
> + InvalidateInstructionCache ();
> + }
> +
> return Address;
> }
>
> @@ -117,7 +224,12 @@ WriteBackInvalidateDataCacheRange (
> IN UINTN Length
> )
> {
> - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));
> + if (RiscVIsCMOEnabled ()) {
> + CacheOpCacheRange (Address, Length, Flush);
> + } else {
> + DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));
> + }
> +
> return Address;
> }
>
> @@ -156,10 +268,7 @@ WriteBackDataCache (
>
> If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
>
> - @param Address The base address of the data cache lines to write back. If
> - the CPU is in a physical addressing mode, then Address is a
> - physical address. If the CPU is in a virtual addressing
> - mode, then Address is a virtual address.
> + @param Address The base address of the data cache lines to write back.
> @param Length The number of bytes to write back from the data cache.
>
> @return Address of cache written in main memory.
> @@ -172,7 +281,12 @@ WriteBackDataCacheRange (
> IN UINTN Length
> )
> {
> - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));
> + if (RiscVIsCMOEnabled ()) {
> + CacheOpCacheRange (Address, Length, Clean);
> + } else {
> + DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));
> + }
> +
> return Address;
> }
>
> @@ -214,10 +328,7 @@ InvalidateDataCache (
>
> If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
>
> - @param Address The base address of the data cache lines to invalidate. If
> - the CPU is in a physical addressing mode, then Address is a
> - physical address. If the CPU is in a virtual addressing mode,
> - then Address is a virtual address.
> + @param Address The base address of the data cache lines to invalidate.
> @param Length The number of bytes to invalidate from the data cache.
>
> @return Address.
> @@ -230,6 +341,16 @@ InvalidateDataCacheRange (
> IN UINTN Length
> )
> {
> - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));
> + if (RiscVIsCMOEnabled ()) {
> + CacheOpCacheRange (Address, Length, Invld);
> + } else {
> + DEBUG (
> + (DEBUG_WARN,
> + "%a:RISC-V unsupported function.\n"
> + "Invalidating the whole Data cache instead.\n", __func__)
> + );
> + InvalidateDataCache ();
> + }
> +
> return Address;
> }
> diff --git a/MdePkg/MdePkg.uni b/MdePkg/MdePkg.uni
> index 5c1fa24065c7..f49c33191054 100644
> --- a/MdePkg/MdePkg.uni
> +++ b/MdePkg/MdePkg.uni
> @@ -287,6 +287,10 @@
>
> #string STR_gEfiMdePkgTokenSpaceGuid_PcdGuidedExtractHandlerTableAddress_HELP #language en-US "This value is used to set the available memory address to store Guided Extract Handlers. The required memory space is decided by the value of PcdMaximumGuidedExtractHandler."
>
> +#string STR_gEfiMdePkgTokenSpaceGuid_PcdRiscVFeatureOverride_PROMPT #language en-US "RISC-V Feature Override"
> +
> +#string STR_gEfiMdePkgTokenSpaceGuid_PcdRiscVFeatureOverride_HELP #language en-US "This value is used to Override Any RISC-V specific features supported by this PCD"
> +
> #string STR_gEfiMdePkgTokenSpaceGuid_PcdPciExpressBaseAddress_PROMPT #language en-US "PCI Express Base Address"
>
> #string STR_gEfiMdePkgTokenSpaceGuid_PcdPciExpressBaseAddress_HELP #language en-US "This value is used to set the base address of PCI express hierarchy."
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [edk2-devel] [PATCH v6 4/5] MdePkg: Utilize Cache Management Operations Implementation For RISC-V
2023-10-21 17:33 ` [edk2-devel] [PATCH v6 4/5] MdePkg: Utilize Cache Management Operations Implementation For RISC-V Dhaval Sharma
2023-10-24 12:45 ` Laszlo Ersek
@ 2023-10-24 20:09 ` Pedro Falcato
2023-10-29 14:48 ` Dhaval Sharma
1 sibling, 1 reply; 13+ messages in thread
From: Pedro Falcato @ 2023-10-24 20:09 UTC (permalink / raw)
To: devel, dhaval; +Cc: Michael D Kinney, Liming Gao, Zhiguang Liu, Laszlo Ersek
On Sat, Oct 21, 2023 at 6:33 PM Dhaval Sharma <dhaval@rivosinc.com> wrote:
>
> Use newly defined cache management operations for RISC-V where possible
> It builds up on the support added for RISC-V cache management
> instructions in BaseLib.
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Liming Gao <gaoliming@byosoft.com.cn>
> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
>
> Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
> ---
>
> Notes:
> V1:
> - Utilize cache management instructions if HW supports it
> This patch is part of restructuring on top of v5
>
> MdePkg/MdePkg.dec | 8 +
> MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf | 2 +
> MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 159 +++++++++++++++++---
> MdePkg/MdePkg.uni | 4 +
> 4 files changed, 154 insertions(+), 19 deletions(-)
>
> diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
> index ac54338089e8..fa92673ff633 100644
> --- a/MdePkg/MdePkg.dec
> +++ b/MdePkg/MdePkg.dec
> @@ -2399,6 +2399,14 @@ [PcdsFixedAtBuild.AARCH64, PcdsPatchableInModule.AARCH64]
> # @Prompt CPU Rng algorithm's GUID.
> gEfiMdePkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm|{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}|VOID*|0x00000037
>
> +[PcdsFixedAtBuild.RISCV64, PcdsPatchableInModule.RISCV64]
> + #
> + # Configurability to override RISC-V CPU Features
> + # BIT 0 = Cache Management Operations. This bit is relevant only if
> + # previous stage has feature enabled and user wants to disable it.
> + #
> + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFF|UINT64|0x69
> +
> [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
> ## This value is used to set the base address of PCI express hierarchy.
> # @Prompt PCI Express Base Address.
> diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
> index 6fd9cbe5f6c9..39a7fb963b49 100644
> --- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
> +++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
> @@ -56,3 +56,5 @@ [LibraryClasses]
> BaseLib
> DebugLib
>
> +[Pcd.RISCV64]
> + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride ## CONSUMES
> diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> index 4eb18edb9aa7..6851970c9e16 100644
> --- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> @@ -1,7 +1,8 @@
> /** @file
> - RISC-V specific functionality for cache.
> + Implement Risc-V Cache Management Operations
Why the change? You're effectively implementing cache management for
riscv, you're not exclusively using any sort of extension (such as
CMO).
>
> Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> + Copyright (c) 2023, Rivos Inc. All rights reserved.<BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
> **/
> @@ -9,10 +10,111 @@
> #include <Base.h>
> #include <Library/BaseLib.h>
> #include <Library/DebugLib.h>
> +#include <Library/PcdLib.h>
> +
> +// TODO: This will be removed once RISC-V CPU HOB is available
> +#define RISCV_CACHE_BLOCK_SIZE 64
> +#define RISCV_CPU_FEATURE_CMO_BITMASK 0x1
> +
> +typedef enum {
> + Clean,
> + Flush,
> + Invld,
> +} CACHE_OP;
> +
> +/**
> +Verify CBOs are supported by this HW
> +TODO: Use RISC-V CPU HOB once available.
> +
> +**/
> +STATIC
> +BOOLEAN
> +RiscVIsCMOEnabled (
> + VOID
> + )
> +{
> + // TODO: Add check for CMO from CPU HOB.
Too many TODOs? One TODO at the top of the file (mentioning feature
detection, cache line size detection) should be enough. There's no
point in peppering these out throughout the file :)
> + // If CMO is disabled in HW, skip Override check
> + // Otherwise this PCD can override settings
> + return ((PcdGet64 (PcdRiscVFeatureOverride) & RISCV_CPU_FEATURE_CMO_BITMASK) != 0);
> +}
> +
> +/**
> + Performs required opeartion on cache lines in the cache coherency domain
> + of the calling CPU. If Address is not aligned on a cache line boundary,
> + then entire cache line containing Address is operated. If Address + Length
> + is not aligned on a cache line boundary, then the entire cache line
> + containing Address + Length -1 is operated.
> + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
> + @param Address The base address of the cache lines to
> + invalidate.
> + @param Length The number of bytes to invalidate from the instruction
> + cache.
> + @param Op Type of CMO operation to be performed
> + @return Address.
> +
> +**/
> +STATIC
> +VOID
> +CacheOpCacheRange (
> + IN VOID *Address,
> + IN UINTN Length,
> + IN CACHE_OP Op
> + )
> +{
> + UINTN CacheLineSize;
> + UINTN Start;
> + UINTN End;
> +
> + if (Length == 0) {
> + return;
> + }
> +
> + if ((Op != Invld) && (Op != Flush) && (Op != Clean)) {
> + return;
> + }
> +
> + ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Address));
> +
> + CacheLineSize = RISCV_CACHE_BLOCK_SIZE;
> +
> + Start = (UINTN)Address;
> + //
> + // Calculate the cache line alignment
> + //
> + End = (Start + Length + (CacheLineSize - 1)) & ~(CacheLineSize - 1);
> + Start &= ~((UINTN)CacheLineSize - 1);
> +
> + DEBUG (
> + (DEBUG_INFO,
> + "%a Performing Cache Management Operation %d \n", __func__, Op)
> + );
nit: Can we pick a log style here? Like <something>: <log message>
In this case, "CacheOpCacheRange: Performing ...". It's just prettier
and more greppable.
> +
> + do {
> + switch (Op) {
> + case Invld:
> + RiscVCpuCacheInvalAsmCbo (Start);
> + break;
> + case Flush:
> + RiscVCpuCacheFlushAsmCbo (Start);
> + break;
> + case Clean:
> + RiscVCpuCacheCleanAsmCbo (Start);
> + break;
> + default:
> + break;
> + }
> +
> + Start = Start + CacheLineSize;
> + } while (Start != End);
> +}
>
> /**
> Invalidates the entire instruction cache in cache coherency domain of the
> - calling CPU.
> + calling CPU. Risc-V does not have currently an CBO implementation which can
> + invalidate entire I-cache. Hence using Fence instruction for now. P.S. Fence
nit: Invalidate *the* entire I-cache
Also, what do you mean? 1) you're calling CacheOpCacheRange for the range
2) please don't mix CBO and CMO. Too much terminology :)
Does Zicbom only operate on the dcache? Or does it also touch the
icache? As far as I'm aware, riscv does not require a dcache/icache
coherency (like ARM), but a quick stroll through the extension's spec
didn't lead me to much.
> + instruction may or may not implement full I-cache invd functionality on all
> + implementations.
>
> **/
> VOID
> @@ -56,12 +158,17 @@ InvalidateInstructionCacheRange (
> IN UINTN Length
> )
> {
> - DEBUG (
> - (DEBUG_WARN,
> - "%a:RISC-V unsupported function.\n"
> - "Invalidating the whole instruction cache instead.\n", __func__)
> - );
> - InvalidateInstructionCache ();
> + if (RiscVIsCMOEnabled ()) {
> + CacheOpCacheRange (Address, Length, Invld);
> + } else {
> + DEBUG (
> + (DEBUG_WARN,
> + "%a:RISC-V unsupported function.\n"
> + "Invalidating the whole instruction cache instead.\n", __func__)
> + );
nit: "%a: ", with a space, but i'd probably write this bit as
> + "%a: Zicbom not enabled, invalidating the whole instruction cache instead.\n", __func__)
Given that this may be repeatedly called, can we just warn once (e.g
on a constructor) that CMO is disabled and leave this be? Since the
cache management is in fact being done correctly, but just in a slower
way.
> + InvalidateInstructionCache ();
> + }
> +
> return Address;
> }
>
> @@ -117,7 +224,12 @@ WriteBackInvalidateDataCacheRange (
> IN UINTN Length
> )
> {
> - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));
> + if (RiscVIsCMOEnabled ()) {
> + CacheOpCacheRange (Address, Length, Flush);
> + } else {
> + DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));
Ok, so here it may make sense to ASSERT, as you're no longer complying
to the function's behavior (and this is unsafe).
> + }
> +
> return Address;
> }
>
> @@ -156,10 +268,7 @@ WriteBackDataCache (
>
> If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
>
> - @param Address The base address of the data cache lines to write back. If
> - the CPU is in a physical addressing mode, then Address is a
> - physical address. If the CPU is in a virtual addressing
> - mode, then Address is a virtual address.
> + @param Address The base address of the data cache lines to write back.
> @param Length The number of bytes to write back from the data cache.
>
> @return Address of cache written in main memory.
> @@ -172,7 +281,12 @@ WriteBackDataCacheRange (
> IN UINTN Length
> )
> {
> - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));
> + if (RiscVIsCMOEnabled ()) {
> + CacheOpCacheRange (Address, Length, Clean);
> + } else {
> + DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));
Same comment here WRT assert.
> + }
> +
> return Address;
> }
>
> @@ -214,10 +328,7 @@ InvalidateDataCache (
>
> If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
>
> - @param Address The base address of the data cache lines to invalidate. If
> - the CPU is in a physical addressing mode, then Address is a
> - physical address. If the CPU is in a virtual addressing mode,
> - then Address is a virtual address.
> + @param Address The base address of the data cache lines to invalidate.
> @param Length The number of bytes to invalidate from the data cache.
>
> @return Address.
> @@ -230,6 +341,16 @@ InvalidateDataCacheRange (
> IN UINTN Length
> )
> {
> - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));
> + if (RiscVIsCMOEnabled ()) {
> + CacheOpCacheRange (Address, Length, Invld);
> + } else {
> + DEBUG (
> + (DEBUG_WARN,
> + "%a:RISC-V unsupported function.\n"
> + "Invalidating the whole Data cache instead.\n", __func__)
> + );
Aaaand the same comment here WRT warning.
Pedro
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* Re: [edk2-devel] [PATCH v6 4/5] MdePkg: Utilize Cache Management Operations Implementation For RISC-V
2023-10-24 20:09 ` Pedro Falcato
@ 2023-10-29 14:48 ` Dhaval Sharma
0 siblings, 0 replies; 13+ messages in thread
From: Dhaval Sharma @ 2023-10-29 14:48 UTC (permalink / raw)
To: Pedro Falcato
Cc: devel, Michael D Kinney, Liming Gao, Zhiguang Liu, Laszlo Ersek
[-- Attachment #1: Type: text/plain, Size: 12596 bytes --]
Replied inline. Most of the cases I have addressed in the new patch I
submitted.
On Wed, Oct 25, 2023 at 1:39 AM Pedro Falcato <pedro.falcato@gmail.com>
wrote:
> On Sat, Oct 21, 2023 at 6:33 PM Dhaval Sharma <dhaval@rivosinc.com> wrote:
> >
> > Use newly defined cache management operations for RISC-V where possible
> > It builds up on the support added for RISC-V cache management
> > instructions in BaseLib.
> > Cc: Michael D Kinney <michael.d.kinney@intel.com>
> > Cc: Liming Gao <gaoliming@byosoft.com.cn>
> > Cc: Zhiguang Liu <zhiguang.liu@intel.com>
> > Cc: Laszlo Ersek <lersek@redhat.com>
> >
> > Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
> > ---
> >
> > Notes:
> > V1:
> > - Utilize cache management instructions if HW supports it
> > This patch is part of restructuring on top of v5
> >
> > MdePkg/MdePkg.dec |
> 8 +
> > MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf |
> 2 +
> > MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c |
> 159 +++++++++++++++++---
> > MdePkg/MdePkg.uni |
> 4 +
> > 4 files changed, 154 insertions(+), 19 deletions(-)
> >
> > diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
> > index ac54338089e8..fa92673ff633 100644
> > --- a/MdePkg/MdePkg.dec
> > +++ b/MdePkg/MdePkg.dec
> > @@ -2399,6 +2399,14 @@ [PcdsFixedAtBuild.AARCH64,
> PcdsPatchableInModule.AARCH64]
> > # @Prompt CPU Rng algorithm's GUID.
> >
> gEfiMdePkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm|{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}|VOID*|0x00000037
> >
> > +[PcdsFixedAtBuild.RISCV64, PcdsPatchableInModule.RISCV64]
> > + #
> > + # Configurability to override RISC-V CPU Features
> > + # BIT 0 = Cache Management Operations. This bit is relevant only if
> > + # previous stage has feature enabled and user wants to disable it.
> > + #
> > +
> gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFF|UINT64|0x69
> > +
> > [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
> > ## This value is used to set the base address of PCI express
> hierarchy.
> > # @Prompt PCI Express Base Address.
> > diff --git
> a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
> b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
> > index 6fd9cbe5f6c9..39a7fb963b49 100644
> > --- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
> > +++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
> > @@ -56,3 +56,5 @@ [LibraryClasses]
> > BaseLib
> > DebugLib
> >
> > +[Pcd.RISCV64]
> > + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride ## CONSUMES
> > diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> > index 4eb18edb9aa7..6851970c9e16 100644
> > --- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> > +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> > @@ -1,7 +1,8 @@
> > /** @file
> > - RISC-V specific functionality for cache.
> > + Implement Risc-V Cache Management Operations
>
> Why the change? You're effectively implementing cache management for
> riscv, you're not exclusively using any sort of extension (such as
> CMO).
>
Done. I believe you meant to keep it a generic description.
>
> >
> > Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All
> rights reserved.<BR>
> > + Copyright (c) 2023, Rivos Inc. All rights reserved.<BR>
> >
> > SPDX-License-Identifier: BSD-2-Clause-Patent
> > **/
> > @@ -9,10 +10,111 @@
> > #include <Base.h>
> > #include <Library/BaseLib.h>
> > #include <Library/DebugLib.h>
> > +#include <Library/PcdLib.h>
> > +
> > +// TODO: This will be removed once RISC-V CPU HOB is available
> > +#define RISCV_CACHE_BLOCK_SIZE 64
> > +#define RISCV_CPU_FEATURE_CMO_BITMASK 0x1
> > +
> > +typedef enum {
> > + Clean,
> > + Flush,
> > + Invld,
> > +} CACHE_OP;
> > +
> > +/**
> > +Verify CBOs are supported by this HW
> > +TODO: Use RISC-V CPU HOB once available.
> > +
> > +**/
> > +STATIC
> > +BOOLEAN
> > +RiscVIsCMOEnabled (
> > + VOID
> > + )
> > +{
> > + // TODO: Add check for CMO from CPU HOB.
>
> Too many TODOs? One TODO at the top of the file (mentioning feature
> detection, cache line size detection) should be enough. There's no
> point in peppering these out throughout the file :)
>
> Done.
> > + // If CMO is disabled in HW, skip Override check
> > + // Otherwise this PCD can override settings
> > + return ((PcdGet64 (PcdRiscVFeatureOverride) &
> RISCV_CPU_FEATURE_CMO_BITMASK) != 0);
> > +}
> > +
> > +/**
> > + Performs required opeartion on cache lines in the cache coherency
> domain
> > + of the calling CPU. If Address is not aligned on a cache line
> boundary,
> > + then entire cache line containing Address is operated. If Address +
> Length
> > + is not aligned on a cache line boundary, then the entire cache line
> > + containing Address + Length -1 is operated.
> > + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
> > + @param Address The base address of the cache lines to
> > + invalidate.
> > + @param Length The number of bytes to invalidate from the instruction
> > + cache.
> > + @param Op Type of CMO operation to be performed
> > + @return Address.
> > +
> > +**/
> > +STATIC
> > +VOID
> > +CacheOpCacheRange (
> > + IN VOID *Address,
> > + IN UINTN Length,
> > + IN CACHE_OP Op
> > + )
> > +{
> > + UINTN CacheLineSize;
> > + UINTN Start;
> > + UINTN End;
> > +
> > + if (Length == 0) {
> > + return;
> > + }
> > +
> > + if ((Op != Invld) && (Op != Flush) && (Op != Clean)) {
> > + return;
> > + }
> > +
> > + ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Address));
> > +
> > + CacheLineSize = RISCV_CACHE_BLOCK_SIZE;
> > +
> > + Start = (UINTN)Address;
> > + //
> > + // Calculate the cache line alignment
> > + //
> > + End = (Start + Length + (CacheLineSize - 1)) & ~(CacheLineSize -
> 1);
> > + Start &= ~((UINTN)CacheLineSize - 1);
> > +
> > + DEBUG (
> > + (DEBUG_INFO,
> > + "%a Performing Cache Management Operation %d \n", __func__, Op)
> > + );
>
> nit: Can we pick a log style here? Like <something>: <log message>
> In this case, "CacheOpCacheRange: Performing ...". It's just prettier
> and more greppable.
>
> Done.
> > +
> > + do {
> > + switch (Op) {
> > + case Invld:
> > + RiscVCpuCacheInvalAsmCbo (Start);
> > + break;
> > + case Flush:
> > + RiscVCpuCacheFlushAsmCbo (Start);
> > + break;
> > + case Clean:
> > + RiscVCpuCacheCleanAsmCbo (Start);
> > + break;
> > + default:
> > + break;
> > + }
> > +
> > + Start = Start + CacheLineSize;
> > + } while (Start != End);
> > +}
> >
> > /**
> > Invalidates the entire instruction cache in cache coherency domain of
> the
> > - calling CPU.
> > + calling CPU. Risc-V does not have currently an CBO implementation
> which can
> > + invalidate entire I-cache. Hence using Fence instruction for now.
> P.S. Fence
> nit: Invalidate *the* entire I-cache
>
> Done.
> Also, what do you mean? 1) you're calling CacheOpCacheRange for the range
> 2) please don't mix CBO and CMO. Too much terminology :)
>
> Modified naming to be consistent. All CMO now.
> Does Zicbom only operate on the dcache? Or does it also touch the
> icache? As far as I'm aware, riscv does not require a dcache/icache
> coherency (like ARM), but a quick stroll through the extension's spec
> didn't lead me to much.
>
My understanding is that Zicbom operates on both. It just needs an address
to act on.
> > + instruction may or may not implement full I-cache invd functionality
> on all
> > + implementations.
> >
> > **/
> > VOID
> > @@ -56,12 +158,17 @@ InvalidateInstructionCacheRange (
> > IN UINTN Length
> > )
> > {
> > - DEBUG (
> > - (DEBUG_WARN,
> > - "%a:RISC-V unsupported function.\n"
> > - "Invalidating the whole instruction cache instead.\n", __func__)
> > - );
> > - InvalidateInstructionCache ();
> > + if (RiscVIsCMOEnabled ()) {
> > + CacheOpCacheRange (Address, Length, Invld);
> > + } else {
> > + DEBUG (
> > + (DEBUG_WARN,
> > + "%a:RISC-V unsupported function.\n"
> > + "Invalidating the whole instruction cache instead.\n", __func__)
> > + );
> nit: "%a: ", with a space, but i'd probably write this bit as
> > + "%a: Zicbom not enabled, invalidating the whole instruction
> cache instead.\n", __func__)
>
> Done with minor modification.
Given that this may be repeatedly called, can we just warn once (e.g
> on a constructor) that CMO is disabled and leave this be? Since the
> cache management is in fact being done correctly, but just in a slower
> way.
>
> > + InvalidateInstructionCache ();
> > + }
> > +
> > return Address;
> > }
> >
> > @@ -117,7 +224,12 @@ WriteBackInvalidateDataCacheRange (
> > IN UINTN Length
> > )
> > {
> > - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));
> > + if (RiscVIsCMOEnabled ()) {
> > + CacheOpCacheRange (Address, Length, Flush);
> > + } else {
> > + DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n",
> __func__));
>
> Ok, so here it may make sense to ASSERT, as you're no longer complying
> to the function's behavior (and this is unsafe).
>
> Done.
> > + }
> > +
> > return Address;
> > }
> >
> > @@ -156,10 +268,7 @@ WriteBackDataCache (
> >
> > If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
> >
> > - @param Address The base address of the data cache lines to write
> back. If
> > - the CPU is in a physical addressing mode, then
> Address is a
> > - physical address. If the CPU is in a virtual
> addressing
> > - mode, then Address is a virtual address.
> > + @param Address The base address of the data cache lines to write
> back.
> > @param Length The number of bytes to write back from the data cache.
> >
> > @return Address of cache written in main memory.
> > @@ -172,7 +281,12 @@ WriteBackDataCacheRange (
> > IN UINTN Length
> > )
> > {
> > - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));
> > + if (RiscVIsCMOEnabled ()) {
> > + CacheOpCacheRange (Address, Length, Clean);
> > + } else {
> > + DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n",
> __func__));
>
> Same comment here WRT assert.
>
Done.
> > + }
> > +
> > return Address;
> > }
> >
> > @@ -214,10 +328,7 @@ InvalidateDataCache (
> >
> > If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
> >
> > - @param Address The base address of the data cache lines to
> invalidate. If
> > - the CPU is in a physical addressing mode, then
> Address is a
> > - physical address. If the CPU is in a virtual
> addressing mode,
> > - then Address is a virtual address.
> > + @param Address The base address of the data cache lines to
> invalidate.
> > @param Length The number of bytes to invalidate from the data cache.
> >
> > @return Address.
> > @@ -230,6 +341,16 @@ InvalidateDataCacheRange (
> > IN UINTN Length
> > )
> > {
> > - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));
> > + if (RiscVIsCMOEnabled ()) {
> > + CacheOpCacheRange (Address, Length, Invld);
> > + } else {
> > + DEBUG (
> > + (DEBUG_WARN,
> > + "%a:RISC-V unsupported function.\n"
> > + "Invalidating the whole Data cache instead.\n", __func__)
> > + );
>
> Aaaand the same comment here WRT warning.
>
> Done.
> Pedro
>
--
Thanks!
=D
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^ permalink raw reply [flat|nested] 13+ messages in thread
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Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-10-21 17:33 [edk2-devel] [PATCH v6 0/5] Cache Management Operations Support For RISC-V Dhaval Sharma
2023-10-21 17:33 ` [edk2-devel] [PATCH v6 1/5] MdePkg: Move RISC-V Cache Management Declarations Into BaseLib Dhaval Sharma
2023-10-24 12:32 ` Laszlo Ersek
2023-10-21 17:33 ` [edk2-devel] [PATCH v6 2/5] MdePkg: Rename Cache Management Function To Clarify Fence Based Op Dhaval Sharma
2023-10-24 12:34 ` Laszlo Ersek
2023-10-21 17:33 ` [edk2-devel] [PATCH v6 3/5] MdePkg: Implement RISC-V Cache Management Operations Dhaval Sharma
2023-10-24 12:39 ` Laszlo Ersek
2023-10-21 17:33 ` [edk2-devel] [PATCH v6 4/5] MdePkg: Utilize Cache Management Operations Implementation For RISC-V Dhaval Sharma
2023-10-24 12:45 ` Laszlo Ersek
2023-10-24 20:09 ` Pedro Falcato
2023-10-29 14:48 ` Dhaval Sharma
2023-10-21 17:33 ` [edk2-devel] [PATCH v6 5/5] OvmfPkg/RiscVVirt: Override for RV CPU Features Dhaval Sharma
2023-10-24 12:45 ` Laszlo Ersek
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