From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 93A2FAC0A4B for ; Tue, 31 Oct 2023 05:13:52 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=EwpK7cNPIVi2A29A5lkT1xecUDxA4siQUR0VLZsLHxw=; c=relaxed/simple; d=groups.io; h=MIME-Version:References:In-Reply-To:From:Date:Message-ID:Subject:To:Cc:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type; s=20140610; t=1698729231; v=1; b=YITgNDJCBCTCDMTGMl6OJmoUmRHEOpJpkjGaqSBuaUsUOpsvCS8ovNk99r0u8mFQASIbJGPs CLJcJjSBc6yZbwSZLeJmxFTikowuq1aL+y/BY+8fRBelVqFQXcbmqZisbK9eDkevLzel/VxJ3lH rY9dZB0u9D2rZpCWEgYCpHxA= X-Received: by 127.0.0.2 with SMTP id CDhAYY7687511x3D5d6jLG9N; Mon, 30 Oct 2023 22:13:51 -0700 X-Received: from mail-qk1-f181.google.com (mail-qk1-f181.google.com [209.85.222.181]) by mx.groups.io with SMTP id smtpd.web11.180307.1698729229967162470 for ; Mon, 30 Oct 2023 22:13:50 -0700 X-Received: by mail-qk1-f181.google.com with SMTP id af79cd13be357-778a20df8c3so375565885a.3 for ; Mon, 30 Oct 2023 22:13:49 -0700 (PDT) X-Gm-Message-State: LhRx7qCZ5RwYAKub6eJjr3uqx7686176AA= X-Google-Smtp-Source: AGHT+IEUgrWiYvWgwMhwDYvJhL9C9G21uLVVIQ9r1xtiaFgvpaGBtFamhFDK02Ndt/RIaHDpLj12Yx+nM1zrJro65VE= X-Received: by 2002:a05:6214:29eb:b0:66d:a4d6:d515 with SMTP id jv11-20020a05621429eb00b0066da4d6d515mr13234095qvb.35.1698729228801; Mon, 30 Oct 2023 22:13:48 -0700 (PDT) MIME-Version: 1.0 References: <20231029144613.150580-1-dhaval@rivosinc.com> In-Reply-To: From: "Dhaval Sharma" Date: Tue, 31 Oct 2023 10:43:38 +0530 Message-ID: Subject: Re: [edk2-devel] [PATCH v7 0/5] Cache Management Operations Support For RISC-V To: "Warkentin, Andrei" Cc: "devel@edk2.groups.io" , Ard Biesheuvel , "Yao, Jiewen" , "Justen, Jordan L" , Gerd Hoffmann , Sunil V L , Laszlo Ersek , "Kinney, Michael D" , "Gao, Liming" , "Liu, Zhiguang" , Daniel Schaefer Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dhaval@rivosinc.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Type: multipart/alternative; boundary="00000000000040ae850608fc3820" X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=YITgNDJC; dmarc=none; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io --00000000000040ae850608fc3820 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Here we go. https://github.com/tianocore/edk2/pull/4974 On Tue, Oct 31, 2023 at 9:46=E2=80=AFAM Warkentin, Andrei < andrei.warkentin@intel.com> wrote: > Hi Dhaval, > > Do you mind sharing the repo with the full patch set? Like a github link? > > A > > > -----Original Message----- > > From: Dhaval > > Sent: Sunday, October 29, 2023 9:46 AM > > To: devel@edk2.groups.io > > Cc: Ard Biesheuvel ; Yao, Jiewen > > ; Justen, Jordan L ; > Gerd > > Hoffmann ; Sunil V L ; > > Warkentin, Andrei ; Laszlo Ersek > > ; Kinney, Michael D ; > > Gao, Liming ; Liu, Zhiguang > > ; Daniel Schaefer > > Subject: [PATCH v7 0/5] Cache Management Operations Support For RISC-V > > > > Implementing code to support Cache Management Operations (CMO) defined > > by RISC-V CMO instructions.https://github.com/riscv/riscv-CMOs > > This is a re-write of original series v5. > > The patchset contains 5 patches- created based on V5 feedback. > > 1. Restructuring of existing code and move instruction declarations int= o > > BaseLib 2. Renaming existing functions to denote type of instruction > used to > > maanage cache. > > This is useful for further patches where more cache management > > instructions are added. > > 3. Add the new cache maintenance operations to BaseLib, including the > > new assembly instruction encodings. > > 4. Update BaseCacheMaintenanceLib (utilizing the new BaseLib primitives= ) > 5. > > Add platform level PCD to allow overriding of RISC-V features. > > > > Cc: Ard Biesheuvel > > Cc: Jiewen Yao > > Cc: Jordan Justen > > Cc: Gerd Hoffmann > > Cc: Sunil V L > > Cc: Andrei Warkentin > > Cc: Laszlo Ersek > > Cc: Michael D Kinney > > Cc: Liming Gao > > Cc: Zhiguang Liu > > Cc: Daniel Schaefer > > > > Dhaval (5): > > MdePkg: Move RISC-V Cache Management Declarations Into BaseLib > > MdePkg: Rename Cache Management Function To Clarify Fence Based Op > > MdePkg: Implement RISC-V Cache Management Operations > > MdePkg: Utilize Cache Management Operations Implementation For RISC-V > > OvmfPkg/RiscVVirt: Override for RV CPU Features > > > > MdePkg/MdePkg.dec | > 8 + > > OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | > 1 + > > MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf | > > 5 + > > MdePkg/Library/BaseLib/BaseLib.inf | > 2 +- > > MdePkg/Include/Library/BaseLib.h | > 53 ++++++ > > MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 1= 72 > > ++++++++++++++++---- > > MdePkg/Include/RiscV64/RiscVasm.inc | > 19 +++ > > MdePkg/Library/BaseLib/RiscV64/FlushCache.S | > 21 --- > > MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S | > 38 +++++ > > MdePkg/MdePkg.uni | > 4 + > > 10 files changed, 269 insertions(+), 54 deletions(-) create mode 1006= 44 > > MdePkg/Include/RiscV64/RiscVasm.inc > > delete mode 100644 MdePkg/Library/BaseLib/RiscV64/FlushCache.S > > create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S > > > > -- > > 2.39.2 > > --=20 Thanks! =3DD -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#110364): https://edk2.groups.io/g/devel/message/110364 Mute This Topic: https://groups.io/mt/102256459/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- --00000000000040ae850608fc3820 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Here we go.=C2=A0https://github.com/tianocore/edk2/pull/4974


On Tue, Oct 31, 2023 at 9:46=E2=80=AFAM Warkentin, Andrei <andrei.warkentin@intel.com> wrote= :
Hi Dhaval,

Do you mind sharing the repo with the full patch set? Like a github link?
A

> -----Original Message-----
> From: Dhaval <dhaval@rivosinc.com>
> Sent: Sunday, October 29, 2023 9:46 AM
> To: devel@ed= k2.groups.io
> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>; Yao, Jiewen
> <jiewen.y= ao@intel.com>; Justen, Jordan L <jordan.l.justen@intel.com>; Gerd
> Hoffmann <kr= axel@redhat.com>; Sunil V L <sunilvl@ventanamicro.com>;
> Warkentin, Andrei <andrei.warkentin@intel.com>; Laszlo Ersek
> <lersek@redh= at.com>; Kinney, Michael D <michael.d.kinney@intel.com>;
> Gao, Liming <gaoliming@byosoft.com.cn>; Liu, Zhiguang
> <zhigua= ng.liu@intel.com>; Daniel Schaefer <git@danielschaefer.me>
> Subject: [PATCH v7 0/5] Cache Management Operations Support For RISC-V=
>
> Implementing code to support Cache Management Operations (CMO) defined=
> by RISC-V CMO instructions.https://github.com/riscv/riscv-CM= Os
> This is a re-write of original series v5.
> The patchset contains 5 patches- created based on V5 feedback.
> 1. Restructuring of existing code and move instruction declarations in= to
> BaseLib 2. Renaming existing functions to denote type of instruction u= sed to
> maanage cache.
>=C2=A0 =C2=A0 This is useful for further patches where more cache manag= ement
> instructions are added.
> 3. Add the new cache maintenance operations to BaseLib, including the<= br> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 new assembly instruction encodings.
> 4. Update BaseCacheMaintenanceLib (utilizing the new BaseLib primitive= s) 5.
> Add platform level PCD to allow overriding of RISC-V features.
>
> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
> Cc: Jiewen Yao <jiewen.yao@intel.com>
> Cc: Jordan Justen <jordan.l.justen@intel.com>
> Cc: Gerd Hoffmann <kraxel@redhat.com>
> Cc: Sunil V L <sunilvl@ventanamicro.com>
> Cc: Andrei Warkentin <andrei.warkentin@intel.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Liming Gao <gaoliming@byosoft.com.cn>
> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
> Cc: Daniel Schaefer <git@danielschaefer.me>
>
> Dhaval (5):
>=C2=A0 =C2=A0MdePkg: Move RISC-V Cache Management Declarations Into Bas= eLib
>=C2=A0 =C2=A0MdePkg: Rename Cache Management Function To Clarify Fence = Based Op
>=C2=A0 =C2=A0MdePkg: Implement RISC-V Cache Management Operations
>=C2=A0 =C2=A0MdePkg: Utilize Cache Management Operations Implementation= For RISC-V
>=C2=A0 =C2=A0OvmfPkg/RiscVVirt: Override for RV CPU Features
>
>=C2=A0 MdePkg/MdePkg.dec=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A08 + >=C2=A0 OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 |=C2=A0 =C2=A01 +
>=C2=A0 MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.i= nf |
> 5 +
>=C2=A0 MdePkg/Library/BaseLib/BaseLib.inf=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0|=C2=A0 =C2=A02 +-
>=C2=A0 MdePkg/Include/Library/BaseLib.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0|=C2=A0 53 ++++++
>=C2=A0 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c=C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | 172
> ++++++++++++++++----
>=C2=A0 MdePkg/Include/RiscV64/RiscVasm.inc=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 |=C2=A0 19 +++
>=C2=A0 MdePkg/Library/BaseLib/RiscV64/FlushCache.S=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 21 -= --
>=C2=A0 MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 38 +++++
>=C2=A0 MdePkg/MdePkg.uni=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A04 + >=C2=A0 10 files changed, 269 insertions(+), 54 deletions(-)=C2=A0 creat= e mode 100644
> MdePkg/Include/RiscV64/RiscVasm.inc
>=C2=A0 delete mode 100644 MdePkg/Library/BaseLib/RiscV64/FlushCache.S >=C2=A0 create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt= .S
>
> --
> 2.39.2



--
Thanks!
=3DD
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