From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::631; helo=mail-pl1-x631.google.com; envelope-from=bcr@google.com; receiver=edk2-devel@lists.01.org Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2EA4721193797 for ; Wed, 21 Nov 2018 17:29:08 -0800 (PST) Received: by mail-pl1-x631.google.com with SMTP id s5-v6so7945653plq.11 for ; Wed, 21 Nov 2018 17:29:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=wDlp+86Zec4hvl8z+DVQAQgdvxE9jwCQMaCr5KXMX0A=; b=YRpLuRR2O5hLIxvReMD8kTLb0EHP87Q7CZLcpGe7FPxkFYxTlXgiRgnXyWmiMsAC4z oTDZv1A9Hyh3Tqk+WHvSWU19qiserjXkevD5Ai9T1JggSBieKUFY9D1acAp+Sx3eUXX2 Iw8OikRkGlJHWyRipJs7MhybV2R3RW5ViM7uPQ8FtYoiC39eMR3mEoSAfs4QcJX7jdiH OfJehC4C4kXDpaLbppNdQcJEQtX9hi9g0MOXCve6EGKICMoSiGFNW/vgAMklzawpWi+N FWJR/flTF22iwSgQKgSzDgQOGwEE5ch918y0LEzbGWLRq6OkCz3OSqc4DJ4odOLy0NUv SAQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=wDlp+86Zec4hvl8z+DVQAQgdvxE9jwCQMaCr5KXMX0A=; b=LV8Eh93v3W2OiHD4i30qNz/HpckZoUuagXDqi0NloPD6Y35mXv9HRQ+yPwOkyXNqxX rM30zwC8CfKopfTf4tIDQ84uSd5H2v5WIspRHgkVAT8Uol8Xz2T2+i+BgM28AJK82iEV phWDVKNYezsTiXFZXiixh8roBofsJgbYPwlssLLiPH0a6652W0h0+Q16nVH6DmDK6xDo 5ulO/ssabRpAU324wY3CTL2WFnKfi3KAcVFoV8Pn8hMQ80pBMMYejFAzzd1GOO8/P93B yAY750KSt9BLcXFHM+opYiN+iI3ESipfh2S/MsT14DgxPURkvsLQn2c3KcDlkKxS3WyA X0HA== X-Gm-Message-State: AA+aEWZNwJhiMNfLa83ny4/CS3Tl83naU4f04P5xMKa7ofeKAz1Px/I8 yPC9Mf513hREUEg0KGOxnd44S9mVGdL22tx9NuS9cQ== X-Google-Smtp-Source: AFSGD/WfXoMYrh0RPKW7oEualjY5O8N+uuXlBX9q2ey3Z3uPydGGwJODBbYJFndAhv9EPIoXnunEqNslmFZ3D2bymM0= X-Received: by 2002:a63:151f:: with SMTP id v31mr8036106pgl.34.1542850148186; Wed, 21 Nov 2018 17:29:08 -0800 (PST) MIME-Version: 1.0 References: <8147e54ded6e405abdafbed45bd52199@SCL-EXCHMB-13.phoenix.com> In-Reply-To: <8147e54ded6e405abdafbed45bd52199@SCL-EXCHMB-13.phoenix.com> From: Bryan Rosario Date: Wed, 21 Nov 2018 17:28:56 -0800 Message-ID: To: Ken_Taylor@phoenix.com Cc: Alain Gefflaut , edk2-devel@lists.01.org X-Content-Filtered-By: Mailman/MimeDel 2.1.29 Subject: Re: Hardcoded IDE Controller B/D/F (0/1/1) in BdsPlatform.c? X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 22 Nov 2018 01:29:09 -0000 Content-Type: text/plain; charset="UTF-8" Hi Ken, That's what I had guessed -- thanks for confirming that it's platform specific. In my use case, I actually want the code to work on multiple hardware configurations, so I can't just replace the hardcoded B/D/F with the one used by a particular platform. Does the change to SataController.c that I mentioned in the original email make sense? I've tested it and confirmed that it works on my platform, but I want to get a sanity check that that is an appropriate place to put this code. Thanks, Bryan On Wed, Nov 21, 2018 at 4:48 PM Ken Taylor wrote: > Hi Bryan, > > That appears to be silicon or platform specific code. It's intended for > one specific hardware configuration. Unless you have an identical hardware > configuration, those particular register writes are actually nonsensical. > > I think what you need to do is consult the silicon specific documentation > for your particular hardware configuration, and determine what silicon > specific registers need to be configured to what specific values to support > your specific hardware design. > > Regards, > -Ken. > > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of > Bryan Rosario via edk2-devel > Sent: Wednesday, November 21, 2018 4:07 PM > To: edk2-devel@lists.01.org > Cc: Alain Gefflaut > Subject: [edk2] Hardcoded IDE Controller B/D/F (0/1/1) in BdsPlatform.c? > > Hi all, > > I noticed that there is apparently a hardcoded B/D/F for an IDE Controller > in BdsPlatform.c, when setting bit 15 of a particular register: > > https://github.com/tianocore/edk2/blob/14923c1a6bf9940b48feeaf47cb5d6c662b6528c/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c#L1612-L1617 > . > > Why is this hardcoded? Is it just old code that has hung around? I noticed > that this code is from this commit, and the surrounding code at the time > had lots of hardcoded B/D/Fs: > > https://github.com/tianocore/edk2/commit/40f2c454343be84ab3bacf9955cc8d7842c70b5c > . > > The context of this question is that I'm trying to make this work in a > configuration with an IDE Controller located at a different B/D/F, and so > the hardcoded value of 0/1/1 doesn't work for me. > > If I want to change this so that it's not hardcoded, what is a good > approach? I've added some code locally to the IdeInitSetTiming function in > SataController.c to set the bit using the PciIo structure which is opened > specifically on the controller in question -- does that sound like the > right approach? > Link to the function I'm referring to: > > https://github.com/tianocore/edk2/blob/f6b0258d25a63ae3d3bc6430abe30fb625abc52a/OvmfPkg/SataControllerDxe/SataController.c#L1091-L1099 > > Thanks, > Bryan > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel > >