From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-ua1-f53.google.com (mail-ua1-f53.google.com [209.85.222.53]) by mx.groups.io with SMTP id smtpd.web10.6576.1593075503783060879 for ; Thu, 25 Jun 2020 01:58:24 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@9elements.com header.s=google header.b=ZQXjXono; spf=pass (domain: 9elements.com, ip: 209.85.222.53, mailfrom: marcello.bauer@9elements.com) Received: by mail-ua1-f53.google.com with SMTP id c7so165890uap.0 for ; Thu, 25 Jun 2020 01:58:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=9elements.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=OGc8Zr3HdBahWuaqnLKINnr6oy14C0DYIUT5wu9n3TA=; b=ZQXjXono4CVehFFLGHjx8QAat6UlciiNkU1ZZlNGhFUynTx6/hbyfd0Oz/0zVL2J/w 3Kn2jtTLc0mxYxdqYB2d9T43Kl98GVZcXEX0OtGf6wSHVDihlqAcLPcj/PH+zEgQFZun 5iBPPzSC0JGumQeJqnP0TRTWleQEtJTfSxL2+2KDtlAaGaTO0P2TRjvJ8MY2aEqtHYMt HI6sfQ3vUfEhe5N0wek2JqE2Hn29Ahk0P/MIhNd6EtRCr1vhYFNO3L9Q4kIxOf8qCWy1 Z/Z9mW9fP7VBnMPZLbVsI9ozRQBjLBHtlStUbKWu+UOmpqS4fWi/VUC40V+gGeX8rgu3 hXpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=OGc8Zr3HdBahWuaqnLKINnr6oy14C0DYIUT5wu9n3TA=; b=fNGu37Ckt8/x/j2MVMahYWmGBraBkdZuHnsuZOd+zqeys1+D8QrTr70jgKAh8Gw85V vEpmNhCnGWdQygfZVy++r0k8DGWvM7N2gQTc1NXsOCUm2Jp73BHmrgpQSmwVaxf8zeit tKln96ZQ3X/xrBucahiHFT07VXIsTijZ9Ym/Kzm7KbKOEC9aE+1sUPrlmjdrmdt57mAp cg9wa2zfzpMzvR4pg0SvSC5NThzFVyNcP4jOMAC3Um74LwvH6dhRmw5hUlbYSdCZB7TV HdiORSgmQ67FD5ryiTGtoqJ6/Ww9kooHKKcb8M9Sctgg8lbZPr4KVQ15m4pIBnTXBOIY hQcQ== X-Gm-Message-State: AOAM532899jmA2qPEAngclYG/KzWLU+ALq0TMOCV6jMHp6yJ+pIH2pPt 1OcGmJA1QC1epn6Uf7H5yfh8TlP8mX3IgeenRYrPH+rb6Xnvew== X-Google-Smtp-Source: ABdhPJynuggO7FlLNhAu+jkQv3c8//1w7AgV3ULAnmav5Vz93N/rV1/KJtNuqQnuA6uymSsqrgNbrn6LjHqUpvKWHnU= X-Received: by 2002:ab0:4425:: with SMTP id m34mr2202392uam.27.1593075502176; Thu, 25 Jun 2020 01:58:22 -0700 (PDT) MIME-Version: 1.0 References: <20200624102545.21390-1-marcello.bauer@9elements.com> <20200624102545.21390-3-marcello.bauer@9elements.com> In-Reply-To: From: "Marcello Sylvester Bauer" Date: Thu, 25 Jun 2020 10:58:10 +0200 Message-ID: Subject: Re: [edk2-devel] [PATCH v1 2/2] UefiPayloadPkg: Runtime MMCONF To: "Dong, Guo" Cc: "devel@edk2.groups.io" , Patrick Rudolph , Christian Walter , "Ma, Maurice" , "Desimone, Nathaniel L" , "Zeng, Star" Content-Type: multipart/alternative; boundary="0000000000006876ba05a8e4cb95" --0000000000006876ba05a8e4cb95 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Guo, didn't see it, my bad. Next time I will rebase again before submitting. Best regards, Marcello On Wed, Jun 24, 2020 at 4:41 PM Dong, Guo wrote: > > Hi Bauer, > > Please check latest code, Ray just checked in a patch to remove hardcoded > PCIe base address as below. > > commit 3900a63e3a1b9ba9a4105bedead7b986188cec2c > Author: Ray Ni > Date: Wed Jun 17 16:34:29 2020 +0800 > UefiPayloadPkg/Pci: Use the PCIE Base Addr stored in AcpiBoardInfo HO= B > > Thanks, > Guo > > > -----Original Message----- > > From: devel@edk2.groups.io On Behalf Of > > Marcello Sylvester Bauer > > Sent: Wednesday, June 24, 2020 3:26 AM > > To: devel@edk2.groups.io > > Cc: Patrick Rudolph ; Christian Walter > > ; Ma, Maurice ; > > Desimone, Nathaniel L ; Zeng, Star > > > > Subject: [edk2-devel] [PATCH v1 2/2] UefiPayloadPkg: Runtime MMCONF > > > > From: Patrick Rudolph > > > > * Don't hardcode PCIE_BASE at build time > > * Support arbitrary platforms with different or even no MMCONF space > > * Fix buffer overflow accessing MMCONF where less than 256 buses are > > exposed > > * Use PciCfg8 for PCI access in PEI, which is only used for debugging > > > > Signed-off-by: Patrick Rudolph > > Signed-off-by: Marcello Sylvester Bauer > > Cc: Patrick Rudolph > > Cc: Christian Walter > > Cc: Maurice Ma > > Cc: Nate DeSimone > > Cc: Star Zeng > > --- > > UefiPayloadPkg/UefiPayloadPkgIa32.dsc | > 16 +- > > UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc | > 16 +- > > UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLib.inf | > 46 + > > UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf | > 42 > > + > > UefiPayloadPkg/Library/BasePciExpressLib/PciExpressLib.c | > 1455 > > ++++++++++++++++++++ > > UefiPayloadPkg/Library/BasePciLibPciExpress/PciLib.c | > 1302 > > ++++++++++++++++++ > > UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLib.uni | > 17 + > > UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.uni | > 17 > > + > > 8 files changed, 2885 insertions(+), 26 deletions(-) > > > > diff --git a/UefiPayloadPkg/UefiPayloadPkgIa32.dsc > > b/UefiPayloadPkg/UefiPayloadPkgIa32.dsc > > index c6c47833871b..48b03af6f223 100644 > > --- a/UefiPayloadPkg/UefiPayloadPkgIa32.dsc > > +++ b/UefiPayloadPkg/UefiPayloadPkgIa32.dsc > > @@ -37,11 +37,6 @@ [Defines] > > # > > > > DEFINE MAX_LOGICAL_PROCESSORS =3D 64 > > > > > > > > - # > > > > - # PCI options > > > > - # > > > > - DEFINE PCIE_BASE =3D 0xE0000000 > > > > - > > > > # > > > > # Serial port set up > > > > # > > > > @@ -121,13 +116,9 @@ [LibraryClasses] > > PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf > > > > CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf > > > > IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf > > > > -!if $(PCIE_BASE) =3D=3D 0 > > > > - PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf > > > > PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf > > > > -!else > > > > - PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf > > > > - PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf > > > > -!endif > > > > + > > > PciLib|UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.i= nf > > > > + > > > PciExpressLib|UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLib.= i > > nf > > > > > > PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibP > > ci.inf > > > > PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf > > > > > > PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/Base > > PeCoffGetEntryPointLib.inf > > > > @@ -216,6 +207,7 @@ [LibraryClasses.IA32.SEC] > > [LibraryClasses.IA32.PEI_CORE, LibraryClasses.IA32.PEIM] > > > > PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf > > > > HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf > > > > + PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf > > > > > > MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemory > > AllocationLib.inf > > > > > > ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiR > > eportStatusCodeLib.inf > > > > > > ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiEx > > tractGuidedSectionLib.inf > > > > @@ -286,8 +278,6 @@ [PcdsFixedAtBuild] > > gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE > > > > gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, > > 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, > 0x66, > > 0x23, 0x31 } > > > > > > > > - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|$(PCIE_BASE) > > > > - > > > > !if $(SOURCE_DEBUG_ENABLE) > > > > > > gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x > > 2 > > > > !endif > > > > diff --git a/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc > > b/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc > > index 5559b1258521..af951ee5aec0 100644 > > --- a/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc > > +++ b/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc > > @@ -38,11 +38,6 @@ [Defines] > > # > > > > DEFINE MAX_LOGICAL_PROCESSORS =3D 64 > > > > > > > > - # > > > > - # PCI options > > > > - # > > > > - DEFINE PCIE_BASE =3D 0xE0000000 > > > > - > > > > # > > > > # Serial port set up > > > > # > > > > @@ -122,13 +117,9 @@ [LibraryClasses] > > PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf > > > > CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf > > > > IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf > > > > -!if $(PCIE_BASE) =3D=3D 0 > > > > - PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf > > > > PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf > > > > -!else > > > > - PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf > > > > - PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf > > > > -!endif > > > > + > > > PciLib|UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.i= nf > > > > + > > > PciExpressLib|UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLib.= i > > nf > > > > > > PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibP > > ci.inf > > > > PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf > > > > > > PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/Base > > PeCoffGetEntryPointLib.inf > > > > @@ -217,6 +208,7 @@ [LibraryClasses.IA32.SEC] > > [LibraryClasses.IA32.PEI_CORE, LibraryClasses.IA32.PEIM] > > > > PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf > > > > HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf > > > > + PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf > > > > > > MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemory > > AllocationLib.inf > > > > > > ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiR > > eportStatusCodeLib.inf > > > > > > ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiEx > > tractGuidedSectionLib.inf > > > > @@ -288,8 +280,6 @@ [PcdsFixedAtBuild] > > gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|TRUE > > > > gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, > > 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, > 0x66, > > 0x23, 0x31 } > > > > > > > > - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|$(PCIE_BASE) > > > > - > > > > !if $(SOURCE_DEBUG_ENABLE) > > > > > > gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x > > 2 > > > > !endif > > > > diff --git > a/UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLib.inf > > b/UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLib.inf > > new file mode 100644 > > index 000000000000..9f052c0a2e65 > > --- /dev/null > > +++ b/UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLib.inf > > @@ -0,0 +1,46 @@ > > +## @file > > > > +# Instance of PCI Express Library using the 256 MB PCI Express MMIO > > window. > > > > +# > > > > +# PCI Express Library that uses the 256 MB PCI Express MMIO window to > > perform > > > > +# PCI Configuration cycles. Layers on top of an I/O Library instance. > > > > +# > > > > +# Copyright (c) 2007 - 2018, Intel Corporation. All rights > reserved.
> > > > +# > > > > +# SPDX-License-Identifier: BSD-2-Clause-Patent > > > > +# > > > > +# > > > > +## > > > > + > > > > +[Defines] > > > > + INF_VERSION =3D 0x00010005 > > > > + BASE_NAME =3D BasePciExpressLib > > > > + MODULE_UNI_FILE =3D BasePciExpressLib.uni > > > > + FILE_GUID =3D 287e50f4-a188-4699-b907-3e4080ca5= 688 > > > > + MODULE_TYPE =3D BASE > > > > + VERSION_STRING =3D 1.0 > > > > + LIBRARY_CLASS =3D PciExpressLib > > > > + CONSTRUCTOR =3D PciExpressLibInitialize > > > > + > > > > +# > > > > +# VALID_ARCHITECTURES =3D IA32 X64 EBC > > > > +# > > > > + > > > > +[Sources] > > > > + PciExpressLib.c > > > > + > > > > +[Packages] > > > > + MdePkg/MdePkg.dec > > > > + UefiPayloadPkg/UefiPayloadPkg.dec > > > > + > > > > +[LibraryClasses] > > > > + BaseLib > > > > + DebugLib > > > > + HobLib > > > > + IoLib > > > > + > > > > +[Guids] > > > > + gUefiAcpiBoardInfoGuid > > > > + > > > > +[Pcd] > > > > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES > > > > + > > > > diff --git > > a/UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf > > b/UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf > > new file mode 100644 > > index 000000000000..0858e49a47ae > > --- /dev/null > > +++ > b/UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf > > @@ -0,0 +1,42 @@ > > +## @file > > > > +# Instance of PCI Library based on PCI Express Library. > > > > +# > > > > +# PCI Library that uses the 256 MB PCI Express MMIO window to perform > > PCI > > > > +# Configuration cycles. Layers on one PCI Express Library instance. > > > > +# > > > > +# Copyright (c) 2007 - 2018, Intel Corporation. All rights > reserved.
> > > > +# > > > > +# SPDX-License-Identifier: BSD-2-Clause-Patent > > > > +# > > > > +# > > > > +## > > > > + > > > > +[Defines] > > > > + INF_VERSION =3D 0x00010005 > > > > + BASE_NAME =3D BasePciLibPciExpress > > > > + MODULE_UNI_FILE =3D BasePciLibPciExpress.uni > > > > + FILE_GUID =3D 8987081e-daeb-44a9-8bef-a195b22d9= 417 > > > > + MODULE_TYPE =3D BASE > > > > + VERSION_STRING =3D 1.0 > > > > + LIBRARY_CLASS =3D PciLib > > > > + CONSTRUCTOR =3D PciLibInitialize > > > > + > > > > +# > > > > +# VALID_ARCHITECTURES =3D IA32 X64 > > > > +# > > > > + > > > > +[Sources] > > > > + PciLib.c > > > > + > > > > +[Packages] > > > > + MdePkg/MdePkg.dec > > > > + UefiPayloadPkg/UefiPayloadPkg.dec > > > > + > > > > +[Guids] > > > > + gUefiAcpiBoardInfoGuid > > > > + > > > > +[LibraryClasses] > > > > + PciExpressLib > > > > + PciCf8Lib > > > > + BaseLib > > > > + HobLib > > > > diff --git a/UefiPayloadPkg/Library/BasePciExpressLib/PciExpressLib.c > > b/UefiPayloadPkg/Library/BasePciExpressLib/PciExpressLib.c > > new file mode 100644 > > index 000000000000..f3b4582d3c47 > > --- /dev/null > > +++ b/UefiPayloadPkg/Library/BasePciExpressLib/PciExpressLib.c > > @@ -0,0 +1,1455 @@ > > +/** @file > > > > + Functions in this library instance make use of MMIO functions in > IoLib to > > > > + access memory mapped PCI configuration space. > > > > + > > > > + All assertions for I/O operations are handled in MMIO functions in > the IoLib > > > > + Library. > > > > + > > > > + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved. > > > > + SPDX-License-Identifier: BSD-2-Clause-Patent > > > > + > > > > +**/ > > > > + > > > > + > > > > +#include > > > > + > > > > +#include > > > > +#include > > > > +#include > > > > +#include > > > > +#include > > > > + > > > > +#include > > > > +#include > > > > +#include > > > > +#include > > > > + > > > > +#include > > > > +#include > > > > + > > > > +STATIC ACPI_BOARD_INFO mBoardInfo; > > > > +/** > > > > + Assert the validity of a PCI address. > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + > > > > + Return 0xff on transaction outside of the MMCONF space. > > > > + > > > > + @param A The address to validate. > > > > + > > > > +**/ > > > > +#define ASSERT_INVALID_PCI_ADDRESS(A) \ > > > > + ASSERT (((A) & ~0xfffffff) =3D=3D 0); \ > > > > + if ((A) >=3D mBoardInfo.PcieBaseSize) { \ > > > > + return ~0; \ > > > > + } > > > > + > > > > +/** > > > > + Registers a PCI device so PCI configuration registers may be accesse= d > after > > > > + SetVirtualAddressMap(). > > > > + > > > > + Registers the PCI device specified by Address so all the PCI > configuration > > > > + registers associated with that PCI device may be accessed after > > SetVirtualAddressMap() > > > > + is called. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + > > > > + @param Address The address that encodes the PCI Bus, Device, Functi= on > > and > > > > + Register. > > > > + > > > > + @retval RETURN_SUCCESS The PCI device was registered for > runtime > > access. > > > > + @retval RETURN_UNSUPPORTED An attempt was made to call this > > function > > > > + after ExitBootServices(). > > > > + @retval RETURN_UNSUPPORTED The resources required to access th= e > > PCI device > > > > + at runtime could not be mapped. > > > > + @retval RETURN_OUT_OF_RESOURCES There are not enough resources > > available to > > > > + complete the registration. > > > > + > > > > +**/ > > > > +RETURN_STATUS > > > > +EFIAPI > > > > +PciExpressRegisterForRuntimeAccess ( > > > > + IN UINTN Address > > > > + ) > > > > +{ > > > > + ASSERT_INVALID_PCI_ADDRESS (Address); > > > > + return RETURN_UNSUPPORTED; > > > > +} > > > > + > > > > +/** > > > > + Performs platform specific initialization required for the CPU to > access > > > > + the MMCONF space. This function does not initialize the MMCONF > itself. > > > > + > > > > + @retval RETURN_SUCCESS The platform specific initialization > succeeded. > > > > + @retval RETURN_DEVICE_ERROR The platform specific initialization > could > > not be completed. > > > > + > > > > +**/ > > > > +RETURN_STATUS > > > > +EFIAPI > > > > +PciExpressLibInitialize ( > > > > + VOID > > > > + ) > > > > +{ > > > > + EFI_HOB_GUID_TYPE *GuidHob; > > > > + > > > > + // > > > > + // Find the acpi board information guid hob > > > > + // > > > > + GuidHob =3D GetFirstGuidHob (&gUefiAcpiBoardInfoGuid); > > > > + ASSERT (GuidHob !=3D NULL); > > > > + if (GuidHob =3D=3D NULL) { > > > > + return EFI_UNSUPPORTED; > > > > + } > > > > + > > > > + CopyMem (&mBoardInfo, GET_GUID_HOB_DATA (GuidHob), > > sizeof(mBoardInfo)); > > > > + return EFI_SUCCESS; > > > > +} > > > > + > > > > +/** > > > > + Gets the base address of PCI Express. > > > > + > > > > + This internal functions retrieves PCI Express Base Address via a PCD > entry > > > > + PcdPciExpressBaseAddress. > > > > + > > > > + @return The base address of PCI Express. > > > > + > > > > +**/ > > > > +VOID* > > > > +GetPciExpressBaseAddress ( > > > > + VOID > > > > + ) > > > > +{ > > > > + return (VOID*)(UINTN) mBoardInfo.PcieBaseAddress; > > > > +} > > > > + > > > > +/** > > > > + Reads an 8-bit PCI configuration register. > > > > + > > > > + Reads and returns the 8-bit PCI configuration register specified by > Address. > > > > + This function must guarantee that all PCI read and write operations > are > > > > + serialized. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + > > > > + @param Address The address that encodes the PCI Bus, Device, Functi= on > > and > > > > + Register. > > > > + > > > > + @return The read value from the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT8 > > > > +EFIAPI > > > > +PciExpressRead8 ( > > > > + IN UINTN Address > > > > + ) > > > > +{ > > > > + ASSERT_INVALID_PCI_ADDRESS (Address); > > > > + return MmioRead8 ((UINTN) GetPciExpressBaseAddress () + Address); > > > > +} > > > > + > > > > +/** > > > > + Writes an 8-bit PCI configuration register. > > > > + > > > > + Writes the 8-bit PCI configuration register specified by Address wit= h > the > > > > + value specified by Value. Value is returned. This function must > guarantee > > > > + that all PCI read and write operations are serialized. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + > > > > + @param Address The address that encodes the PCI Bus, Device, Functi= on > > and > > > > + Register. > > > > + @param Value The value to write. > > > > + > > > > + @return The value written to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT8 > > > > +EFIAPI > > > > +PciExpressWrite8 ( > > > > + IN UINTN Address, > > > > + IN UINT8 Value > > > > + ) > > > > +{ > > > > + ASSERT_INVALID_PCI_ADDRESS (Address); > > > > + return MmioWrite8 ((UINTN) GetPciExpressBaseAddress () + Address, > > Value); > > > > +} > > > > + > > > > +/** > > > > + Performs a bitwise OR of an 8-bit PCI configuration register with > > > > + an 8-bit value. > > > > + > > > > + Reads the 8-bit PCI configuration register specified by Address, > performs a > > > > + bitwise OR between the read result and the value specified by > > > > + OrData, and writes the result to the 8-bit PCI configuration registe= r > > > > + specified by Address. The value written to the PCI configuration > register is > > > > + returned. This function must guarantee that all PCI read and write > > operations > > > > + are serialized. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + > > > > + @param Address The address that encodes the PCI Bus, Device, Functi= on > > and > > > > + Register. > > > > + @param OrData The value to OR with the PCI configuration register. > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT8 > > > > +EFIAPI > > > > +PciExpressOr8 ( > > > > + IN UINTN Address, > > > > + IN UINT8 OrData > > > > + ) > > > > +{ > > > > + ASSERT_INVALID_PCI_ADDRESS (Address); > > > > + return MmioOr8 ((UINTN) GetPciExpressBaseAddress () + Address, > > OrData); > > > > +} > > > > + > > > > +/** > > > > + Performs a bitwise AND of an 8-bit PCI configuration register with a= n > 8-bit > > > > + value. > > > > + > > > > + Reads the 8-bit PCI configuration register specified by Address, > performs a > > > > + bitwise AND between the read result and the value specified by > AndData, > > and > > > > + writes the result to the 8-bit PCI configuration register specified = by > > > > + Address. The value written to the PCI configuration register is > returned. > > > > + This function must guarantee that all PCI read and write operations > are > > > > + serialized. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + > > > > + @param Address The address that encodes the PCI Bus, Device, Functi= on > > and > > > > + Register. > > > > + @param AndData The value to AND with the PCI configuration register= . > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT8 > > > > +EFIAPI > > > > +PciExpressAnd8 ( > > > > + IN UINTN Address, > > > > + IN UINT8 AndData > > > > + ) > > > > +{ > > > > + ASSERT_INVALID_PCI_ADDRESS (Address); > > > > + return MmioAnd8 ((UINTN) GetPciExpressBaseAddress () + Address, > > AndData); > > > > +} > > > > + > > > > +/** > > > > + Performs a bitwise AND of an 8-bit PCI configuration register with a= n > 8-bit > > > > + value, followed a bitwise OR with another 8-bit value. > > > > + > > > > + Reads the 8-bit PCI configuration register specified by Address, > performs a > > > > + bitwise AND between the read result and the value specified by > AndData, > > > > + performs a bitwise OR between the result of the AND operation and > > > > + the value specified by OrData, and writes the result to the 8-bit PC= I > > > > + configuration register specified by Address. The value written to th= e > PCI > > > > + configuration register is returned. This function must guarantee tha= t > all PCI > > > > + read and write operations are serialized. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + > > > > + @param Address The address that encodes the PCI Bus, Device, Functi= on > > and > > > > + Register. > > > > + @param AndData The value to AND with the PCI configuration register= . > > > > + @param OrData The value to OR with the result of the AND operation= . > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT8 > > > > +EFIAPI > > > > +PciExpressAndThenOr8 ( > > > > + IN UINTN Address, > > > > + IN UINT8 AndData, > > > > + IN UINT8 OrData > > > > + ) > > > > +{ > > > > + ASSERT_INVALID_PCI_ADDRESS (Address); > > > > + return MmioAndThenOr8 ( > > > > + (UINTN) GetPciExpressBaseAddress () + Address, > > > > + AndData, > > > > + OrData > > > > + ); > > > > +} > > > > + > > > > +/** > > > > + Reads a bit field of a PCI configuration register. > > > > + > > > > + Reads the bit field in an 8-bit PCI configuration register. The bit > field is > > > > + specified by the StartBit and the EndBit. The value of the bit field > is > > > > + returned. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If StartBit is greater than 7, then ASSERT(). > > > > + If EndBit is greater than 7, then ASSERT(). > > > > + If EndBit is less than StartBit, then ASSERT(). > > > > + > > > > + @param Address The PCI configuration register to read. > > > > + @param StartBit The ordinal of the least significant bit in the bi= t > field. > > > > + Range 0..7. > > > > + @param EndBit The ordinal of the most significant bit in the bit > field. > > > > + Range 0..7. > > > > + > > > > + @return The value of the bit field read from the PCI configuration > register. > > > > + > > > > +**/ > > > > +UINT8 > > > > +EFIAPI > > > > +PciExpressBitFieldRead8 ( > > > > + IN UINTN Address, > > > > + IN UINTN StartBit, > > > > + IN UINTN EndBit > > > > + ) > > > > +{ > > > > + ASSERT_INVALID_PCI_ADDRESS (Address); > > > > + return MmioBitFieldRead8 ( > > > > + (UINTN) GetPciExpressBaseAddress () + Address, > > > > + StartBit, > > > > + EndBit > > > > + ); > > > > +} > > > > + > > > > +/** > > > > + Writes a bit field to a PCI configuration register. > > > > + > > > > + Writes Value to the bit field of the PCI configuration register. The > bit > > > > + field is specified by the StartBit and the EndBit. All other bits in > the > > > > + destination PCI configuration register are preserved. The new value > of the > > > > + 8-bit register is returned. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If StartBit is greater than 7, then ASSERT(). > > > > + If EndBit is greater than 7, then ASSERT(). > > > > + If EndBit is less than StartBit, then ASSERT(). > > > > + If Value is larger than the bitmask value range specified by StartBi= t > and > > EndBit, then ASSERT(). > > > > + > > > > + @param Address The PCI configuration register to write. > > > > + @param StartBit The ordinal of the least significant bit in the bi= t > field. > > > > + Range 0..7. > > > > + @param EndBit The ordinal of the most significant bit in the bit > field. > > > > + Range 0..7. > > > > + @param Value The new value of the bit field. > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT8 > > > > +EFIAPI > > > > +PciExpressBitFieldWrite8 ( > > > > + IN UINTN Address, > > > > + IN UINTN StartBit, > > > > + IN UINTN EndBit, > > > > + IN UINT8 Value > > > > + ) > > > > +{ > > > > + ASSERT_INVALID_PCI_ADDRESS (Address); > > > > + return MmioBitFieldWrite8 ( > > > > + (UINTN) GetPciExpressBaseAddress () + Address, > > > > + StartBit, > > > > + EndBit, > > > > + Value > > > > + ); > > > > +} > > > > + > > > > +/** > > > > + Reads a bit field in an 8-bit PCI configuration, performs a bitwise > OR, and > > > > + writes the result back to the bit field in the 8-bit port. > > > > + > > > > + Reads the 8-bit PCI configuration register specified by Address, > performs a > > > > + bitwise OR between the read result and the value specified by > > > > + OrData, and writes the result to the 8-bit PCI configuration registe= r > > > > + specified by Address. The value written to the PCI configuration > register is > > > > + returned. This function must guarantee that all PCI read and write > > operations > > > > + are serialized. Extra left bits in OrData are stripped. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If StartBit is greater than 7, then ASSERT(). > > > > + If EndBit is greater than 7, then ASSERT(). > > > > + If EndBit is less than StartBit, then ASSERT(). > > > > + If OrData is larger than the bitmask value range specified by > StartBit and > > EndBit, then ASSERT(). > > > > + > > > > + @param Address The PCI configuration register to write. > > > > + @param StartBit The ordinal of the least significant bit in the bi= t > field. > > > > + Range 0..7. > > > > + @param EndBit The ordinal of the most significant bit in the bit > field. > > > > + Range 0..7. > > > > + @param OrData The value to OR with the PCI configuration registe= r. > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT8 > > > > +EFIAPI > > > > +PciExpressBitFieldOr8 ( > > > > + IN UINTN Address, > > > > + IN UINTN StartBit, > > > > + IN UINTN EndBit, > > > > + IN UINT8 OrData > > > > + ) > > > > +{ > > > > + ASSERT_INVALID_PCI_ADDRESS (Address); > > > > + return MmioBitFieldOr8 ( > > > > + (UINTN) GetPciExpressBaseAddress () + Address, > > > > + StartBit, > > > > + EndBit, > > > > + OrData > > > > + ); > > > > +} > > > > + > > > > +/** > > > > + Reads a bit field in an 8-bit PCI configuration register, performs a > bitwise > > > > + AND, and writes the result back to the bit field in the 8-bit > register. > > > > + > > > > + Reads the 8-bit PCI configuration register specified by Address, > performs a > > > > + bitwise AND between the read result and the value specified by > AndData, > > and > > > > + writes the result to the 8-bit PCI configuration register specified = by > > > > + Address. The value written to the PCI configuration register is > returned. > > > > + This function must guarantee that all PCI read and write operations > are > > > > + serialized. Extra left bits in AndData are stripped. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If StartBit is greater than 7, then ASSERT(). > > > > + If EndBit is greater than 7, then ASSERT(). > > > > + If EndBit is less than StartBit, then ASSERT(). > > > > + If AndData is larger than the bitmask value range specified by > StartBit and > > EndBit, then ASSERT(). > > > > + > > > > + @param Address The PCI configuration register to write. > > > > + @param StartBit The ordinal of the least significant bit in the bi= t > field. > > > > + Range 0..7. > > > > + @param EndBit The ordinal of the most significant bit in the bit > field. > > > > + Range 0..7. > > > > + @param AndData The value to AND with the PCI configuration > register. > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT8 > > > > +EFIAPI > > > > +PciExpressBitFieldAnd8 ( > > > > + IN UINTN Address, > > > > + IN UINTN StartBit, > > > > + IN UINTN EndBit, > > > > + IN UINT8 AndData > > > > + ) > > > > +{ > > > > + ASSERT_INVALID_PCI_ADDRESS (Address); > > > > + return MmioBitFieldAnd8 ( > > > > + (UINTN) GetPciExpressBaseAddress () + Address, > > > > + StartBit, > > > > + EndBit, > > > > + AndData > > > > + ); > > > > +} > > > > + > > > > +/** > > > > + Reads a bit field in an 8-bit port, performs a bitwise AND followed > by a > > > > + bitwise OR, and writes the result back to the bit field in the > > > > + 8-bit port. > > > > + > > > > + Reads the 8-bit PCI configuration register specified by Address, > performs a > > > > + bitwise AND followed by a bitwise OR between the read result and > > > > + the value specified by AndData, and writes the result to the 8-bit P= CI > > > > + configuration register specified by Address. The value written to th= e > PCI > > > > + configuration register is returned. This function must guarantee tha= t > all PCI > > > > + read and write operations are serialized. Extra left bits in both > AndData and > > > > + OrData are stripped. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If StartBit is greater than 7, then ASSERT(). > > > > + If EndBit is greater than 7, then ASSERT(). > > > > + If EndBit is less than StartBit, then ASSERT(). > > > > + If AndData is larger than the bitmask value range specified by > StartBit and > > EndBit, then ASSERT(). > > > > + If OrData is larger than the bitmask value range specified by > StartBit and > > EndBit, then ASSERT(). > > > > + > > > > + @param Address The PCI configuration register to write. > > > > + @param StartBit The ordinal of the least significant bit in the bi= t > field. > > > > + Range 0..7. > > > > + @param EndBit The ordinal of the most significant bit in the bit > field. > > > > + Range 0..7. > > > > + @param AndData The value to AND with the PCI configuration > register. > > > > + @param OrData The value to OR with the result of the AND > operation. > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT8 > > > > +EFIAPI > > > > +PciExpressBitFieldAndThenOr8 ( > > > > + IN UINTN Address, > > > > + IN UINTN StartBit, > > > > + IN UINTN EndBit, > > > > + IN UINT8 AndData, > > > > + IN UINT8 OrData > > > > + ) > > > > +{ > > > > + ASSERT_INVALID_PCI_ADDRESS (Address); > > > > + return MmioBitFieldAndThenOr8 ( > > > > + (UINTN) GetPciExpressBaseAddress () + Address, > > > > + StartBit, > > > > + EndBit, > > > > + AndData, > > > > + OrData > > > > + ); > > > > +} > > > > + > > > > +/** > > > > + Reads a 16-bit PCI configuration register. > > > > + > > > > + Reads and returns the 16-bit PCI configuration register specified by > > Address. > > > > + This function must guarantee that all PCI read and write operations > are > > > > + serialized. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > > > > + > > > > + @param Address The address that encodes the PCI Bus, Device, Functi= on > > and > > > > + Register. > > > > + > > > > + @return The read value from the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT16 > > > > +EFIAPI > > > > +PciExpressRead16 ( > > > > + IN UINTN Address > > > > + ) > > > > +{ > > > > + ASSERT_INVALID_PCI_ADDRESS (Address); > > > > + return MmioRead16 ((UINTN) GetPciExpressBaseAddress () + Address); > > > > +} > > > > + > > > > +/** > > > > + Writes a 16-bit PCI configuration register. > > > > + > > > > + Writes the 16-bit PCI configuration register specified by Address > with the > > > > + value specified by Value. Value is returned. This function must > guarantee > > > > + that all PCI read and write operations are serialized. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > > > > + > > > > + @param Address The address that encodes the PCI Bus, Device, Functi= on > > and > > > > + Register. > > > > + @param Value The value to write. > > > > + > > > > + @return The value written to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT16 > > > > +EFIAPI > > > > +PciExpressWrite16 ( > > > > + IN UINTN Address, > > > > + IN UINT16 Value > > > > + ) > > > > +{ > > > > + ASSERT_INVALID_PCI_ADDRESS (Address); > > > > + return MmioWrite16 ((UINTN) GetPciExpressBaseAddress () + Address, > > Value); > > > > +} > > > > + > > > > +/** > > > > + Performs a bitwise OR of a 16-bit PCI configuration register with > > > > + a 16-bit value. > > > > + > > > > + Reads the 16-bit PCI configuration register specified by Address, > performs > > a > > > > + bitwise OR between the read result and the value specified by > > > > + OrData, and writes the result to the 16-bit PCI configuration regist= er > > > > + specified by Address. The value written to the PCI configuration > register is > > > > + returned. This function must guarantee that all PCI read and write > > operations > > > > + are serialized. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > > > > + > > > > + @param Address The address that encodes the PCI Bus, Device, Functi= on > > and > > > > + Register. > > > > + @param OrData The value to OR with the PCI configuration register. > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT16 > > > > +EFIAPI > > > > +PciExpressOr16 ( > > > > + IN UINTN Address, > > > > + IN UINT16 OrData > > > > + ) > > > > +{ > > > > + ASSERT_INVALID_PCI_ADDRESS (Address); > > > > + return MmioOr16 ((UINTN) GetPciExpressBaseAddress () + Address, > > OrData); > > > > +} > > > > + > > > > +/** > > > > + Performs a bitwise AND of a 16-bit PCI configuration register with a > 16-bit > > > > + value. > > > > + > > > > + Reads the 16-bit PCI configuration register specified by Address, > performs > > a > > > > + bitwise AND between the read result and the value specified by > AndData, > > and > > > > + writes the result to the 16-bit PCI configuration register specified > by > > > > + Address. The value written to the PCI configuration register is > returned. > > > > + This function must guarantee that all PCI read and write operations > are > > > > + serialized. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > > > > + > > > > + @param Address The address that encodes the PCI Bus, Device, Functi= on > > and > > > > + Register. > > > > + @param AndData The value to AND with the PCI configuration register= . > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT16 > > > > +EFIAPI > > > > +PciExpressAnd16 ( > > > > + IN UINTN Address, > > > > + IN UINT16 AndData > > > > + ) > > > > +{ > > > > + ASSERT_INVALID_PCI_ADDRESS (Address); > > > > + return MmioAnd16 ((UINTN) GetPciExpressBaseAddress () + Address, > > AndData); > > > > +} > > > > + > > > > +/** > > > > + Performs a bitwise AND of a 16-bit PCI configuration register with a > 16-bit > > > > + value, followed a bitwise OR with another 16-bit value. > > > > + > > > > + Reads the 16-bit PCI configuration register specified by Address, > performs > > a > > > > + bitwise AND between the read result and the value specified by > AndData, > > > > + performs a bitwise OR between the result of the AND operation and > > > > + the value specified by OrData, and writes the result to the 16-bit P= CI > > > > + configuration register specified by Address. The value written to th= e > PCI > > > > + configuration register is returned. This function must guarantee tha= t > all PCI > > > > + read and write operations are serialized. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > > > > + > > > > + @param Address The address that encodes the PCI Bus, Device, Functi= on > > and > > > > + Register. > > > > + @param AndData The value to AND with the PCI configuration register= . > > > > + @param OrData The value to OR with the result of the AND operation= . > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT16 > > > > +EFIAPI > > > > +PciExpressAndThenOr16 ( > > > > + IN UINTN Address, > > > > + IN UINT16 AndData, > > > > + IN UINT16 OrData > > > > + ) > > > > +{ > > > > + ASSERT_INVALID_PCI_ADDRESS (Address); > > > > + return MmioAndThenOr16 ( > > > > + (UINTN) GetPciExpressBaseAddress () + Address, > > > > + AndData, > > > > + OrData > > > > + ); > > > > +} > > > > + > > > > +/** > > > > + Reads a bit field of a PCI configuration register. > > > > + > > > > + Reads the bit field in a 16-bit PCI configuration register. The bit > field is > > > > + specified by the StartBit and the EndBit. The value of the bit field > is > > > > + returned. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > > > > + If StartBit is greater than 15, then ASSERT(). > > > > + If EndBit is greater than 15, then ASSERT(). > > > > + If EndBit is less than StartBit, then ASSERT(). > > > > + > > > > + @param Address The PCI configuration register to read. > > > > + @param StartBit The ordinal of the least significant bit in the bi= t > field. > > > > + Range 0..15. > > > > + @param EndBit The ordinal of the most significant bit in the bit > field. > > > > + Range 0..15. > > > > + > > > > + @return The value of the bit field read from the PCI configuration > register. > > > > + > > > > +**/ > > > > +UINT16 > > > > +EFIAPI > > > > +PciExpressBitFieldRead16 ( > > > > + IN UINTN Address, > > > > + IN UINTN StartBit, > > > > + IN UINTN EndBit > > > > + ) > > > > +{ > > > > + ASSERT_INVALID_PCI_ADDRESS (Address); > > > > + return MmioBitFieldRead16 ( > > > > + (UINTN) GetPciExpressBaseAddress () + Address, > > > > + StartBit, > > > > + EndBit > > > > + ); > > > > +} > > > > + > > > > +/** > > > > + Writes a bit field to a PCI configuration register. > > > > + > > > > + Writes Value to the bit field of the PCI configuration register. The > bit > > > > + field is specified by the StartBit and the EndBit. All other bits in > the > > > > + destination PCI configuration register are preserved. The new value > of the > > > > + 16-bit register is returned. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > > > > + If StartBit is greater than 15, then ASSERT(). > > > > + If EndBit is greater than 15, then ASSERT(). > > > > + If EndBit is less than StartBit, then ASSERT(). > > > > + If Value is larger than the bitmask value range specified by StartBi= t > and > > EndBit, then ASSERT(). > > > > + > > > > + @param Address The PCI configuration register to write. > > > > + @param StartBit The ordinal of the least significant bit in the bi= t > field. > > > > + Range 0..15. > > > > + @param EndBit The ordinal of the most significant bit in the bit > field. > > > > + Range 0..15. > > > > + @param Value The new value of the bit field. > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT16 > > > > +EFIAPI > > > > +PciExpressBitFieldWrite16 ( > > > > + IN UINTN Address, > > > > + IN UINTN StartBit, > > > > + IN UINTN EndBit, > > > > + IN UINT16 Value > > > > + ) > > > > +{ > > > > + ASSERT_INVALID_PCI_ADDRESS (Address); > > > > + return MmioBitFieldWrite16 ( > > > > + (UINTN) GetPciExpressBaseAddress () + Address, > > > > + StartBit, > > > > + EndBit, > > > > + Value > > > > + ); > > > > +} > > > > + > > > > +/** > > > > + Reads a bit field in a 16-bit PCI configuration, performs a bitwise > OR, and > > > > + writes the result back to the bit field in the 16-bit port. > > > > + > > > > + Reads the 16-bit PCI configuration register specified by Address, > performs > > a > > > > + bitwise OR between the read result and the value specified by > > > > + OrData, and writes the result to the 16-bit PCI configuration regist= er > > > > + specified by Address. The value written to the PCI configuration > register is > > > > + returned. This function must guarantee that all PCI read and write > > operations > > > > + are serialized. Extra left bits in OrData are stripped. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > > > > + If StartBit is greater than 15, then ASSERT(). > > > > + If EndBit is greater than 15, then ASSERT(). > > > > + If EndBit is less than StartBit, then ASSERT(). > > > > + If OrData is larger than the bitmask value range specified by > StartBit and > > EndBit, then ASSERT(). > > > > + > > > > + @param Address The PCI configuration register to write. > > > > + @param StartBit The ordinal of the least significant bit in the bi= t > field. > > > > + Range 0..15. > > > > + @param EndBit The ordinal of the most significant bit in the bit > field. > > > > + Range 0..15. > > > > + @param OrData The value to OR with the PCI configuration registe= r. > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT16 > > > > +EFIAPI > > > > +PciExpressBitFieldOr16 ( > > > > + IN UINTN Address, > > > > + IN UINTN StartBit, > > > > + IN UINTN EndBit, > > > > + IN UINT16 OrData > > > > + ) > > > > +{ > > > > + ASSERT_INVALID_PCI_ADDRESS (Address); > > > > + return MmioBitFieldOr16 ( > > > > + (UINTN) GetPciExpressBaseAddress () + Address, > > > > + StartBit, > > > > + EndBit, > > > > + OrData > > > > + ); > > > > +} > > > > + > > > > +/** > > > > + Reads a bit field in a 16-bit PCI configuration register, performs a > bitwise > > > > + AND, and writes the result back to the bit field in the 16-bit > register. > > > > + > > > > + Reads the 16-bit PCI configuration register specified by Address, > performs > > a > > > > + bitwise AND between the read result and the value specified by > AndData, > > and > > > > + writes the result to the 16-bit PCI configuration register specified > by > > > > + Address. The value written to the PCI configuration register is > returned. > > > > + This function must guarantee that all PCI read and write operations > are > > > > + serialized. Extra left bits in AndData are stripped. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > > > > + If StartBit is greater than 15, then ASSERT(). > > > > + If EndBit is greater than 15, then ASSERT(). > > > > + If EndBit is less than StartBit, then ASSERT(). > > > > + If AndData is larger than the bitmask value range specified by > StartBit and > > EndBit, then ASSERT(). > > > > + > > > > + @param Address The PCI configuration register to write. > > > > + @param StartBit The ordinal of the least significant bit in the bi= t > field. > > > > + Range 0..15. > > > > + @param EndBit The ordinal of the most significant bit in the bit > field. > > > > + Range 0..15. > > > > + @param AndData The value to AND with the PCI configuration > register. > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT16 > > > > +EFIAPI > > > > +PciExpressBitFieldAnd16 ( > > > > + IN UINTN Address, > > > > + IN UINTN StartBit, > > > > + IN UINTN EndBit, > > > > + IN UINT16 AndData > > > > + ) > > > > +{ > > > > + ASSERT_INVALID_PCI_ADDRESS (Address); > > > > + return MmioBitFieldAnd16 ( > > > > + (UINTN) GetPciExpressBaseAddress () + Address, > > > > + StartBit, > > > > + EndBit, > > > > + AndData > > > > + ); > > > > +} > > > > + > > > > +/** > > > > + Reads a bit field in a 16-bit port, performs a bitwise AND followed > by a > > > > + bitwise OR, and writes the result back to the bit field in the > > > > + 16-bit port. > > > > + > > > > + Reads the 16-bit PCI configuration register specified by Address, > performs > > a > > > > + bitwise AND followed by a bitwise OR between the read result and > > > > + the value specified by AndData, and writes the result to the 16-bit > PCI > > > > + configuration register specified by Address. The value written to th= e > PCI > > > > + configuration register is returned. This function must guarantee tha= t > all PCI > > > > + read and write operations are serialized. Extra left bits in both > AndData and > > > > + OrData are stripped. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > > > > + If StartBit is greater than 15, then ASSERT(). > > > > + If EndBit is greater than 15, then ASSERT(). > > > > + If EndBit is less than StartBit, then ASSERT(). > > > > + If AndData is larger than the bitmask value range specified by > StartBit and > > EndBit, then ASSERT(). > > > > + If OrData is larger than the bitmask value range specified by > StartBit and > > EndBit, then ASSERT(). > > > > + > > > > + @param Address The PCI configuration register to write. > > > > + @param StartBit The ordinal of the least significant bit in the bi= t > field. > > > > + Range 0..15. > > > > + @param EndBit The ordinal of the most significant bit in the bit > field. > > > > + Range 0..15. > > > > + @param AndData The value to AND with the PCI configuration > register. > > > > + @param OrData The value to OR with the result of the AND > operation. > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT16 > > > > +EFIAPI > > > > +PciExpressBitFieldAndThenOr16 ( > > > > + IN UINTN Address, > > > > + IN UINTN StartBit, > > > > + IN UINTN EndBit, > > > > + IN UINT16 AndData, > > > > + IN UINT16 OrData > > > > + ) > > > > +{ > > > > + ASSERT_INVALID_PCI_ADDRESS (Address); > > > > + return MmioBitFieldAndThenOr16 ( > > > > + (UINTN) GetPciExpressBaseAddress () + Address, > > > > + StartBit, > > > > + EndBit, > > > > + AndData, > > > > + OrData > > > > + ); > > > > +} > > > > + > > > > +/** > > > > + Reads a 32-bit PCI configuration register. > > > > + > > > > + Reads and returns the 32-bit PCI configuration register specified by > > Address. > > > > + This function must guarantee that all PCI read and write operations > are > > > > + serialized. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > > > > + > > > > + @param Address The address that encodes the PCI Bus, Device, Functi= on > > and > > > > + Register. > > > > + > > > > + @return The read value from the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT32 > > > > +EFIAPI > > > > +PciExpressRead32 ( > > > > + IN UINTN Address > > > > + ) > > > > +{ > > > > + ASSERT_INVALID_PCI_ADDRESS (Address); > > > > + return MmioRead32 ((UINTN) GetPciExpressBaseAddress () + Address); > > > > +} > > > > + > > > > +/** > > > > + Writes a 32-bit PCI configuration register. > > > > + > > > > + Writes the 32-bit PCI configuration register specified by Address > with the > > > > + value specified by Value. Value is returned. This function must > guarantee > > > > + that all PCI read and write operations are serialized. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > > > > + > > > > + @param Address The address that encodes the PCI Bus, Device, Functi= on > > and > > > > + Register. > > > > + @param Value The value to write. > > > > + > > > > + @return The value written to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT32 > > > > +EFIAPI > > > > +PciExpressWrite32 ( > > > > + IN UINTN Address, > > > > + IN UINT32 Value > > > > + ) > > > > +{ > > > > + ASSERT_INVALID_PCI_ADDRESS (Address); > > > > + return MmioWrite32 ((UINTN) GetPciExpressBaseAddress () + Address, > > Value); > > > > +} > > > > + > > > > +/** > > > > + Performs a bitwise OR of a 32-bit PCI configuration register with > > > > + a 32-bit value. > > > > + > > > > + Reads the 32-bit PCI configuration register specified by Address, > performs > > a > > > > + bitwise OR between the read result and the value specified by > > > > + OrData, and writes the result to the 32-bit PCI configuration regist= er > > > > + specified by Address. The value written to the PCI configuration > register is > > > > + returned. This function must guarantee that all PCI read and write > > operations > > > > + are serialized. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > > > > + > > > > + @param Address The address that encodes the PCI Bus, Device, Functi= on > > and > > > > + Register. > > > > + @param OrData The value to OR with the PCI configuration register. > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT32 > > > > +EFIAPI > > > > +PciExpressOr32 ( > > > > + IN UINTN Address, > > > > + IN UINT32 OrData > > > > + ) > > > > +{ > > > > + ASSERT_INVALID_PCI_ADDRESS (Address); > > > > + return MmioOr32 ((UINTN) GetPciExpressBaseAddress () + Address, > > OrData); > > > > +} > > > > + > > > > +/** > > > > + Performs a bitwise AND of a 32-bit PCI configuration register with a > 32-bit > > > > + value. > > > > + > > > > + Reads the 32-bit PCI configuration register specified by Address, > performs > > a > > > > + bitwise AND between the read result and the value specified by > AndData, > > and > > > > + writes the result to the 32-bit PCI configuration register specified > by > > > > + Address. The value written to the PCI configuration register is > returned. > > > > + This function must guarantee that all PCI read and write operations > are > > > > + serialized. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > > > > + > > > > + @param Address The address that encodes the PCI Bus, Device, Functi= on > > and > > > > + Register. > > > > + @param AndData The value to AND with the PCI configuration register= . > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT32 > > > > +EFIAPI > > > > +PciExpressAnd32 ( > > > > + IN UINTN Address, > > > > + IN UINT32 AndData > > > > + ) > > > > +{ > > > > + ASSERT_INVALID_PCI_ADDRESS (Address); > > > > + return MmioAnd32 ((UINTN) GetPciExpressBaseAddress () + Address, > > AndData); > > > > +} > > > > + > > > > +/** > > > > + Performs a bitwise AND of a 32-bit PCI configuration register with a > 32-bit > > > > + value, followed a bitwise OR with another 32-bit value. > > > > + > > > > + Reads the 32-bit PCI configuration register specified by Address, > performs > > a > > > > + bitwise AND between the read result and the value specified by > AndData, > > > > + performs a bitwise OR between the result of the AND operation and > > > > + the value specified by OrData, and writes the result to the 32-bit P= CI > > > > + configuration register specified by Address. The value written to th= e > PCI > > > > + configuration register is returned. This function must guarantee tha= t > all PCI > > > > + read and write operations are serialized. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > > > > + > > > > + @param Address The address that encodes the PCI Bus, Device, Functi= on > > and > > > > + Register. > > > > + @param AndData The value to AND with the PCI configuration register= . > > > > + @param OrData The value to OR with the result of the AND operation= . > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT32 > > > > +EFIAPI > > > > +PciExpressAndThenOr32 ( > > > > + IN UINTN Address, > > > > + IN UINT32 AndData, > > > > + IN UINT32 OrData > > > > + ) > > > > +{ > > > > + ASSERT_INVALID_PCI_ADDRESS (Address); > > > > + return MmioAndThenOr32 ( > > > > + (UINTN) GetPciExpressBaseAddress () + Address, > > > > + AndData, > > > > + OrData > > > > + ); > > > > +} > > > > + > > > > +/** > > > > + Reads a bit field of a PCI configuration register. > > > > + > > > > + Reads the bit field in a 32-bit PCI configuration register. The bit > field is > > > > + specified by the StartBit and the EndBit. The value of the bit field > is > > > > + returned. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > > > > + If StartBit is greater than 31, then ASSERT(). > > > > + If EndBit is greater than 31, then ASSERT(). > > > > + If EndBit is less than StartBit, then ASSERT(). > > > > + > > > > + @param Address The PCI configuration register to read. > > > > + @param StartBit The ordinal of the least significant bit in the bi= t > field. > > > > + Range 0..31. > > > > + @param EndBit The ordinal of the most significant bit in the bit > field. > > > > + Range 0..31. > > > > + > > > > + @return The value of the bit field read from the PCI configuration > register. > > > > + > > > > +**/ > > > > +UINT32 > > > > +EFIAPI > > > > +PciExpressBitFieldRead32 ( > > > > + IN UINTN Address, > > > > + IN UINTN StartBit, > > > > + IN UINTN EndBit > > > > + ) > > > > +{ > > > > + ASSERT_INVALID_PCI_ADDRESS (Address); > > > > + return MmioBitFieldRead32 ( > > > > + (UINTN) GetPciExpressBaseAddress () + Address, > > > > + StartBit, > > > > + EndBit > > > > + ); > > > > +} > > > > + > > > > +/** > > > > + Writes a bit field to a PCI configuration register. > > > > + > > > > + Writes Value to the bit field of the PCI configuration register. The > bit > > > > + field is specified by the StartBit and the EndBit. All other bits in > the > > > > + destination PCI configuration register are preserved. The new value > of the > > > > + 32-bit register is returned. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > > > > + If StartBit is greater than 31, then ASSERT(). > > > > + If EndBit is greater than 31, then ASSERT(). > > > > + If EndBit is less than StartBit, then ASSERT(). > > > > + If Value is larger than the bitmask value range specified by StartBi= t > and > > EndBit, then ASSERT(). > > > > + > > > > + @param Address The PCI configuration register to write. > > > > + @param StartBit The ordinal of the least significant bit in the bi= t > field. > > > > + Range 0..31. > > > > + @param EndBit The ordinal of the most significant bit in the bit > field. > > > > + Range 0..31. > > > > + @param Value The new value of the bit field. > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT32 > > > > +EFIAPI > > > > +PciExpressBitFieldWrite32 ( > > > > + IN UINTN Address, > > > > + IN UINTN StartBit, > > > > + IN UINTN EndBit, > > > > + IN UINT32 Value > > > > + ) > > > > +{ > > > > + ASSERT_INVALID_PCI_ADDRESS (Address); > > > > + return MmioBitFieldWrite32 ( > > > > + (UINTN) GetPciExpressBaseAddress () + Address, > > > > + StartBit, > > > > + EndBit, > > > > + Value > > > > + ); > > > > +} > > > > + > > > > +/** > > > > + Reads a bit field in a 32-bit PCI configuration, performs a bitwise > OR, and > > > > + writes the result back to the bit field in the 32-bit port. > > > > + > > > > + Reads the 32-bit PCI configuration register specified by Address, > performs > > a > > > > + bitwise OR between the read result and the value specified by > > > > + OrData, and writes the result to the 32-bit PCI configuration regist= er > > > > + specified by Address. The value written to the PCI configuration > register is > > > > + returned. This function must guarantee that all PCI read and write > > operations > > > > + are serialized. Extra left bits in OrData are stripped. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > > > > + If StartBit is greater than 31, then ASSERT(). > > > > + If EndBit is greater than 31, then ASSERT(). > > > > + If EndBit is less than StartBit, then ASSERT(). > > > > + If OrData is larger than the bitmask value range specified by > StartBit and > > EndBit, then ASSERT(). > > > > + > > > > + @param Address The PCI configuration register to write. > > > > + @param StartBit The ordinal of the least significant bit in the bi= t > field. > > > > + Range 0..31. > > > > + @param EndBit The ordinal of the most significant bit in the bit > field. > > > > + Range 0..31. > > > > + @param OrData The value to OR with the PCI configuration registe= r. > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT32 > > > > +EFIAPI > > > > +PciExpressBitFieldOr32 ( > > > > + IN UINTN Address, > > > > + IN UINTN StartBit, > > > > + IN UINTN EndBit, > > > > + IN UINT32 OrData > > > > + ) > > > > +{ > > > > + ASSERT_INVALID_PCI_ADDRESS (Address); > > > > + return MmioBitFieldOr32 ( > > > > + (UINTN) GetPciExpressBaseAddress () + Address, > > > > + StartBit, > > > > + EndBit, > > > > + OrData > > > > + ); > > > > +} > > > > + > > > > +/** > > > > + Reads a bit field in a 32-bit PCI configuration register, performs a > bitwise > > > > + AND, and writes the result back to the bit field in the 32-bit > register. > > > > + > > > > + Reads the 32-bit PCI configuration register specified by Address, > performs > > a > > > > + bitwise AND between the read result and the value specified by > AndData, > > and > > > > + writes the result to the 32-bit PCI configuration register specified > by > > > > + Address. The value written to the PCI configuration register is > returned. > > > > + This function must guarantee that all PCI read and write operations > are > > > > + serialized. Extra left bits in AndData are stripped. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > > > > + If StartBit is greater than 31, then ASSERT(). > > > > + If EndBit is greater than 31, then ASSERT(). > > > > + If EndBit is less than StartBit, then ASSERT(). > > > > + If AndData is larger than the bitmask value range specified by > StartBit and > > EndBit, then ASSERT(). > > > > + > > > > + @param Address The PCI configuration register to write. > > > > + @param StartBit The ordinal of the least significant bit in the bi= t > field. > > > > + Range 0..31. > > > > + @param EndBit The ordinal of the most significant bit in the bit > field. > > > > + Range 0..31. > > > > + @param AndData The value to AND with the PCI configuration > register. > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT32 > > > > +EFIAPI > > > > +PciExpressBitFieldAnd32 ( > > > > + IN UINTN Address, > > > > + IN UINTN StartBit, > > > > + IN UINTN EndBit, > > > > + IN UINT32 AndData > > > > + ) > > > > +{ > > > > + ASSERT_INVALID_PCI_ADDRESS (Address); > > > > + return MmioBitFieldAnd32 ( > > > > + (UINTN) GetPciExpressBaseAddress () + Address, > > > > + StartBit, > > > > + EndBit, > > > > + AndData > > > > + ); > > > > +} > > > > + > > > > +/** > > > > + Reads a bit field in a 32-bit port, performs a bitwise AND followed > by a > > > > + bitwise OR, and writes the result back to the bit field in the > > > > + 32-bit port. > > > > + > > > > + Reads the 32-bit PCI configuration register specified by Address, > performs > > a > > > > + bitwise AND followed by a bitwise OR between the read result and > > > > + the value specified by AndData, and writes the result to the 32-bit > PCI > > > > + configuration register specified by Address. The value written to th= e > PCI > > > > + configuration register is returned. This function must guarantee tha= t > all PCI > > > > + read and write operations are serialized. Extra left bits in both > AndData and > > > > + OrData are stripped. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > > > > + If StartBit is greater than 31, then ASSERT(). > > > > + If EndBit is greater than 31, then ASSERT(). > > > > + If EndBit is less than StartBit, then ASSERT(). > > > > + If AndData is larger than the bitmask value range specified by > StartBit and > > EndBit, then ASSERT(). > > > > + If OrData is larger than the bitmask value range specified by > StartBit and > > EndBit, then ASSERT(). > > > > + > > > > + @param Address The PCI configuration register to write. > > > > + @param StartBit The ordinal of the least significant bit in the bi= t > field. > > > > + Range 0..31. > > > > + @param EndBit The ordinal of the most significant bit in the bit > field. > > > > + Range 0..31. > > > > + @param AndData The value to AND with the PCI configuration > register. > > > > + @param OrData The value to OR with the result of the AND > operation. > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT32 > > > > +EFIAPI > > > > +PciExpressBitFieldAndThenOr32 ( > > > > + IN UINTN Address, > > > > + IN UINTN StartBit, > > > > + IN UINTN EndBit, > > > > + IN UINT32 AndData, > > > > + IN UINT32 OrData > > > > + ) > > > > +{ > > > > + ASSERT_INVALID_PCI_ADDRESS (Address); > > > > + return MmioBitFieldAndThenOr32 ( > > > > + (UINTN) GetPciExpressBaseAddress () + Address, > > > > + StartBit, > > > > + EndBit, > > > > + AndData, > > > > + OrData > > > > + ); > > > > +} > > > > + > > > > +/** > > > > + Reads a range of PCI configuration registers into a caller supplied > buffer. > > > > + > > > > + Reads the range of PCI configuration registers specified by > StartAddress > > and > > > > + Size into the buffer specified by Buffer. This function only allows > the PCI > > > > + configuration registers from a single PCI function to be read. Size = is > > > > + returned. When possible 32-bit PCI configuration read cycles are use= d > to > > read > > > > + from StartAdress to StartAddress + Size. Due to alignment > restrictions, 8- > > bit > > > > + and 16-bit PCI configuration read cycles may be used at the beginnin= g > and > > the > > > > + end of the range. > > > > + > > > > + If StartAddress > 0x0FFFFFFF, then ASSERT(). > > > > + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). > > > > + If Size > 0 and Buffer is NULL, then ASSERT(). > > > > + > > > > + @param StartAddress The starting address that encodes the PCI Bus, > > Device, > > > > + Function and Register. > > > > + @param Size The size in bytes of the transfer. > > > > + @param Buffer The pointer to a buffer receiving the data rea= d. > > > > + > > > > + @return Size read data from StartAddress. > > > > + > > > > +**/ > > > > +UINTN > > > > +EFIAPI > > > > +PciExpressReadBuffer ( > > > > + IN UINTN StartAddress, > > > > + IN UINTN Size, > > > > + OUT VOID *Buffer > > > > + ) > > > > +{ > > > > + UINTN ReturnValue; > > > > + > > > > + ASSERT_INVALID_PCI_ADDRESS (StartAddress); > > > > + ASSERT (((StartAddress & 0xFFF) + Size) <=3D 0x1000); > > > > + > > > > + if (Size =3D=3D 0) { > > > > + return Size; > > > > + } > > > > + > > > > + ASSERT (Buffer !=3D NULL); > > > > + > > > > + // > > > > + // Save Size for return > > > > + // > > > > + ReturnValue =3D Size; > > > > + > > > > + if ((StartAddress & 1) !=3D 0) { > > > > + // > > > > + // Read a byte if StartAddress is byte aligned > > > > + // > > > > + *(volatile UINT8 *)Buffer =3D PciExpressRead8 (StartAddress); > > > > + StartAddress +=3D sizeof (UINT8); > > > > + Size -=3D sizeof (UINT8); > > > > + Buffer =3D (UINT8*)Buffer + 1; > > > > + } > > > > + > > > > + if (Size >=3D sizeof (UINT16) && (StartAddress & 2) !=3D 0) { > > > > + // > > > > + // Read a word if StartAddress is word aligned > > > > + // > > > > + WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 > > (StartAddress)); > > > > + > > > > + StartAddress +=3D sizeof (UINT16); > > > > + Size -=3D sizeof (UINT16); > > > > + Buffer =3D (UINT16*)Buffer + 1; > > > > + } > > > > + > > > > + while (Size >=3D sizeof (UINT32)) { > > > > + // > > > > + // Read as many double words as possible > > > > + // > > > > + WriteUnaligned32 ((UINT32 *) Buffer, (UINT32) PciExpressRead32 > > (StartAddress)); > > > > + > > > > + StartAddress +=3D sizeof (UINT32); > > > > + Size -=3D sizeof (UINT32); > > > > + Buffer =3D (UINT32*)Buffer + 1; > > > > + } > > > > + > > > > + if (Size >=3D sizeof (UINT16)) { > > > > + // > > > > + // Read the last remaining word if exist > > > > + // > > > > + WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 > > (StartAddress)); > > > > + StartAddress +=3D sizeof (UINT16); > > > > + Size -=3D sizeof (UINT16); > > > > + Buffer =3D (UINT16*)Buffer + 1; > > > > + } > > > > + > > > > + if (Size >=3D sizeof (UINT8)) { > > > > + // > > > > + // Read the last remaining byte if exist > > > > + // > > > > + *(volatile UINT8 *)Buffer =3D PciExpressRead8 (StartAddress); > > > > + } > > > > + > > > > + return ReturnValue; > > > > +} > > > > + > > > > +/** > > > > + Copies the data in a caller supplied buffer to a specified range of > PCI > > > > + configuration space. > > > > + > > > > + Writes the range of PCI configuration registers specified by > StartAddress > > and > > > > + Size from the buffer specified by Buffer. This function only allows > the PCI > > > > + configuration registers from a single PCI function to be written. > Size is > > > > + returned. When possible 32-bit PCI configuration write cycles are > used to > > > > + write from StartAdress to StartAddress + Size. Due to alignment > > restrictions, > > > > + 8-bit and 16-bit PCI configuration write cycles may be used at the > beginning > > > > + and the end of the range. > > > > + > > > > + If StartAddress > 0x0FFFFFFF, then ASSERT(). > > > > + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). > > > > + If Size > 0 and Buffer is NULL, then ASSERT(). > > > > + > > > > + @param StartAddress The starting address that encodes the PCI Bus, > > Device, > > > > + Function and Register. > > > > + @param Size The size in bytes of the transfer. > > > > + @param Buffer The pointer to a buffer containing the data to > write. > > > > + > > > > + @return Size written to StartAddress. > > > > + > > > > +**/ > > > > +UINTN > > > > +EFIAPI > > > > +PciExpressWriteBuffer ( > > > > + IN UINTN StartAddress, > > > > + IN UINTN Size, > > > > + IN VOID *Buffer > > > > + ) > > > > +{ > > > > + UINTN ReturnValue; > > > > + > > > > + ASSERT_INVALID_PCI_ADDRESS (StartAddress); > > > > + ASSERT (((StartAddress & 0xFFF) + Size) <=3D 0x1000); > > > > + > > > > + if (Size =3D=3D 0) { > > > > + return 0; > > > > + } > > > > + > > > > + ASSERT (Buffer !=3D NULL); > > > > + > > > > + // > > > > + // Save Size for return > > > > + // > > > > + ReturnValue =3D Size; > > > > + > > > > + if ((StartAddress & 1) !=3D 0) { > > > > + // > > > > + // Write a byte if StartAddress is byte aligned > > > > + // > > > > + PciExpressWrite8 (StartAddress, *(UINT8*)Buffer); > > > > + StartAddress +=3D sizeof (UINT8); > > > > + Size -=3D sizeof (UINT8); > > > > + Buffer =3D (UINT8*)Buffer + 1; > > > > + } > > > > + > > > > + if (Size >=3D sizeof (UINT16) && (StartAddress & 2) !=3D 0) { > > > > + // > > > > + // Write a word if StartAddress is word aligned > > > > + // > > > > + PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer)= ); > > > > + StartAddress +=3D sizeof (UINT16); > > > > + Size -=3D sizeof (UINT16); > > > > + Buffer =3D (UINT16*)Buffer + 1; > > > > + } > > > > + > > > > + while (Size >=3D sizeof (UINT32)) { > > > > + // > > > > + // Write as many double words as possible > > > > + // > > > > + PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32*)Buffer)= ); > > > > + StartAddress +=3D sizeof (UINT32); > > > > + Size -=3D sizeof (UINT32); > > > > + Buffer =3D (UINT32*)Buffer + 1; > > > > + } > > > > + > > > > + if (Size >=3D sizeof (UINT16)) { > > > > + // > > > > + // Write the last remaining word if exist > > > > + // > > > > + PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer)= ); > > > > + StartAddress +=3D sizeof (UINT16); > > > > + Size -=3D sizeof (UINT16); > > > > + Buffer =3D (UINT16*)Buffer + 1; > > > > + } > > > > + > > > > + if (Size >=3D sizeof (UINT8)) { > > > > + // > > > > + // Write the last remaining byte if exist > > > > + // > > > > + PciExpressWrite8 (StartAddress, *(UINT8*)Buffer); > > > > + } > > > > + > > > > + return ReturnValue; > > > > +} > > > > diff --git a/UefiPayloadPkg/Library/BasePciLibPciExpress/PciLib.c > > b/UefiPayloadPkg/Library/BasePciLibPciExpress/PciLib.c > > new file mode 100644 > > index 000000000000..fba5914462c8 > > --- /dev/null > > +++ b/UefiPayloadPkg/Library/BasePciLibPciExpress/PciLib.c > > @@ -0,0 +1,1302 @@ > > +/** @file > > > > + PCI Library functions that use the 256 MB PCI Express MMIO window to > > perform PCI > > > > + Configuration cycles. Layers on PCI Express Library. > > > > + > > > > + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved. > > > > + SPDX-License-Identifier: BSD-2-Clause-Patent > > > > + > > > > +**/ > > > > + > > > > + > > > > +#include > > > > + > > > > +#include > > > > +#include > > > > +#include > > > > + > > > > +#include > > > > +#include > > > > +#include > > > > +#include > > > > + > > > > +#include > > > > +#include > > > > + > > > > +STATIC BOOLEAN mMMCONFEnabled; > > > > + > > > > +/** > > > > + Registers a PCI device so PCI configuration registers may be accesse= d > after > > > > + SetVirtualAddressMap(). > > > > + > > > > + Registers the PCI device specified by Address so all the PCI > configuration > > registers > > > > + associated with that PCI device may be accessed after > > SetVirtualAddressMap() is called. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + > > > > + @param Address The address that encodes the PCI Bus, Device, Functi= on > > and > > > > + Register. > > > > + > > > > + @retval RETURN_SUCCESS The PCI device was registered for > runtime > > access. > > > > + @retval RETURN_UNSUPPORTED An attempt was made to call this > > function > > > > + after ExitBootServices(). > > > > + @retval RETURN_UNSUPPORTED The resources required to access th= e > > PCI device > > > > + at runtime could not be mapped. > > > > + @retval RETURN_OUT_OF_RESOURCES There are not enough resources > > available to > > > > + complete the registration. > > > > + > > > > +**/ > > > > +RETURN_STATUS > > > > +EFIAPI > > > > +PciRegisterForRuntimeAccess ( > > > > + IN UINTN Address > > > > + ) > > > > +{ > > > > + return PciExpressRegisterForRuntimeAccess (Address); > > > > +} > > > > + > > > > +/** > > > > + Performs platform specific initialization required for the CPU to > access > > > > + the MMCONF space. This function does not initialize the MMCONF > itself. > > > > + > > > > + @retval RETURN_SUCCESS The platform specific initialization > succeeded. > > > > + @retval RETURN_DEVICE_ERROR The platform specific initialization > could > > not be completed. > > > > + > > > > +**/ > > > > +RETURN_STATUS > > > > +EFIAPI > > > > +PciLibInitialize ( > > > > + VOID > > > > + ) > > > > +{ > > > > + EFI_HOB_GUID_TYPE *GuidHob; > > > > + ACPI_BOARD_INFO *AcpiBoardInfoPtr; > > > > + > > > > + // > > > > + // Find the acpi board information guid hob > > > > + // > > > > + GuidHob =3D GetFirstGuidHob (&gUefiAcpiBoardInfoGuid); > > > > + if (GuidHob =3D=3D NULL) { > > > > + return EFI_SUCCESS; > > > > + } > > > > + AcpiBoardInfoPtr =3D (ACPI_BOARD_INFO *)GET_GUID_HOB_DATA > > (GuidHob); > > > > + > > > > + mMMCONFEnabled =3D AcpiBoardInfoPtr->PcieBaseAddress !=3D 0 && > > > > + AcpiBoardInfoPtr->PcieBaseSize !=3D 0; > > > > + return EFI_SUCCESS; > > > > +} > > > > + > > > > +/** > > > > + Reads an 8-bit PCI configuration register. > > > > + > > > > + Reads and returns the 8-bit PCI configuration register specified by > Address. > > > > + This function must guarantee that all PCI read and write operations > are > > > > + serialized. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + > > > > + @param Address The address that encodes the PCI Bus, Device, Functi= on > > and > > > > + Register. > > > > + > > > > + @return The read value from the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT8 > > > > +EFIAPI > > > > +PciRead8 ( > > > > + IN UINTN Address > > > > + ) > > > > +{ > > > > + if (mMMCONFEnabled) { > > > > + return PciExpressRead8 (Address); > > > > + } else { > > > > + return PciCf8Read8 (Address); > > > > + } > > > > +} > > > > + > > > > +/** > > > > + Writes an 8-bit PCI configuration register. > > > > + > > > > + Writes the 8-bit PCI configuration register specified by Address wit= h > the > > > > + value specified by Value. Value is returned. This function must > guarantee > > > > + that all PCI read and write operations are serialized. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + > > > > + @param Address The address that encodes the PCI Bus, Device, Functi= on > > and > > > > + Register. > > > > + @param Value The value to write. > > > > + > > > > + @return The value written to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT8 > > > > +EFIAPI > > > > +PciWrite8 ( > > > > + IN UINTN Address, > > > > + IN UINT8 Value > > > > + ) > > > > +{ > > > > + if (mMMCONFEnabled) { > > > > + return PciExpressWrite8 (Address, Value); > > > > + } else { > > > > + return PciCf8Write8 (Address, Value); > > > > + } > > > > +} > > > > + > > > > +/** > > > > + Performs a bitwise OR of an 8-bit PCI configuration register with > > > > + an 8-bit value. > > > > + > > > > + Reads the 8-bit PCI configuration register specified by Address, > performs a > > > > + bitwise OR between the read result and the value specified by > > > > + OrData, and writes the result to the 8-bit PCI configuration registe= r > > > > + specified by Address. The value written to the PCI configuration > register is > > > > + returned. This function must guarantee that all PCI read and write > > operations > > > > + are serialized. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + > > > > + @param Address The address that encodes the PCI Bus, Device, Functi= on > > and > > > > + Register. > > > > + @param OrData The value to OR with the PCI configuration register. > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT8 > > > > +EFIAPI > > > > +PciOr8 ( > > > > + IN UINTN Address, > > > > + IN UINT8 OrData > > > > + ) > > > > +{ > > > > + if (mMMCONFEnabled) { > > > > + return PciExpressOr8 (Address, OrData); > > > > + } else { > > > > + return PciCf8Or8 (Address, OrData); > > > > + } > > > > +} > > > > + > > > > +/** > > > > + Performs a bitwise AND of an 8-bit PCI configuration register with a= n > 8-bit > > > > + value. > > > > + > > > > + Reads the 8-bit PCI configuration register specified by Address, > performs a > > > > + bitwise AND between the read result and the value specified by > AndData, > > and > > > > + writes the result to the 8-bit PCI configuration register specified = by > > > > + Address. The value written to the PCI configuration register is > returned. > > > > + This function must guarantee that all PCI read and write operations > are > > > > + serialized. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + > > > > + @param Address The address that encodes the PCI Bus, Device, Functi= on > > and > > > > + Register. > > > > + @param AndData The value to AND with the PCI configuration register= . > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT8 > > > > +EFIAPI > > > > +PciAnd8 ( > > > > + IN UINTN Address, > > > > + IN UINT8 AndData > > > > + ) > > > > +{ > > > > + if (mMMCONFEnabled) { > > > > + return PciExpressAnd8 (Address, AndData); > > > > + } else { > > > > + return PciCf8And8 (Address, AndData); > > > > + } > > > > +} > > > > + > > > > +/** > > > > + Performs a bitwise AND of an 8-bit PCI configuration register with a= n > 8-bit > > > > + value, followed a bitwise OR with another 8-bit value. > > > > + > > > > + Reads the 8-bit PCI configuration register specified by Address, > performs a > > > > + bitwise AND between the read result and the value specified by > AndData, > > > > + performs a bitwise OR between the result of the AND operation and > > > > + the value specified by OrData, and writes the result to the 8-bit PC= I > > > > + configuration register specified by Address. The value written to th= e > PCI > > > > + configuration register is returned. This function must guarantee tha= t > all PCI > > > > + read and write operations are serialized. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + > > > > + @param Address The address that encodes the PCI Bus, Device, Functi= on > > and > > > > + Register. > > > > + @param AndData The value to AND with the PCI configuration register= . > > > > + @param OrData The value to OR with the result of the AND operation= . > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT8 > > > > +EFIAPI > > > > +PciAndThenOr8 ( > > > > + IN UINTN Address, > > > > + IN UINT8 AndData, > > > > + IN UINT8 OrData > > > > + ) > > > > +{ > > > > + if (mMMCONFEnabled) { > > > > + return PciExpressAndThenOr8 (Address, AndData, OrData); > > > > + } else { > > > > + return PciCf8AndThenOr8 (Address, AndData, OrData); > > > > + } > > > > +} > > > > + > > > > +/** > > > > + Reads a bit field of a PCI configuration register. > > > > + > > > > + Reads the bit field in an 8-bit PCI configuration register. The bit > field is > > > > + specified by the StartBit and the EndBit. The value of the bit field > is > > > > + returned. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If StartBit is greater than 7, then ASSERT(). > > > > + If EndBit is greater than 7, then ASSERT(). > > > > + If EndBit is less than StartBit, then ASSERT(). > > > > + > > > > + @param Address The PCI configuration register to read. > > > > + @param StartBit The ordinal of the least significant bit in the bi= t > field. > > > > + Range 0..7. > > > > + @param EndBit The ordinal of the most significant bit in the bit > field. > > > > + Range 0..7. > > > > + > > > > + @return The value of the bit field read from the PCI configuration > register. > > > > + > > > > +**/ > > > > +UINT8 > > > > +EFIAPI > > > > +PciBitFieldRead8 ( > > > > + IN UINTN Address, > > > > + IN UINTN StartBit, > > > > + IN UINTN EndBit > > > > + ) > > > > +{ > > > > + if (mMMCONFEnabled) { > > > > + return PciExpressBitFieldRead8 (Address, StartBit, EndBit); > > > > + } else { > > > > + return PciCf8BitFieldRead8 (Address, StartBit, EndBit); > > > > + } > > > > +} > > > > + > > > > +/** > > > > + Writes a bit field to a PCI configuration register. > > > > + > > > > + Writes Value to the bit field of the PCI configuration register. The > bit > > > > + field is specified by the StartBit and the EndBit. All other bits in > the > > > > + destination PCI configuration register are preserved. The new value > of the > > > > + 8-bit register is returned. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If StartBit is greater than 7, then ASSERT(). > > > > + If EndBit is greater than 7, then ASSERT(). > > > > + If EndBit is less than StartBit, then ASSERT(). > > > > + If Value is larger than the bitmask value range specified by StartBi= t > and > > EndBit, then ASSERT(). > > > > + > > > > + @param Address The PCI configuration register to write. > > > > + @param StartBit The ordinal of the least significant bit in the bi= t > field. > > > > + Range 0..7. > > > > + @param EndBit The ordinal of the most significant bit in the bit > field. > > > > + Range 0..7. > > > > + @param Value The new value of the bit field. > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT8 > > > > +EFIAPI > > > > +PciBitFieldWrite8 ( > > > > + IN UINTN Address, > > > > + IN UINTN StartBit, > > > > + IN UINTN EndBit, > > > > + IN UINT8 Value > > > > + ) > > > > +{ > > > > + if (mMMCONFEnabled) { > > > > + return PciExpressBitFieldWrite8 (Address, StartBit, EndBit, Value)= ; > > > > + } else { > > > > + return PciCf8BitFieldWrite8 (Address, StartBit, EndBit, Value); > > > > + } > > > > +} > > > > + > > > > +/** > > > > + Reads a bit field in an 8-bit PCI configuration, performs a bitwise > OR, and > > > > + writes the result back to the bit field in the 8-bit port. > > > > + > > > > + Reads the 8-bit PCI configuration register specified by Address, > performs a > > > > + bitwise OR between the read result and the value specified by > > > > + OrData, and writes the result to the 8-bit PCI configuration registe= r > > > > + specified by Address. The value written to the PCI configuration > register is > > > > + returned. This function must guarantee that all PCI read and write > > operations > > > > + are serialized. Extra left bits in OrData are stripped. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If StartBit is greater than 7, then ASSERT(). > > > > + If EndBit is greater than 7, then ASSERT(). > > > > + If EndBit is less than StartBit, then ASSERT(). > > > > + If OrData is larger than the bitmask value range specified by > StartBit and > > EndBit, then ASSERT(). > > > > + > > > > + @param Address The PCI configuration register to write. > > > > + @param StartBit The ordinal of the least significant bit in the bi= t > field. > > > > + Range 0..7. > > > > + @param EndBit The ordinal of the most significant bit in the bit > field. > > > > + Range 0..7. > > > > + @param OrData The value to OR with the PCI configuration registe= r. > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT8 > > > > +EFIAPI > > > > +PciBitFieldOr8 ( > > > > + IN UINTN Address, > > > > + IN UINTN StartBit, > > > > + IN UINTN EndBit, > > > > + IN UINT8 OrData > > > > + ) > > > > +{ > > > > + if (mMMCONFEnabled) { > > > > + return PciExpressBitFieldOr8 (Address, StartBit, EndBit, OrData); > > > > + } else { > > > > + return PciCf8BitFieldOr8 (Address, StartBit, EndBit, OrData); > > > > + } > > > > +} > > > > + > > > > +/** > > > > + Reads a bit field in an 8-bit PCI configuration register, performs a > bitwise > > > > + AND, and writes the result back to the bit field in the 8-bit > register. > > > > + > > > > + Reads the 8-bit PCI configuration register specified by Address, > performs a > > > > + bitwise AND between the read result and the value specified by > AndData, > > and > > > > + writes the result to the 8-bit PCI configuration register specified = by > > > > + Address. The value written to the PCI configuration register is > returned. > > > > + This function must guarantee that all PCI read and write operations > are > > > > + serialized. Extra left bits in AndData are stripped. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If StartBit is greater than 7, then ASSERT(). > > > > + If EndBit is greater than 7, then ASSERT(). > > > > + If EndBit is less than StartBit, then ASSERT(). > > > > + If AndData is larger than the bitmask value range specified by > StartBit and > > EndBit, then ASSERT(). > > > > + > > > > + @param Address The PCI configuration register to write. > > > > + @param StartBit The ordinal of the least significant bit in the bi= t > field. > > > > + Range 0..7. > > > > + @param EndBit The ordinal of the most significant bit in the bit > field. > > > > + Range 0..7. > > > > + @param AndData The value to AND with the PCI configuration > register. > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT8 > > > > +EFIAPI > > > > +PciBitFieldAnd8 ( > > > > + IN UINTN Address, > > > > + IN UINTN StartBit, > > > > + IN UINTN EndBit, > > > > + IN UINT8 AndData > > > > + ) > > > > +{ > > > > + if (mMMCONFEnabled) { > > > > + return PciExpressBitFieldAnd8 (Address, StartBit, EndBit, AndData)= ; > > > > + } else { > > > > + return PciCf8BitFieldAnd8 (Address, StartBit, EndBit, AndData); > > > > + } > > > > +} > > > > + > > > > +/** > > > > + Reads a bit field in an 8-bit port, performs a bitwise AND followed > by a > > > > + bitwise OR, and writes the result back to the bit field in the > > > > + 8-bit port. > > > > + > > > > + Reads the 8-bit PCI configuration register specified by Address, > performs a > > > > + bitwise AND followed by a bitwise OR between the read result and > > > > + the value specified by AndData, and writes the result to the 8-bit P= CI > > > > + configuration register specified by Address. The value written to th= e > PCI > > > > + configuration register is returned. This function must guarantee tha= t > all PCI > > > > + read and write operations are serialized. Extra left bits in both > AndData and > > > > + OrData are stripped. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If StartBit is greater than 7, then ASSERT(). > > > > + If EndBit is greater than 7, then ASSERT(). > > > > + If EndBit is less than StartBit, then ASSERT(). > > > > + If AndData is larger than the bitmask value range specified by > StartBit and > > EndBit, then ASSERT(). > > > > + If OrData is larger than the bitmask value range specified by > StartBit and > > EndBit, then ASSERT(). > > > > + > > > > + @param Address The PCI configuration register to write. > > > > + @param StartBit The ordinal of the least significant bit in the bi= t > field. > > > > + Range 0..7. > > > > + @param EndBit The ordinal of the most significant bit in the bit > field. > > > > + Range 0..7. > > > > + @param AndData The value to AND with the PCI configuration > register. > > > > + @param OrData The value to OR with the result of the AND > operation. > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT8 > > > > +EFIAPI > > > > +PciBitFieldAndThenOr8 ( > > > > + IN UINTN Address, > > > > + IN UINTN StartBit, > > > > + IN UINTN EndBit, > > > > + IN UINT8 AndData, > > > > + IN UINT8 OrData > > > > + ) > > > > +{ > > > > + if (mMMCONFEnabled) { > > > > + return PciExpressBitFieldAndThenOr8 (Address, StartBit, EndBit, > AndData, > > OrData); > > > > + } else { > > > > + return PciCf8BitFieldAndThenOr8 (Address, StartBit, EndBit, AndDat= a, > > OrData); > > > > + } > > > > +} > > > > + > > > > +/** > > > > + Reads a 16-bit PCI configuration register. > > > > + > > > > + Reads and returns the 16-bit PCI configuration register specified by > > Address. > > > > + This function must guarantee that all PCI read and write operations > are > > > > + serialized. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > > > > + > > > > + @param Address The address that encodes the PCI Bus, Device, Functi= on > > and > > > > + Register. > > > > + > > > > + @return The read value from the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT16 > > > > +EFIAPI > > > > +PciRead16 ( > > > > + IN UINTN Address > > > > + ) > > > > +{ > > > > + if (mMMCONFEnabled) { > > > > + return PciExpressRead16 (Address); > > > > + } else { > > > > + return PciCf8Read16 (Address); > > > > + } > > > > +} > > > > + > > > > +/** > > > > + Writes a 16-bit PCI configuration register. > > > > + > > > > + Writes the 16-bit PCI configuration register specified by Address > with the > > > > + value specified by Value. Value is returned. This function must > guarantee > > > > + that all PCI read and write operations are serialized. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > > > > + > > > > + @param Address The address that encodes the PCI Bus, Device, Functi= on > > and > > > > + Register. > > > > + @param Value The value to write. > > > > + > > > > + @return The value written to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT16 > > > > +EFIAPI > > > > +PciWrite16 ( > > > > + IN UINTN Address, > > > > + IN UINT16 Value > > > > + ) > > > > +{ > > > > + if (mMMCONFEnabled) { > > > > + return PciExpressWrite16 (Address, Value); > > > > + } else { > > > > + return PciCf8Write16 (Address, Value); > > > > + } > > > > +} > > > > + > > > > +/** > > > > + Performs a bitwise OR of a 16-bit PCI configuration register with > > > > + a 16-bit value. > > > > + > > > > + Reads the 16-bit PCI configuration register specified by Address, > performs > > a > > > > + bitwise OR between the read result and the value specified by > > > > + OrData, and writes the result to the 16-bit PCI configuration regist= er > > > > + specified by Address. The value written to the PCI configuration > register is > > > > + returned. This function must guarantee that all PCI read and write > > operations > > > > + are serialized. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > > > > + > > > > + @param Address The address that encodes the PCI Bus, Device, Functi= on > > and > > > > + Register. > > > > + @param OrData The value to OR with the PCI configuration register. > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT16 > > > > +EFIAPI > > > > +PciOr16 ( > > > > + IN UINTN Address, > > > > + IN UINT16 OrData > > > > + ) > > > > +{ > > > > + if (mMMCONFEnabled) { > > > > + return PciExpressOr16 (Address, OrData); > > > > + } else { > > > > + return PciCf8Or16 (Address, OrData); > > > > + } > > > > +} > > > > + > > > > +/** > > > > + Performs a bitwise AND of a 16-bit PCI configuration register with a > 16-bit > > > > + value. > > > > + > > > > + Reads the 16-bit PCI configuration register specified by Address, > performs > > a > > > > + bitwise AND between the read result and the value specified by > AndData, > > and > > > > + writes the result to the 16-bit PCI configuration register specified > by > > > > + Address. The value written to the PCI configuration register is > returned. > > > > + This function must guarantee that all PCI read and write operations > are > > > > + serialized. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > > > > + > > > > + @param Address The address that encodes the PCI Bus, Device, Functi= on > > and > > > > + Register. > > > > + @param AndData The value to AND with the PCI configuration register= . > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT16 > > > > +EFIAPI > > > > +PciAnd16 ( > > > > + IN UINTN Address, > > > > + IN UINT16 AndData > > > > + ) > > > > +{ > > > > + if (mMMCONFEnabled) { > > > > + return PciExpressAnd16 (Address, AndData); > > > > + } else { > > > > + return PciCf8And16 (Address, AndData); > > > > + } > > > > +} > > > > + > > > > +/** > > > > + Performs a bitwise AND of a 16-bit PCI configuration register with a > 16-bit > > > > + value, followed a bitwise OR with another 16-bit value. > > > > + > > > > + Reads the 16-bit PCI configuration register specified by Address, > performs > > a > > > > + bitwise AND between the read result and the value specified by > AndData, > > > > + performs a bitwise OR between the result of the AND operation and > > > > + the value specified by OrData, and writes the result to the 16-bit P= CI > > > > + configuration register specified by Address. The value written to th= e > PCI > > > > + configuration register is returned. This function must guarantee tha= t > all PCI > > > > + read and write operations are serialized. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > > > > + > > > > + @param Address The address that encodes the PCI Bus, Device, Functi= on > > and > > > > + Register. > > > > + @param AndData The value to AND with the PCI configuration register= . > > > > + @param OrData The value to OR with the result of the AND operation= . > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT16 > > > > +EFIAPI > > > > +PciAndThenOr16 ( > > > > + IN UINTN Address, > > > > + IN UINT16 AndData, > > > > + IN UINT16 OrData > > > > + ) > > > > +{ > > > > + if (mMMCONFEnabled) { > > > > + return PciExpressAndThenOr16 (Address, AndData, OrData); > > > > + } else { > > > > + return PciCf8AndThenOr16 (Address, AndData, OrData); > > > > + } > > > > +} > > > > + > > > > +/** > > > > + Reads a bit field of a PCI configuration register. > > > > + > > > > + Reads the bit field in a 16-bit PCI configuration register. The bit > field is > > > > + specified by the StartBit and the EndBit. The value of the bit field > is > > > > + returned. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > > > > + If StartBit is greater than 15, then ASSERT(). > > > > + If EndBit is greater than 15, then ASSERT(). > > > > + If EndBit is less than StartBit, then ASSERT(). > > > > + > > > > + @param Address The PCI configuration register to read. > > > > + @param StartBit The ordinal of the least significant bit in the bi= t > field. > > > > + Range 0..15. > > > > + @param EndBit The ordinal of the most significant bit in the bit > field. > > > > + Range 0..15. > > > > + > > > > + @return The value of the bit field read from the PCI configuration > register. > > > > + > > > > +**/ > > > > +UINT16 > > > > +EFIAPI > > > > +PciBitFieldRead16 ( > > > > + IN UINTN Address, > > > > + IN UINTN StartBit, > > > > + IN UINTN EndBit > > > > + ) > > > > +{ > > > > + if (mMMCONFEnabled) { > > > > + return PciExpressBitFieldRead16 (Address, StartBit, EndBit); > > > > + } else { > > > > + return PciCf8BitFieldRead16 (Address, StartBit, EndBit); > > > > + } > > > > +} > > > > + > > > > +/** > > > > + Writes a bit field to a PCI configuration register. > > > > + > > > > + Writes Value to the bit field of the PCI configuration register. The > bit > > > > + field is specified by the StartBit and the EndBit. All other bits in > the > > > > + destination PCI configuration register are preserved. The new value > of the > > > > + 16-bit register is returned. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > > > > + If StartBit is greater than 15, then ASSERT(). > > > > + If EndBit is greater than 15, then ASSERT(). > > > > + If EndBit is less than StartBit, then ASSERT(). > > > > + If Value is larger than the bitmask value range specified by StartBi= t > and > > EndBit, then ASSERT(). > > > > + > > > > + @param Address The PCI configuration register to write. > > > > + @param StartBit The ordinal of the least significant bit in the bi= t > field. > > > > + Range 0..15. > > > > + @param EndBit The ordinal of the most significant bit in the bit > field. > > > > + Range 0..15. > > > > + @param Value The new value of the bit field. > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT16 > > > > +EFIAPI > > > > +PciBitFieldWrite16 ( > > > > + IN UINTN Address, > > > > + IN UINTN StartBit, > > > > + IN UINTN EndBit, > > > > + IN UINT16 Value > > > > + ) > > > > +{ > > > > + if (mMMCONFEnabled) { > > > > + return PciExpressBitFieldWrite16 (Address, StartBit, EndBit, Value= ); > > > > + } else { > > > > + return PciCf8BitFieldWrite16 (Address, StartBit, EndBit, Value); > > > > + } > > > > +} > > > > + > > > > +/** > > > > + Reads a bit field in a 16-bit PCI configuration, performs a bitwise > OR, and > > > > + writes the result back to the bit field in the 16-bit port. > > > > + > > > > + Reads the 16-bit PCI configuration register specified by Address, > performs > > a > > > > + bitwise OR between the read result and the value specified by > > > > + OrData, and writes the result to the 16-bit PCI configuration regist= er > > > > + specified by Address. The value written to the PCI configuration > register is > > > > + returned. This function must guarantee that all PCI read and write > > operations > > > > + are serialized. Extra left bits in OrData are stripped. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > > > > + If StartBit is greater than 15, then ASSERT(). > > > > + If EndBit is greater than 15, then ASSERT(). > > > > + If EndBit is less than StartBit, then ASSERT(). > > > > + If OrData is larger than the bitmask value range specified by > StartBit and > > EndBit, then ASSERT(). > > > > + > > > > + @param Address The PCI configuration register to write. > > > > + @param StartBit The ordinal of the least significant bit in the bi= t > field. > > > > + Range 0..15. > > > > + @param EndBit The ordinal of the most significant bit in the bit > field. > > > > + Range 0..15. > > > > + @param OrData The value to OR with the PCI configuration registe= r. > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT16 > > > > +EFIAPI > > > > +PciBitFieldOr16 ( > > > > + IN UINTN Address, > > > > + IN UINTN StartBit, > > > > + IN UINTN EndBit, > > > > + IN UINT16 OrData > > > > + ) > > > > +{ > > > > + if (mMMCONFEnabled) { > > > > + return PciExpressBitFieldOr16 (Address, StartBit, EndBit, OrData); > > > > + } else { > > > > + return PciCf8BitFieldOr16 (Address, StartBit, EndBit, OrData); > > > > + } > > > > +} > > > > + > > > > +/** > > > > + Reads a bit field in a 16-bit PCI configuration register, performs a > bitwise > > > > + AND, and writes the result back to the bit field in the 16-bit > register. > > > > + > > > > + Reads the 16-bit PCI configuration register specified by Address, > performs > > a > > > > + bitwise AND between the read result and the value specified by > AndData, > > and > > > > + writes the result to the 16-bit PCI configuration register specified > by > > > > + Address. The value written to the PCI configuration register is > returned. > > > > + This function must guarantee that all PCI read and write operations > are > > > > + serialized. Extra left bits in AndData are stripped. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > > > > + If StartBit is greater than 15, then ASSERT(). > > > > + If EndBit is greater than 15, then ASSERT(). > > > > + If EndBit is less than StartBit, then ASSERT(). > > > > + If AndData is larger than the bitmask value range specified by > StartBit and > > EndBit, then ASSERT(). > > > > + > > > > + @param Address The PCI configuration register to write. > > > > + @param StartBit The ordinal of the least significant bit in the bi= t > field. > > > > + Range 0..15. > > > > + @param EndBit The ordinal of the most significant bit in the bit > field. > > > > + Range 0..15. > > > > + @param AndData The value to AND with the PCI configuration > register. > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT16 > > > > +EFIAPI > > > > +PciBitFieldAnd16 ( > > > > + IN UINTN Address, > > > > + IN UINTN StartBit, > > > > + IN UINTN EndBit, > > > > + IN UINT16 AndData > > > > + ) > > > > +{ > > > > + if (mMMCONFEnabled) { > > > > + return PciExpressBitFieldAnd16 (Address, StartBit, EndBit, AndData= ); > > > > + } else { > > > > + return PciCf8BitFieldAnd16 (Address, StartBit, EndBit, AndData); > > > > + } > > > > +} > > > > + > > > > +/** > > > > + Reads a bit field in a 16-bit port, performs a bitwise AND followed > by a > > > > + bitwise OR, and writes the result back to the bit field in the > > > > + 16-bit port. > > > > + > > > > + Reads the 16-bit PCI configuration register specified by Address, > performs > > a > > > > + bitwise AND followed by a bitwise OR between the read result and > > > > + the value specified by AndData, and writes the result to the 16-bit > PCI > > > > + configuration register specified by Address. The value written to th= e > PCI > > > > + configuration register is returned. This function must guarantee tha= t > all PCI > > > > + read and write operations are serialized. Extra left bits in both > AndData and > > > > + OrData are stripped. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > > > > + If StartBit is greater than 15, then ASSERT(). > > > > + If EndBit is greater than 15, then ASSERT(). > > > > + If EndBit is less than StartBit, then ASSERT(). > > > > + If AndData is larger than the bitmask value range specified by > StartBit and > > EndBit, then ASSERT(). > > > > + If OrData is larger than the bitmask value range specified by > StartBit and > > EndBit, then ASSERT(). > > > > + > > > > + @param Address The PCI configuration register to write. > > > > + @param StartBit The ordinal of the least significant bit in the bi= t > field. > > > > + Range 0..15. > > > > + @param EndBit The ordinal of the most significant bit in the bit > field. > > > > + Range 0..15. > > > > + @param AndData The value to AND with the PCI configuration > register. > > > > + @param OrData The value to OR with the result of the AND > operation. > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT16 > > > > +EFIAPI > > > > +PciBitFieldAndThenOr16 ( > > > > + IN UINTN Address, > > > > + IN UINTN StartBit, > > > > + IN UINTN EndBit, > > > > + IN UINT16 AndData, > > > > + IN UINT16 OrData > > > > + ) > > > > +{ > > > > + if (mMMCONFEnabled) { > > > > + return PciExpressBitFieldAndThenOr16 (Address, StartBit, EndBit, > > AndData, OrData); > > > > + } else { > > > > + return PciCf8BitFieldAndThenOr16 (Address, StartBit, EndBit, > AndData, > > OrData); > > > > + } > > > > +} > > > > + > > > > +/** > > > > + Reads a 32-bit PCI configuration register. > > > > + > > > > + Reads and returns the 32-bit PCI configuration register specified by > > Address. > > > > + This function must guarantee that all PCI read and write operations > are > > > > + serialized. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > > > > + > > > > + @param Address The address that encodes the PCI Bus, Device, Functi= on > > and > > > > + Register. > > > > + > > > > + @return The read value from the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT32 > > > > +EFIAPI > > > > +PciRead32 ( > > > > + IN UINTN Address > > > > + ) > > > > +{ > > > > + if (mMMCONFEnabled) { > > > > + return PciExpressRead32 (Address); > > > > + } else { > > > > + return PciCf8Read32 (Address); > > > > + } > > > > +} > > > > + > > > > +/** > > > > + Writes a 32-bit PCI configuration register. > > > > + > > > > + Writes the 32-bit PCI configuration register specified by Address > with the > > > > + value specified by Value. Value is returned. This function must > guarantee > > > > + that all PCI read and write operations are serialized. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > > > > + > > > > + @param Address The address that encodes the PCI Bus, Device, Functi= on > > and > > > > + Register. > > > > + @param Value The value to write. > > > > + > > > > + @return The value written to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT32 > > > > +EFIAPI > > > > +PciWrite32 ( > > > > + IN UINTN Address, > > > > + IN UINT32 Value > > > > + ) > > > > +{ > > > > + if (mMMCONFEnabled) { > > > > + return PciExpressWrite32 (Address, Value); > > > > + } else { > > > > + return PciCf8Write32 (Address, Value); > > > > + } > > > > +} > > > > + > > > > +/** > > > > + Performs a bitwise OR of a 32-bit PCI configuration register with > > > > + a 32-bit value. > > > > + > > > > + Reads the 32-bit PCI configuration register specified by Address, > performs > > a > > > > + bitwise OR between the read result and the value specified by > > > > + OrData, and writes the result to the 32-bit PCI configuration regist= er > > > > + specified by Address. The value written to the PCI configuration > register is > > > > + returned. This function must guarantee that all PCI read and write > > operations > > > > + are serialized. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > > > > + > > > > + @param Address The address that encodes the PCI Bus, Device, Functi= on > > and > > > > + Register. > > > > + @param OrData The value to OR with the PCI configuration register. > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT32 > > > > +EFIAPI > > > > +PciOr32 ( > > > > + IN UINTN Address, > > > > + IN UINT32 OrData > > > > + ) > > > > +{ > > > > + if (mMMCONFEnabled) { > > > > + return PciExpressOr32 (Address, OrData); > > > > + } else { > > > > + return PciCf8Or32 (Address, OrData); > > > > + } > > > > +} > > > > + > > > > +/** > > > > + Performs a bitwise AND of a 32-bit PCI configuration register with a > 32-bit > > > > + value. > > > > + > > > > + Reads the 32-bit PCI configuration register specified by Address, > performs > > a > > > > + bitwise AND between the read result and the value specified by > AndData, > > and > > > > + writes the result to the 32-bit PCI configuration register specified > by > > > > + Address. The value written to the PCI configuration register is > returned. > > > > + This function must guarantee that all PCI read and write operations > are > > > > + serialized. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > > > > + > > > > + @param Address The address that encodes the PCI Bus, Device, Functi= on > > and > > > > + Register. > > > > + @param AndData The value to AND with the PCI configuration register= . > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT32 > > > > +EFIAPI > > > > +PciAnd32 ( > > > > + IN UINTN Address, > > > > + IN UINT32 AndData > > > > + ) > > > > +{ > > > > + if (mMMCONFEnabled) { > > > > + return PciExpressAnd32 (Address, AndData); > > > > + } else { > > > > + return PciCf8And32 (Address, AndData); > > > > + } > > > > +} > > > > + > > > > +/** > > > > + Performs a bitwise AND of a 32-bit PCI configuration register with a > 32-bit > > > > + value, followed a bitwise OR with another 32-bit value. > > > > + > > > > + Reads the 32-bit PCI configuration register specified by Address, > performs > > a > > > > + bitwise AND between the read result and the value specified by > AndData, > > > > + performs a bitwise OR between the result of the AND operation and > > > > + the value specified by OrData, and writes the result to the 32-bit P= CI > > > > + configuration register specified by Address. The value written to th= e > PCI > > > > + configuration register is returned. This function must guarantee tha= t > all PCI > > > > + read and write operations are serialized. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > > > > + > > > > + @param Address The address that encodes the PCI Bus, Device, Functi= on > > and > > > > + Register. > > > > + @param AndData The value to AND with the PCI configuration register= . > > > > + @param OrData The value to OR with the result of the AND operation= . > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT32 > > > > +EFIAPI > > > > +PciAndThenOr32 ( > > > > + IN UINTN Address, > > > > + IN UINT32 AndData, > > > > + IN UINT32 OrData > > > > + ) > > > > +{ > > > > + if (mMMCONFEnabled) { > > > > + return PciExpressAndThenOr32 (Address, AndData, OrData); > > > > + } else { > > > > + return PciCf8AndThenOr32 (Address, AndData, OrData); > > > > + } > > > > +} > > > > + > > > > +/** > > > > + Reads a bit field of a PCI configuration register. > > > > + > > > > + Reads the bit field in a 32-bit PCI configuration register. The bit > field is > > > > + specified by the StartBit and the EndBit. The value of the bit field > is > > > > + returned. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > > > > + If StartBit is greater than 31, then ASSERT(). > > > > + If EndBit is greater than 31, then ASSERT(). > > > > + If EndBit is less than StartBit, then ASSERT(). > > > > + > > > > + @param Address The PCI configuration register to read. > > > > + @param StartBit The ordinal of the least significant bit in the bi= t > field. > > > > + Range 0..31. > > > > + @param EndBit The ordinal of the most significant bit in the bit > field. > > > > + Range 0..31. > > > > + > > > > + @return The value of the bit field read from the PCI configuration > register. > > > > + > > > > +**/ > > > > +UINT32 > > > > +EFIAPI > > > > +PciBitFieldRead32 ( > > > > + IN UINTN Address, > > > > + IN UINTN StartBit, > > > > + IN UINTN EndBit > > > > + ) > > > > +{ > > > > + if (mMMCONFEnabled) { > > > > + return PciExpressBitFieldRead32 (Address, StartBit, EndBit); > > > > + } else { > > > > + return PciCf8BitFieldRead32 (Address, StartBit, EndBit); > > > > + } > > > > +} > > > > + > > > > +/** > > > > + Writes a bit field to a PCI configuration register. > > > > + > > > > + Writes Value to the bit field of the PCI configuration register. The > bit > > > > + field is specified by the StartBit and the EndBit. All other bits in > the > > > > + destination PCI configuration register are preserved. The new value > of the > > > > + 32-bit register is returned. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > > > > + If StartBit is greater than 31, then ASSERT(). > > > > + If EndBit is greater than 31, then ASSERT(). > > > > + If EndBit is less than StartBit, then ASSERT(). > > > > + If Value is larger than the bitmask value range specified by StartBi= t > and > > EndBit, then ASSERT(). > > > > + > > > > + @param Address The PCI configuration register to write. > > > > + @param StartBit The ordinal of the least significant bit in the bi= t > field. > > > > + Range 0..31. > > > > + @param EndBit The ordinal of the most significant bit in the bit > field. > > > > + Range 0..31. > > > > + @param Value The new value of the bit field. > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT32 > > > > +EFIAPI > > > > +PciBitFieldWrite32 ( > > > > + IN UINTN Address, > > > > + IN UINTN StartBit, > > > > + IN UINTN EndBit, > > > > + IN UINT32 Value > > > > + ) > > > > +{ > > > > + if (mMMCONFEnabled) { > > > > + return PciExpressBitFieldWrite32 (Address, StartBit, EndBit, Value= ); > > > > + } else { > > > > + return PciCf8BitFieldWrite32 (Address, StartBit, EndBit, Value); > > > > + } > > > > +} > > > > + > > > > +/** > > > > + Reads a bit field in a 32-bit PCI configuration, performs a bitwise > OR, and > > > > + writes the result back to the bit field in the 32-bit port. > > > > + > > > > + Reads the 32-bit PCI configuration register specified by Address, > performs > > a > > > > + bitwise OR between the read result and the value specified by > > > > + OrData, and writes the result to the 32-bit PCI configuration regist= er > > > > + specified by Address. The value written to the PCI configuration > register is > > > > + returned. This function must guarantee that all PCI read and write > > operations > > > > + are serialized. Extra left bits in OrData are stripped. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > > > > + If StartBit is greater than 31, then ASSERT(). > > > > + If EndBit is greater than 31, then ASSERT(). > > > > + If EndBit is less than StartBit, then ASSERT(). > > > > + If OrData is larger than the bitmask value range specified by > StartBit and > > EndBit, then ASSERT(). > > > > + > > > > + @param Address The PCI configuration register to write. > > > > + @param StartBit The ordinal of the least significant bit in the bi= t > field. > > > > + Range 0..31. > > > > + @param EndBit The ordinal of the most significant bit in the bit > field. > > > > + Range 0..31. > > > > + @param OrData The value to OR with the PCI configuration registe= r. > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT32 > > > > +EFIAPI > > > > +PciBitFieldOr32 ( > > > > + IN UINTN Address, > > > > + IN UINTN StartBit, > > > > + IN UINTN EndBit, > > > > + IN UINT32 OrData > > > > + ) > > > > +{ > > > > + if (mMMCONFEnabled) { > > > > + return PciExpressBitFieldOr32 (Address, StartBit, EndBit, OrData); > > > > + } else { > > > > + return PciCf8BitFieldOr32 (Address, StartBit, EndBit, OrData); > > > > + } > > > > +} > > > > + > > > > +/** > > > > + Reads a bit field in a 32-bit PCI configuration register, performs a > bitwise > > > > + AND, and writes the result back to the bit field in the 32-bit > register. > > > > + > > > > + Reads the 32-bit PCI configuration register specified by Address, > performs > > a > > > > + bitwise AND between the read result and the value specified by > AndData, > > and > > > > + writes the result to the 32-bit PCI configuration register specified > by > > > > + Address. The value written to the PCI configuration register is > returned. > > > > + This function must guarantee that all PCI read and write operations > are > > > > + serialized. Extra left bits in AndData are stripped. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > > > > + If StartBit is greater than 31, then ASSERT(). > > > > + If EndBit is greater than 31, then ASSERT(). > > > > + If EndBit is less than StartBit, then ASSERT(). > > > > + If AndData is larger than the bitmask value range specified by > StartBit and > > EndBit, then ASSERT(). > > > > + > > > > + @param Address The PCI configuration register to write. > > > > + @param StartBit The ordinal of the least significant bit in the bi= t > field. > > > > + Range 0..31. > > > > + @param EndBit The ordinal of the most significant bit in the bit > field. > > > > + Range 0..31. > > > > + @param AndData The value to AND with the PCI configuration > register. > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT32 > > > > +EFIAPI > > > > +PciBitFieldAnd32 ( > > > > + IN UINTN Address, > > > > + IN UINTN StartBit, > > > > + IN UINTN EndBit, > > > > + IN UINT32 AndData > > > > + ) > > > > +{ > > > > + if (mMMCONFEnabled) { > > > > + return PciExpressBitFieldAnd32 (Address, StartBit, EndBit, AndData= ); > > > > + } else { > > > > + return PciCf8BitFieldAnd32 (Address, StartBit, EndBit, AndData); > > > > + } > > > > +} > > > > + > > > > +/** > > > > + Reads a bit field in a 32-bit port, performs a bitwise AND followed > by a > > > > + bitwise OR, and writes the result back to the bit field in the > > > > + 32-bit port. > > > > + > > > > + Reads the 32-bit PCI configuration register specified by Address, > performs > > a > > > > + bitwise AND followed by a bitwise OR between the read result and > > > > + the value specified by AndData, and writes the result to the 32-bit > PCI > > > > + configuration register specified by Address. The value written to th= e > PCI > > > > + configuration register is returned. This function must guarantee tha= t > all PCI > > > > + read and write operations are serialized. Extra left bits in both > AndData and > > > > + OrData are stripped. > > > > + > > > > + If Address > 0x0FFFFFFF, then ASSERT(). > > > > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > > > > + If StartBit is greater than 31, then ASSERT(). > > > > + If EndBit is greater than 31, then ASSERT(). > > > > + If EndBit is less than StartBit, then ASSERT(). > > > > + If AndData is larger than the bitmask value range specified by > StartBit and > > EndBit, then ASSERT(). > > > > + If OrData is larger than the bitmask value range specified by > StartBit and > > EndBit, then ASSERT(). > > > > + > > > > + @param Address The PCI configuration register to write. > > > > + @param StartBit The ordinal of the least significant bit in the bi= t > field. > > > > + Range 0..31. > > > > + @param EndBit The ordinal of the most significant bit in the bit > field. > > > > + Range 0..31. > > > > + @param AndData The value to AND with the PCI configuration > register. > > > > + @param OrData The value to OR with the result of the AND > operation. > > > > + > > > > + @return The value written back to the PCI configuration register. > > > > + > > > > +**/ > > > > +UINT32 > > > > +EFIAPI > > > > +PciBitFieldAndThenOr32 ( > > > > + IN UINTN Address, > > > > + IN UINTN StartBit, > > > > + IN UINTN EndBit, > > > > + IN UINT32 AndData, > > > > + IN UINT32 OrData > > > > + ) > > > > +{ > > > > + if (mMMCONFEnabled) { > > > > + return PciExpressBitFieldAndThenOr32 (Address, StartBit, EndBit, > > AndData, OrData); > > > > + } else { > > > > + return PciCf8BitFieldAndThenOr32 (Address, StartBit, EndBit, > AndData, > > OrData); > > > > + } > > > > +} > > > > + > > > > +/** > > > > + Reads a range of PCI configuration registers into a caller supplied > buffer. > > > > + > > > > + Reads the range of PCI configuration registers specified by > StartAddress > > and > > > > + Size into the buffer specified by Buffer. This function only allows > the PCI > > > > + configuration registers from a single PCI function to be read. Size = is > > > > + returned. When possible 32-bit PCI configuration read cycles are use= d > to > > read > > > > + from StartAdress to StartAddress + Size. Due to alignment > restrictions, 8- > > bit > > > > + and 16-bit PCI configuration read cycles may be used at the beginnin= g > and > > the > > > > + end of the range. > > > > + > > > > + If StartAddress > 0x0FFFFFFF, then ASSERT(). > > > > + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). > > > > + If Size > 0 and Buffer is NULL, then ASSERT(). > > > > + > > > > + @param StartAddress The starting address that encodes the PCI Bus, > > Device, > > > > + Function and Register. > > > > + @param Size The size in bytes of the transfer. > > > > + @param Buffer The pointer to a buffer receiving the data rea= d. > > > > + > > > > + @return Size > > > > + > > > > +**/ > > > > +UINTN > > > > +EFIAPI > > > > +PciReadBuffer ( > > > > + IN UINTN StartAddress, > > > > + IN UINTN Size, > > > > + OUT VOID *Buffer > > > > + ) > > > > +{ > > > > + if (mMMCONFEnabled) { > > > > + return PciExpressReadBuffer (StartAddress, Size, Buffer); > > > > + } else { > > > > + return PciCf8ReadBuffer (StartAddress, Size, Buffer); > > > > + } > > > > +} > > > > + > > > > +/** > > > > + Copies the data in a caller supplied buffer to a specified range of > PCI > > > > + configuration space. > > > > + > > > > + Writes the range of PCI configuration registers specified by > StartAddress > > and > > > > + Size from the buffer specified by Buffer. This function only allows > the PCI > > > > + configuration registers from a single PCI function to be written. > Size is > > > > + returned. When possible 32-bit PCI configuration write cycles are > used to > > > > + write from StartAdress to StartAddress + Size. Due to alignment > > restrictions, > > > > + 8-bit and 16-bit PCI configuration write cycles may be used at the > beginning > > > > + and the end of the range. > > > > + > > > > + If StartAddress > 0x0FFFFFFF, then ASSERT(). > > > > + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). > > > > + If Size > 0 and Buffer is NULL, then ASSERT(). > > > > + > > > > + @param StartAddress The starting address that encodes the PCI Bus, > > Device, > > > > + Function and Register. > > > > + @param Size The size in bytes of the transfer. > > > > + @param Buffer The pointer to a buffer containing the data to > write. > > > > + > > > > + @return Size written to StartAddress. > > > > + > > > > +**/ > > > > +UINTN > > > > +EFIAPI > > > > +PciWriteBuffer ( > > > > + IN UINTN StartAddress, > > > > + IN UINTN Size, > > > > + IN VOID *Buffer > > > > + ) > > > > +{ > > > > + if (mMMCONFEnabled) { > > > > + return PciExpressWriteBuffer (StartAddress, Size, Buffer); > > > > + } else { > > > > + return PciCf8WriteBuffer (StartAddress, Size, Buffer); > > > > + } > > > > +} > > > > diff --git > a/UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLib.uni > > b/UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLib.uni > > new file mode 100644 > > index 000000000000..98010ef2f929 > > --- /dev/null > > +++ b/UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLib.uni > > @@ -0,0 +1,17 @@ > > +// /** @file > > > > +// Instance of PCI Express Library using the 256 MB PCI Express MMIO > > window. > > > > +// > > > > +// PCI Express Library that uses the 256 MB PCI Express MMIO window to > > perform > > > > +// PCI Configuration cycles. Layers on top of an I/O Library instance. > > > > +// > > > > +// Copyright (c) 2007 - 2014, Intel Corporation. All rights > reserved.
> > > > +// > > > > +// SPDX-License-Identifier: BSD-2-Clause-Patent > > > > +// > > > > +// **/ > > > > + > > > > + > > > > +#string STR_MODULE_ABSTRACT #language en-US "Instance of P= CI > > Express Library using the 256 MB PCI Express MMIO window" > > > > + > > > > +#string STR_MODULE_DESCRIPTION #language en-US "PCI Express > > Library that uses the 256 MB PCI Express MMIO window to perform PCI > > Configuration cycles. Layers on top of an I/O Library instance." > > > > + > > > > diff --git > > a/UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.uni > > b/UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.uni > > new file mode 100644 > > index 000000000000..ccc456356cf2 > > --- /dev/null > > +++ > > b/UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.uni > > @@ -0,0 +1,17 @@ > > +// /** @file > > > > +// Instance of PCI Library based on PCI Express Library. > > > > +// > > > > +// PCI Library that uses the 256 MB PCI Express MMIO window to perform > > PCI > > > > +// Configuration cycles. Layers on one PCI Express Library instance. > > > > +// > > > > +// Copyright (c) 2007 - 2014, Intel Corporation. All rights > reserved.
> > > > +// > > > > +// SPDX-License-Identifier: BSD-2-Clause-Patent > > > > +// > > > > +// **/ > > > > + > > > > + > > > > +#string STR_MODULE_ABSTRACT #language en-US "Instance of P= CI > > Library based on PCI Express Library" > > > > + > > > > +#string STR_MODULE_DESCRIPTION #language en-US "PCI Library > that > > uses the 256 MB PCI Express MMIO window to perform PCI Configuration > > cycles. Layers on an PCI Express Library instance." > > > > + > > > > -- > > 2.25.4 > > > > > > -=3D-=3D-=3D-=3D-=3D-=3D > > Groups.io Links: You receive all messages sent to this group. > > > > View/Reply Online (#61655): https://edk2.groups.io/g/devel/message/6165= 5 > > Mute This Topic: https://groups.io/mt/75080104/1781375 > > Group Owner: devel+owner@edk2.groups.io > > Unsubscribe: https://edk2.groups.io/g/devel/unsub [guo.dong@intel.com] > > -=3D-=3D-=3D-=3D-=3D-=3D > > --=20 *[Marcello Sylvester Bauer]* 9elements Agency GmbH, Kortumstra=C3=9Fe 19-21, 44787 Bochum, Germany Email: [DEINE EMAIL ADDRESSE] Phone: *+49 234 68 94 188 <+492346894188>* Mobile: *+49 1722847618 <+491722847618>* Sitz der Gesellschaft: Bochum Handelsregister: Amtsgericht Bochum, HRB 17519 Gesch=C3=A4ftsf=C3=BChrung: Sebastian Deutsch, Eray Basar Datenschutzhinweise nach Art. 13 DSGVO --0000000000006876ba05a8e4cb95 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi=C2=A0Guo,

didn't see it, my bad.= Next time I will rebase again before submitting.

Best regards,
M= arcello=C2=A0

On Wed, Jun 24, 2020 at 4:41 PM Dong, Guo <guo.dong@intel.com> wro= te:

Hi Bauer,

Please check latest code, Ray just checked in a patch to remove hardcoded P= CIe base address as below.

commit 3900a63e3a1b9ba9a4105bedead7b986188cec2c
Author: Ray Ni <ra= y.ni@intel.com>
Date:=C2=A0 =C2=A0Wed Jun 17 16:34:29 2020 +0800
=C2=A0 =C2=A0 UefiPayloadPkg/Pci: Use the PCIE Base Addr stored in AcpiBoar= dInfo HOB

Thanks,
Guo

> -----Original Message-----
> From: devel@= edk2.groups.io <devel@edk2.groups.io> On Behalf Of
> Marcello Sylvester Bauer
> Sent: Wednesday, June 24, 2020 3:26 AM
> To: devel@ed= k2.groups.io
> Cc: Patrick Rudolph <patrick.rudolph@9elements.com>; Christian Walte= r
> <christian.walter@9elements.com>; Ma, Maurice <maurice.ma@intel.com>;
> Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Zeng, Star<= br> > <star.zeng= @intel.com>
> Subject: [edk2-devel] [PATCH v1 2/2] UefiPayloadPkg: Runtime MMCONF >
> From: Patrick Rudolph <patrick.rudolph@9elements.com>
>
> * Don't hardcode PCIE_BASE at build time
> * Support arbitrary platforms with different or even no MMCONF space > * Fix buffer overflow accessing MMCONF where less than 256 buses are >=C2=A0 =C2=A0exposed
> * Use PciCfg8 for PCI access in PEI, which is only used for debugging<= br> >
> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
> Signed-off-by: Marcello Sylvester Bauer <marcello.bauer@9elements.com>= ;
> Cc: Patrick Rudolph <patrick.rudolph@9elements.com>
> Cc: Christian Walter <christian.walter@9elements.com>
> Cc: Maurice Ma <maurice.ma@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Star Zeng <star.zeng@intel.com>
> ---
>=C2=A0 UefiPayloadPkg/UefiPayloadPkgIa32.dsc=C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 |=C2=A0 =C2=A016 +-
>=C2=A0 UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0|=C2=A0 =C2=A016 +-
>=C2=A0 UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLib.inf= =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A046 +
>=C2=A0 UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpress= .inf |=C2=A0 =C2=A042
> +
>=C2=A0 UefiPayloadPkg/Library/BasePciExpressLib/PciExpressLib.c=C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 1455
> ++++++++++++++++++++
>=C2=A0 UefiPayloadPkg/Library/BasePciLibPciExpress/PciLib.c=C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 1302
> ++++++++++++++++++
>=C2=A0 UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLib.uni= =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A017 +
>=C2=A0 UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpress= .uni |=C2=A0 =C2=A017
> +
>=C2=A0 8 files changed, 2885 insertions(+), 26 deletions(-)
>
> diff --git a/UefiPayloadPkg/UefiPayloadPkgIa32.dsc
> b/UefiPayloadPkg/UefiPayloadPkgIa32.dsc
> index c6c47833871b..48b03af6f223 100644
> --- a/UefiPayloadPkg/UefiPayloadPkgIa32.dsc
> +++ b/UefiPayloadPkg/UefiPayloadPkgIa32.dsc
> @@ -37,11 +37,6 @@ [Defines]
>=C2=A0 =C2=A0 #
>
>=C2=A0 =C2=A0 DEFINE MAX_LOGICAL_PROCESSORS=C2=A0 =C2=A0 =C2=A0 =C2=A0= =3D 64
>
>
>
> -=C2=A0 #
>
> -=C2=A0 # PCI options
>
> -=C2=A0 #
>
> -=C2=A0 DEFINE PCIE_BASE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =3D 0xE0000000
>
> -
>
>=C2=A0 =C2=A0 #
>
>=C2=A0 =C2=A0 # Serial port set up
>
>=C2=A0 =C2=A0 #
>
> @@ -121,13 +116,9 @@ [LibraryClasses]
>=C2=A0 =C2=A0 PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
>
>=C2=A0 =C2=A0 CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
>
>=C2=A0 =C2=A0 IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsi= c.inf
>
> -!if $(PCIE_BASE) =3D=3D 0
>
> -=C2=A0 PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
>
>=C2=A0 =C2=A0 PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf<= br> >
> -!else
>
> -=C2=A0 PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpres= s.inf
>
> -=C2=A0 PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressL= ib.inf
>
> -!endif
>
> +
> PciLib|UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpres= s.inf
>
> +
> PciExpressLib|UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressL= ib.i
> nf
>
>
> PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibP > ci.inf
>
>=C2=A0 =C2=A0 PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf<= br> >
>
> PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/Base<= br> > PeCoffGetEntryPointLib.inf
>
> @@ -216,6 +207,7 @@ [LibraryClasses.IA32.SEC]
>=C2=A0 [LibraryClasses.IA32.PEI_CORE, LibraryClasses.IA32.PEIM]
>
>=C2=A0 =C2=A0 PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
>
>=C2=A0 =C2=A0 HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
>
> +=C2=A0 PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
>
>
> MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemory > AllocationLib.inf
>
>
> ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiR > eportStatusCodeLib.inf
>
>
> ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiE= x
> tractGuidedSectionLib.inf
>
> @@ -286,8 +278,6 @@ [PcdsFixedAtBuild]
>=C2=A0 =C2=A0 gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FAL= SE
>
>=C2=A0 =C2=A0 gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0= x21,
> 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4= , 0x66,
> 0x23, 0x31 }
>
>
>
> -=C2=A0 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|$(PCIE_BASE)=
>
> -
>
>=C2=A0 !if $(SOURCE_DEBUG_ENABLE)
>
>
> gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x
> 2
>
>=C2=A0 !endif
>
> diff --git a/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc
> b/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc
> index 5559b1258521..af951ee5aec0 100644
> --- a/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc
> +++ b/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc
> @@ -38,11 +38,6 @@ [Defines]
>=C2=A0 =C2=A0 #
>
>=C2=A0 =C2=A0 DEFINE MAX_LOGICAL_PROCESSORS=C2=A0 =C2=A0 =C2=A0 =C2=A0= =3D 64
>
>
>
> -=C2=A0 #
>
> -=C2=A0 # PCI options
>
> -=C2=A0 #
>
> -=C2=A0 DEFINE PCIE_BASE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =3D 0xE0000000
>
> -
>
>=C2=A0 =C2=A0 #
>
>=C2=A0 =C2=A0 # Serial port set up
>
>=C2=A0 =C2=A0 #
>
> @@ -122,13 +117,9 @@ [LibraryClasses]
>=C2=A0 =C2=A0 PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
>
>=C2=A0 =C2=A0 CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
>
>=C2=A0 =C2=A0 IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsi= c.inf
>
> -!if $(PCIE_BASE) =3D=3D 0
>
> -=C2=A0 PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
>
>=C2=A0 =C2=A0 PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf<= br> >
> -!else
>
> -=C2=A0 PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpres= s.inf
>
> -=C2=A0 PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressL= ib.inf
>
> -!endif
>
> +
> PciLib|UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpres= s.inf
>
> +
> PciExpressLib|UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressL= ib.i
> nf
>
>
> PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibP > ci.inf
>
>=C2=A0 =C2=A0 PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf<= br> >
>
> PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/Base<= br> > PeCoffGetEntryPointLib.inf
>
> @@ -217,6 +208,7 @@ [LibraryClasses.IA32.SEC]
>=C2=A0 [LibraryClasses.IA32.PEI_CORE, LibraryClasses.IA32.PEIM]
>
>=C2=A0 =C2=A0 PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
>
>=C2=A0 =C2=A0 HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
>
> +=C2=A0 PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
>
>
> MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemory > AllocationLib.inf
>
>
> ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiR > eportStatusCodeLib.inf
>
>
> ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiE= x
> tractGuidedSectionLib.inf
>
> @@ -288,8 +280,6 @@ [PcdsFixedAtBuild]
>=C2=A0 =C2=A0 gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|TRUE
>
>=C2=A0 =C2=A0 gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0= x21,
> 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4= , 0x66,
> 0x23, 0x31 }
>
>
>
> -=C2=A0 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|$(PCIE_BASE)=
>
> -
>
>=C2=A0 !if $(SOURCE_DEBUG_ENABLE)
>
>
> gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x
> 2
>
>=C2=A0 !endif
>
> diff --git a/UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLi= b.inf
> b/UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLib.inf
> new file mode 100644
> index 000000000000..9f052c0a2e65
> --- /dev/null
> +++ b/UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLib.inf > @@ -0,0 +1,46 @@
> +## @file
>
> +#=C2=A0 Instance of PCI Express Library using the 256 MB PCI Express = MMIO
> window.
>
> +#
>
> +#=C2=A0 PCI Express Library that uses the 256 MB PCI Express MMIO win= dow to
> perform
>
> +#=C2=A0 PCI Configuration cycles. Layers on top of an I/O Library ins= tance.
>
> +#
>
> +#=C2=A0 Copyright (c) 2007 - 2018, Intel Corporation. All rights rese= rved.<BR>
>
> +#
>
> +#=C2=A0 SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +#
>
> +#
>
> +##
>
> +
>
> +[Defines]
>
> +=C2=A0 INF_VERSION=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =3D 0x00010005
>
> +=C2=A0 BASE_NAME=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =3D BasePciExpressLib
>
> +=C2=A0 MODULE_UNI_FILE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =3D BasePciExpressLib.uni
>
> +=C2=A0 FILE_GUID=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =3D 287e50f4-a188-4699-b907-3e4080ca5688
>
> +=C2=A0 MODULE_TYPE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =3D BASE
>
> +=C2=A0 VERSION_STRING=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0=3D 1.0
>
> +=C2=A0 LIBRARY_CLASS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =3D PciExpressLib
>
> +=C2=A0 CONSTRUCTOR=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =3D PciExpressLibInitialize
>
> +
>
> +#
>
> +#=C2=A0 VALID_ARCHITECTURES=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =3D IA32 X64 EBC
>
> +#
>
> +
>
> +[Sources]
>
> +=C2=A0 PciExpressLib.c
>
> +
>
> +[Packages]
>
> +=C2=A0 MdePkg/MdePkg.dec
>
> +=C2=A0 UefiPayloadPkg/UefiPayloadPkg.dec
>
> +
>
> +[LibraryClasses]
>
> +=C2=A0 BaseLib
>
> +=C2=A0 DebugLib
>
> +=C2=A0 HobLib
>
> +=C2=A0 IoLib
>
> +
>
> +[Guids]
>
> +=C2=A0 gUefiAcpiBoardInfoGuid
>
> +
>
> +[Pcd]
>
> +=C2=A0 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress=C2=A0 ## CON= SUMES
>
> +
>
> diff --git
> a/UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf=
> b/UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf=
> new file mode 100644
> index 000000000000..0858e49a47ae
> --- /dev/null
> +++ b/UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpress= .inf
> @@ -0,0 +1,42 @@
> +## @file
>
> +#=C2=A0 Instance of PCI Library based on PCI Express Library.
>
> +#
>
> +#=C2=A0 PCI Library that uses the 256 MB PCI Express MMIO window to p= erform
> PCI
>
> +#=C2=A0 Configuration cycles. Layers on one PCI Express Library insta= nce.
>
> +#
>
> +#=C2=A0 Copyright (c) 2007 - 2018, Intel Corporation. All rights rese= rved.<BR>
>
> +#
>
> +#=C2=A0 SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +#
>
> +#
>
> +##
>
> +
>
> +[Defines]
>
> +=C2=A0 INF_VERSION=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =3D 0x00010005
>
> +=C2=A0 BASE_NAME=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =3D BasePciLibPciExpress
>
> +=C2=A0 MODULE_UNI_FILE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =3D BasePciLibPciExpress.uni
>
> +=C2=A0 FILE_GUID=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =3D 8987081e-daeb-44a9-8bef-a195b22d9417
>
> +=C2=A0 MODULE_TYPE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =3D BASE
>
> +=C2=A0 VERSION_STRING=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0=3D 1.0
>
> +=C2=A0 LIBRARY_CLASS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =3D PciLib
>
> +=C2=A0 CONSTRUCTOR=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =3D PciLibInitialize
>
> +
>
> +#
>
> +#=C2=A0 VALID_ARCHITECTURES=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =3D IA32 X64
>
> +#
>
> +
>
> +[Sources]
>
> +=C2=A0 PciLib.c
>
> +
>
> +[Packages]
>
> +=C2=A0 MdePkg/MdePkg.dec
>
> +=C2=A0 UefiPayloadPkg/UefiPayloadPkg.dec
>
> +
>
> +[Guids]
>
> +=C2=A0 gUefiAcpiBoardInfoGuid
>
> +
>
> +[LibraryClasses]
>
> +=C2=A0 PciExpressLib
>
> +=C2=A0 PciCf8Lib
>
> +=C2=A0 BaseLib
>
> +=C2=A0 HobLib
>
> diff --git a/UefiPayloadPkg/Library/BasePciExpressLib/PciExpressLib.c<= br> > b/UefiPayloadPkg/Library/BasePciExpressLib/PciExpressLib.c
> new file mode 100644
> index 000000000000..f3b4582d3c47
> --- /dev/null
> +++ b/UefiPayloadPkg/Library/BasePciExpressLib/PciExpressLib.c
> @@ -0,0 +1,1455 @@
> +/** @file
>
> +=C2=A0 Functions in this library instance make use of MMIO functions = in IoLib to
>
> +=C2=A0 access memory mapped PCI configuration space.
>
> +
>
> +=C2=A0 All assertions for I/O operations are handled in MMIO function= s in the IoLib
>
> +=C2=A0 Library.
>
> +
>
> +=C2=A0 Copyright (c) 2006 - 2018, Intel Corporation. All rights reser= ved.<BR>
>
> +=C2=A0 SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +
>
> +**/
>
> +
>
> +
>
> +#include <Base.h>
>
> +
>
> +#include <Library/BaseLib.h>
>
> +#include <Library/PciExpressLib.h>
>
> +#include <Library/DebugLib.h>
>
> +#include <Library/IoLib.h>
>
> +#include <Library/BaseMemoryLib.h>
>
> +
>
> +#include <Pi/PiBootMode.h>
>
> +#include <Uefi/UefiBaseType.h>
>
> +#include <Uefi/UefiMultiPhase.h>
>
> +#include <Pi/PiHob.h>
>
> +
>
> +#include <Library/HobLib.h>
>
> +#include <Guid/AcpiBoardInfoGuid.h>
>
> +
>
> +STATIC ACPI_BOARD_INFO mBoardInfo;
>
> +/**
>
> +=C2=A0 Assert the validity of a PCI address.
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +
>
> +=C2=A0 Return 0xff on transaction outside of the MMCONF space.
>
> +
>
> +=C2=A0 @param=C2=A0 A The address to validate.
>
> +
>
> +**/
>
> +#define ASSERT_INVALID_PCI_ADDRESS(A) \
>
> +=C2=A0 ASSERT (((A) & ~0xfffffff) =3D=3D 0); \
>
> +=C2=A0 if ((A) >=3D mBoardInfo.PcieBaseSize) { \
>
> +=C2=A0 =C2=A0 return ~0; \
>
> +=C2=A0 }
>
> +
>
> +/**
>
> +=C2=A0 Registers a PCI device so PCI configuration registers may be a= ccessed after
>
> +=C2=A0 SetVirtualAddressMap().
>
> +
>
> +=C2=A0 Registers the PCI device specified by Address so all the PCI c= onfiguration
>
> +=C2=A0 registers associated with that PCI device may be accessed afte= r
> SetVirtualAddressMap()
>
> +=C2=A0 is called.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address The address that encodes the PCI Bus, Dev= ice, Function
> and
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Regist= er.
>
> +
>
> +=C2=A0 @retval RETURN_SUCCESS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0The PCI device was registered for runtime
> access.
>
> +=C2=A0 @retval RETURN_UNSUPPORTED=C2=A0 =C2=A0 =C2=A0 =C2=A0An attemp= t was made to call this
> function
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0after ExitBootServi= ces().
>
> +=C2=A0 @retval RETURN_UNSUPPORTED=C2=A0 =C2=A0 =C2=A0 =C2=A0The resou= rces required to access the
> PCI device
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0at runtime could no= t be mapped.
>
> +=C2=A0 @retval RETURN_OUT_OF_RESOURCES=C2=A0 There are not enough res= ources
> available to
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0complete the regist= ration.
>
> +
>
> +**/
>
> +RETURN_STATUS
>
> +EFIAPI
>
> +PciExpressRegisterForRuntimeAccess (
>
> +=C2=A0 IN UINTN=C2=A0 Address
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 ASSERT_INVALID_PCI_ADDRESS (Address);
>
> +=C2=A0 return RETURN_UNSUPPORTED;
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Performs platform specific initialization required for the CPU= to access
>
> +=C2=A0 the MMCONF space.=C2=A0 This function does not initialize the = MMCONF itself.
>
> +
>
> +=C2=A0 @retval RETURN_SUCCESS=C2=A0 =C2=A0 =C2=A0 =C2=A0The platform = specific initialization succeeded.
>
> +=C2=A0 @retval RETURN_DEVICE_ERROR=C2=A0 The platform specific initia= lization could
> not be completed.
>
> +
>
> +**/
>
> +RETURN_STATUS
>
> +EFIAPI
>
> +PciExpressLibInitialize (
>
> +=C2=A0 VOID
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 EFI_HOB_GUID_TYPE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*GuidHob; >
> +
>
> +=C2=A0 //
>
> +=C2=A0 // Find the acpi board information guid hob
>
> +=C2=A0 //
>
> +=C2=A0 GuidHob =3D GetFirstGuidHob (&gUefiAcpiBoardInfoGuid);
>
> +=C2=A0 ASSERT (GuidHob !=3D NULL);
>
> +=C2=A0 if (GuidHob =3D=3D NULL) {
>
> +=C2=A0 =C2=A0 return EFI_UNSUPPORTED;
>
> +=C2=A0 }
>
> +
>
> +=C2=A0 CopyMem (&mBoardInfo, GET_GUID_HOB_DATA (GuidHob),
> sizeof(mBoardInfo));
>
> +=C2=A0 return EFI_SUCCESS;
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Gets the base address of PCI Express.
>
> +
>
> +=C2=A0 This internal functions retrieves PCI Express Base Address via= a PCD entry
>
> +=C2=A0 PcdPciExpressBaseAddress.
>
> +
>
> +=C2=A0 @return The base address of PCI Express.
>
> +
>
> +**/
>
> +VOID*
>
> +GetPciExpressBaseAddress (
>
> +=C2=A0 VOID
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 return (VOID*)(UINTN) mBoardInfo.PcieBaseAddress;
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Reads an 8-bit PCI configuration register.
>
> +
>
> +=C2=A0 Reads and returns the 8-bit PCI configuration register specifi= ed by Address.
>
> +=C2=A0 This function must guarantee that all PCI read and write opera= tions are
>
> +=C2=A0 serialized.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address The address that encodes the PCI Bus, Dev= ice, Function
> and
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Regist= er.
>
> +
>
> +=C2=A0 @return The read value from the PCI configuration register. >
> +
>
> +**/
>
> +UINT8
>
> +EFIAPI
>
> +PciExpressRead8 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 ASSERT_INVALID_PCI_ADDRESS (Address);
>
> +=C2=A0 return MmioRead8 ((UINTN) GetPciExpressBaseAddress () + Addres= s);
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Writes an 8-bit PCI configuration register.
>
> +
>
> +=C2=A0 Writes the 8-bit PCI configuration register specified by Addre= ss with the
>
> +=C2=A0 value specified by Value. Value is returned. This function mus= t guarantee
>
> +=C2=A0 that all PCI read and write operations are serialized.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address The address that encodes the PCI Bus, Dev= ice, Function
> and
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Regist= er.
>
> +=C2=A0 @param=C2=A0 Value=C2=A0 =C2=A0The value to write.
>
> +
>
> +=C2=A0 @return The value written to the PCI configuration register. >
> +
>
> +**/
>
> +UINT8
>
> +EFIAPI
>
> +PciExpressWrite8 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Value
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 ASSERT_INVALID_PCI_ADDRESS (Address);
>
> +=C2=A0 return MmioWrite8 ((UINTN) GetPciExpressBaseAddress () + Addre= ss,
> Value);
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Performs a bitwise OR of an 8-bit PCI configuration register w= ith
>
> +=C2=A0 an 8-bit value.
>
> +
>
> +=C2=A0 Reads the 8-bit PCI configuration register specified by Addres= s, performs a
>
> +=C2=A0 bitwise OR between the read result and the value specified by<= br> >
> +=C2=A0 OrData, and writes the result to the 8-bit PCI configuration r= egister
>
> +=C2=A0 specified by Address. The value written to the PCI configurati= on register is
>
> +=C2=A0 returned. This function must guarantee that all PCI read and w= rite
> operations
>
> +=C2=A0 are serialized.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address The address that encodes the PCI Bus, Dev= ice, Function
> and
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Regist= er.
>
> +=C2=A0 @param=C2=A0 OrData=C2=A0 The value to OR with the PCI configu= ration register.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT8
>
> +EFIAPI
>
> +PciExpressOr8 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0OrData
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 ASSERT_INVALID_PCI_ADDRESS (Address);
>
> +=C2=A0 return MmioOr8 ((UINTN) GetPciExpressBaseAddress () + Address,=
> OrData);
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Performs a bitwise AND of an 8-bit PCI configuration register = with an 8-bit
>
> +=C2=A0 value.
>
> +
>
> +=C2=A0 Reads the 8-bit PCI configuration register specified by Addres= s, performs a
>
> +=C2=A0 bitwise AND between the read result and the value specified by= AndData,
> and
>
> +=C2=A0 writes the result to the 8-bit PCI configuration register spec= ified by
>
> +=C2=A0 Address. The value written to the PCI configuration register i= s returned.
>
> +=C2=A0 This function must guarantee that all PCI read and write opera= tions are
>
> +=C2=A0 serialized.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address The address that encodes the PCI Bus, Dev= ice, Function
> and
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Regist= er.
>
> +=C2=A0 @param=C2=A0 AndData The value to AND with the PCI configurati= on register.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT8
>
> +EFIAPI
>
> +PciExpressAnd8 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0AndData
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 ASSERT_INVALID_PCI_ADDRESS (Address);
>
> +=C2=A0 return MmioAnd8 ((UINTN) GetPciExpressBaseAddress () + Address= ,
> AndData);
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Performs a bitwise AND of an 8-bit PCI configuration register = with an 8-bit
>
> +=C2=A0 value, followed a=C2=A0 bitwise OR with another 8-bit value. >
> +
>
> +=C2=A0 Reads the 8-bit PCI configuration register specified by Addres= s, performs a
>
> +=C2=A0 bitwise AND between the read result and the value specified by= AndData,
>
> +=C2=A0 performs a bitwise OR between the result of the AND operation = and
>
> +=C2=A0 the value specified by OrData, and writes the result to the 8-= bit PCI
>
> +=C2=A0 configuration register specified by Address. The value written= to the PCI
>
> +=C2=A0 configuration register is returned. This function must guarant= ee that all PCI
>
> +=C2=A0 read and write operations are serialized.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address The address that encodes the PCI Bus, Dev= ice, Function
> and
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Regist= er.
>
> +=C2=A0 @param=C2=A0 AndData The value to AND with the PCI configurati= on register.
>
> +=C2=A0 @param=C2=A0 OrData=C2=A0 The value to OR with the result of t= he AND operation.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT8
>
> +EFIAPI
>
> +PciExpressAndThenOr8 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0AndData,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0OrData
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 ASSERT_INVALID_PCI_ADDRESS (Address);
>
> +=C2=A0 return MmioAndThenOr8 (
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(UINTN) GetPciExpressBaseAdd= ress () + Address,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0AndData,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0OrData
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0);
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Reads a bit field of a PCI configuration register.
>
> +
>
> +=C2=A0 Reads the bit field in an 8-bit PCI configuration register. Th= e bit field is
>
> +=C2=A0 specified by the StartBit and the EndBit. The value of the bit= field is
>
> +=C2=A0 returned.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If StartBit is greater than 7, then ASSERT().
>
> +=C2=A0 If EndBit is greater than 7, then ASSERT().
>
> +=C2=A0 If EndBit is less than StartBit, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address=C2=A0 =C2=A0The PCI configuration registe= r to read.
>
> +=C2=A0 @param=C2=A0 StartBit=C2=A0 The ordinal of the least significa= nt bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..7.
>
> +=C2=A0 @param=C2=A0 EndBit=C2=A0 =C2=A0 The ordinal of the most signi= ficant bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..7.
>
> +
>
> +=C2=A0 @return The value of the bit field read from the PCI configura= tion register.
>
> +
>
> +**/
>
> +UINT8
>
> +EFIAPI
>
> +PciExpressBitFieldRead8 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 ASSERT_INVALID_PCI_ADDRESS (Address);
>
> +=C2=A0 return MmioBitFieldRead8 (
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(UINTN) GetPciExpressBaseAdd= ress () + Address,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0);
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Writes a bit field to a PCI configuration register.
>
> +
>
> +=C2=A0 Writes Value to the bit field of the PCI configuration registe= r. The bit
>
> +=C2=A0 field is specified by the StartBit and the EndBit. All other b= its in the
>
> +=C2=A0 destination PCI configuration register are preserved. The new = value of the
>
> +=C2=A0 8-bit register is returned.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If StartBit is greater than 7, then ASSERT().
>
> +=C2=A0 If EndBit is greater than 7, then ASSERT().
>
> +=C2=A0 If EndBit is less than StartBit, then ASSERT().
>
> +=C2=A0 If Value is larger than the bitmask value range specified by S= tartBit and
> EndBit, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address=C2=A0 =C2=A0The PCI configuration registe= r to write.
>
> +=C2=A0 @param=C2=A0 StartBit=C2=A0 The ordinal of the least significa= nt bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..7.
>
> +=C2=A0 @param=C2=A0 EndBit=C2=A0 =C2=A0 The ordinal of the most signi= ficant bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..7.
>
> +=C2=A0 @param=C2=A0 Value=C2=A0 =C2=A0 =C2=A0The new value of the bit= field.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT8
>
> +EFIAPI
>
> +PciExpressBitFieldWrite8 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Value
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 ASSERT_INVALID_PCI_ADDRESS (Address);
>
> +=C2=A0 return MmioBitFieldWrite8 (
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(UINTN) GetPciExpressBaseAdd= ress () + Address,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Value
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0);
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Reads a bit field in an 8-bit PCI configuration, performs a bi= twise OR, and
>
> +=C2=A0 writes the result back to the bit field in the 8-bit port.
>
> +
>
> +=C2=A0 Reads the 8-bit PCI configuration register specified by Addres= s, performs a
>
> +=C2=A0 bitwise OR between the read result and the value specified by<= br> >
> +=C2=A0 OrData, and writes the result to the 8-bit PCI configuration r= egister
>
> +=C2=A0 specified by Address. The value written to the PCI configurati= on register is
>
> +=C2=A0 returned. This function must guarantee that all PCI read and w= rite
> operations
>
> +=C2=A0 are serialized. Extra left bits in OrData are stripped.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If StartBit is greater than 7, then ASSERT().
>
> +=C2=A0 If EndBit is greater than 7, then ASSERT().
>
> +=C2=A0 If EndBit is less than StartBit, then ASSERT().
>
> +=C2=A0 If OrData is larger than the bitmask value range specified by = StartBit and
> EndBit, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address=C2=A0 =C2=A0The PCI configuration registe= r to write.
>
> +=C2=A0 @param=C2=A0 StartBit=C2=A0 The ordinal of the least significa= nt bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..7.
>
> +=C2=A0 @param=C2=A0 EndBit=C2=A0 =C2=A0 The ordinal of the most signi= ficant bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..7.
>
> +=C2=A0 @param=C2=A0 OrData=C2=A0 =C2=A0 The value to OR with the PCI = configuration register.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT8
>
> +EFIAPI
>
> +PciExpressBitFieldOr8 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0OrData
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 ASSERT_INVALID_PCI_ADDRESS (Address);
>
> +=C2=A0 return MmioBitFieldOr8 (
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(UINTN) GetPciExpressBaseAdd= ress () + Address,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0OrData
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0);
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Reads a bit field in an 8-bit PCI configuration register, perf= orms a bitwise
>
> +=C2=A0 AND, and writes the result back to the bit field in the 8-bit = register.
>
> +
>
> +=C2=A0 Reads the 8-bit PCI configuration register specified by Addres= s, performs a
>
> +=C2=A0 bitwise AND between the read result and the value specified by= AndData,
> and
>
> +=C2=A0 writes the result to the 8-bit PCI configuration register spec= ified by
>
> +=C2=A0 Address. The value written to the PCI configuration register i= s returned.
>
> +=C2=A0 This function must guarantee that all PCI read and write opera= tions are
>
> +=C2=A0 serialized. Extra left bits in AndData are stripped.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If StartBit is greater than 7, then ASSERT().
>
> +=C2=A0 If EndBit is greater than 7, then ASSERT().
>
> +=C2=A0 If EndBit is less than StartBit, then ASSERT().
>
> +=C2=A0 If AndData is larger than the bitmask value range specified by= StartBit and
> EndBit, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address=C2=A0 =C2=A0The PCI configuration registe= r to write.
>
> +=C2=A0 @param=C2=A0 StartBit=C2=A0 The ordinal of the least significa= nt bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..7.
>
> +=C2=A0 @param=C2=A0 EndBit=C2=A0 =C2=A0 The ordinal of the most signi= ficant bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..7.
>
> +=C2=A0 @param=C2=A0 AndData=C2=A0 =C2=A0The value to AND with the PCI= configuration register.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT8
>
> +EFIAPI
>
> +PciExpressBitFieldAnd8 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0AndData
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 ASSERT_INVALID_PCI_ADDRESS (Address);
>
> +=C2=A0 return MmioBitFieldAnd8 (
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(UINTN) GetPciExpressBaseAdd= ress () + Address,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0AndData
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0);
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Reads a bit field in an 8-bit port, performs a bitwise AND fol= lowed by a
>
> +=C2=A0 bitwise OR, and writes the result back to the bit field in the=
>
> +=C2=A0 8-bit port.
>
> +
>
> +=C2=A0 Reads the 8-bit PCI configuration register specified by Addres= s, performs a
>
> +=C2=A0 bitwise AND followed by a bitwise OR between the read result a= nd
>
> +=C2=A0 the value specified by AndData, and writes the result to the 8= -bit PCI
>
> +=C2=A0 configuration register specified by Address. The value written= to the PCI
>
> +=C2=A0 configuration register is returned. This function must guarant= ee that all PCI
>
> +=C2=A0 read and write operations are serialized. Extra left bits in b= oth AndData and
>
> +=C2=A0 OrData are stripped.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If StartBit is greater than 7, then ASSERT().
>
> +=C2=A0 If EndBit is greater than 7, then ASSERT().
>
> +=C2=A0 If EndBit is less than StartBit, then ASSERT().
>
> +=C2=A0 If AndData is larger than the bitmask value range specified by= StartBit and
> EndBit, then ASSERT().
>
> +=C2=A0 If OrData is larger than the bitmask value range specified by = StartBit and
> EndBit, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address=C2=A0 =C2=A0The PCI configuration registe= r to write.
>
> +=C2=A0 @param=C2=A0 StartBit=C2=A0 The ordinal of the least significa= nt bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..7.
>
> +=C2=A0 @param=C2=A0 EndBit=C2=A0 =C2=A0 The ordinal of the most signi= ficant bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..7.
>
> +=C2=A0 @param=C2=A0 AndData=C2=A0 =C2=A0The value to AND with the PCI= configuration register.
>
> +=C2=A0 @param=C2=A0 OrData=C2=A0 =C2=A0 The value to OR with the resu= lt of the AND operation.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT8
>
> +EFIAPI
>
> +PciExpressBitFieldAndThenOr8 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0AndData,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0OrData
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 ASSERT_INVALID_PCI_ADDRESS (Address);
>
> +=C2=A0 return MmioBitFieldAndThenOr8 (
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(UINTN) GetPciExpressBaseAdd= ress () + Address,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0AndData,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0OrData
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0);
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Reads a 16-bit PCI configuration register.
>
> +
>
> +=C2=A0 Reads and returns the 16-bit PCI configuration register specif= ied by
> Address.
>
> +=C2=A0 This function must guarantee that all PCI read and write opera= tions are
>
> +=C2=A0 serialized.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 16-bit boundary, then ASSERT().=
>
> +
>
> +=C2=A0 @param=C2=A0 Address The address that encodes the PCI Bus, Dev= ice, Function
> and
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Regist= er.
>
> +
>
> +=C2=A0 @return The read value from the PCI configuration register. >
> +
>
> +**/
>
> +UINT16
>
> +EFIAPI
>
> +PciExpressRead16 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 ASSERT_INVALID_PCI_ADDRESS (Address);
>
> +=C2=A0 return MmioRead16 ((UINTN) GetPciExpressBaseAddress () + Addre= ss);
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Writes a 16-bit PCI configuration register.
>
> +
>
> +=C2=A0 Writes the 16-bit PCI configuration register specified by Addr= ess with the
>
> +=C2=A0 value specified by Value. Value is returned. This function mus= t guarantee
>
> +=C2=A0 that all PCI read and write operations are serialized.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 16-bit boundary, then ASSERT().=
>
> +
>
> +=C2=A0 @param=C2=A0 Address The address that encodes the PCI Bus, Dev= ice, Function
> and
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Regist= er.
>
> +=C2=A0 @param=C2=A0 Value=C2=A0 =C2=A0The value to write.
>
> +
>
> +=C2=A0 @return The value written to the PCI configuration register. >
> +
>
> +**/
>
> +UINT16
>
> +EFIAPI
>
> +PciExpressWrite16 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT16=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Value
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 ASSERT_INVALID_PCI_ADDRESS (Address);
>
> +=C2=A0 return MmioWrite16 ((UINTN) GetPciExpressBaseAddress () + Addr= ess,
> Value);
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Performs a bitwise OR of a 16-bit PCI configuration register w= ith
>
> +=C2=A0 a 16-bit value.
>
> +
>
> +=C2=A0 Reads the 16-bit PCI configuration register specified by Addre= ss, performs
> a
>
> +=C2=A0 bitwise OR between the read result and the value specified by<= br> >
> +=C2=A0 OrData, and writes the result to the 16-bit PCI configuration = register
>
> +=C2=A0 specified by Address. The value written to the PCI configurati= on register is
>
> +=C2=A0 returned. This function must guarantee that all PCI read and w= rite
> operations
>
> +=C2=A0 are serialized.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 16-bit boundary, then ASSERT().=
>
> +
>
> +=C2=A0 @param=C2=A0 Address The address that encodes the PCI Bus, Dev= ice, Function
> and
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Regist= er.
>
> +=C2=A0 @param=C2=A0 OrData=C2=A0 The value to OR with the PCI configu= ration register.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT16
>
> +EFIAPI
>
> +PciExpressOr16 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT16=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 OrData
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 ASSERT_INVALID_PCI_ADDRESS (Address);
>
> +=C2=A0 return MmioOr16 ((UINTN) GetPciExpressBaseAddress () + Address= ,
> OrData);
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Performs a bitwise AND of a 16-bit PCI configuration register = with a 16-bit
>
> +=C2=A0 value.
>
> +
>
> +=C2=A0 Reads the 16-bit PCI configuration register specified by Addre= ss, performs
> a
>
> +=C2=A0 bitwise AND between the read result and the value specified by= AndData,
> and
>
> +=C2=A0 writes the result to the 16-bit PCI configuration register spe= cified by
>
> +=C2=A0 Address. The value written to the PCI configuration register i= s returned.
>
> +=C2=A0 This function must guarantee that all PCI read and write opera= tions are
>
> +=C2=A0 serialized.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 16-bit boundary, then ASSERT().=
>
> +
>
> +=C2=A0 @param=C2=A0 Address The address that encodes the PCI Bus, Dev= ice, Function
> and
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Regist= er.
>
> +=C2=A0 @param=C2=A0 AndData The value to AND with the PCI configurati= on register.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT16
>
> +EFIAPI
>
> +PciExpressAnd16 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT16=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 AndData
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 ASSERT_INVALID_PCI_ADDRESS (Address);
>
> +=C2=A0 return MmioAnd16 ((UINTN) GetPciExpressBaseAddress () + Addres= s,
> AndData);
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Performs a bitwise AND of a 16-bit PCI configuration register = with a 16-bit
>
> +=C2=A0 value, followed a=C2=A0 bitwise OR with another 16-bit value.<= br> >
> +
>
> +=C2=A0 Reads the 16-bit PCI configuration register specified by Addre= ss, performs
> a
>
> +=C2=A0 bitwise AND between the read result and the value specified by= AndData,
>
> +=C2=A0 performs a bitwise OR between the result of the AND operation = and
>
> +=C2=A0 the value specified by OrData, and writes the result to the 16= -bit PCI
>
> +=C2=A0 configuration register specified by Address. The value written= to the PCI
>
> +=C2=A0 configuration register is returned. This function must guarant= ee that all PCI
>
> +=C2=A0 read and write operations are serialized.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 16-bit boundary, then ASSERT().=
>
> +
>
> +=C2=A0 @param=C2=A0 Address The address that encodes the PCI Bus, Dev= ice, Function
> and
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Regist= er.
>
> +=C2=A0 @param=C2=A0 AndData The value to AND with the PCI configurati= on register.
>
> +=C2=A0 @param=C2=A0 OrData=C2=A0 The value to OR with the result of t= he AND operation.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT16
>
> +EFIAPI
>
> +PciExpressAndThenOr16 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT16=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 AndData,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT16=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 OrData
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 ASSERT_INVALID_PCI_ADDRESS (Address);
>
> +=C2=A0 return MmioAndThenOr16 (
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(UINTN) GetPciExpressBaseAdd= ress () + Address,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0AndData,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0OrData
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0);
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Reads a bit field of a PCI configuration register.
>
> +
>
> +=C2=A0 Reads the bit field in a 16-bit PCI configuration register. Th= e bit field is
>
> +=C2=A0 specified by the StartBit and the EndBit. The value of the bit= field is
>
> +=C2=A0 returned.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 16-bit boundary, then ASSERT().=
>
> +=C2=A0 If StartBit is greater than 15, then ASSERT().
>
> +=C2=A0 If EndBit is greater than 15, then ASSERT().
>
> +=C2=A0 If EndBit is less than StartBit, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address=C2=A0 =C2=A0The PCI configuration registe= r to read.
>
> +=C2=A0 @param=C2=A0 StartBit=C2=A0 The ordinal of the least significa= nt bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..15.
>
> +=C2=A0 @param=C2=A0 EndBit=C2=A0 =C2=A0 The ordinal of the most signi= ficant bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..15.
>
> +
>
> +=C2=A0 @return The value of the bit field read from the PCI configura= tion register.
>
> +
>
> +**/
>
> +UINT16
>
> +EFIAPI
>
> +PciExpressBitFieldRead16 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 ASSERT_INVALID_PCI_ADDRESS (Address);
>
> +=C2=A0 return MmioBitFieldRead16 (
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(UINTN) GetPciExpressBaseAdd= ress () + Address,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0);
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Writes a bit field to a PCI configuration register.
>
> +
>
> +=C2=A0 Writes Value to the bit field of the PCI configuration registe= r. The bit
>
> +=C2=A0 field is specified by the StartBit and the EndBit. All other b= its in the
>
> +=C2=A0 destination PCI configuration register are preserved. The new = value of the
>
> +=C2=A0 16-bit register is returned.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 16-bit boundary, then ASSERT().=
>
> +=C2=A0 If StartBit is greater than 15, then ASSERT().
>
> +=C2=A0 If EndBit is greater than 15, then ASSERT().
>
> +=C2=A0 If EndBit is less than StartBit, then ASSERT().
>
> +=C2=A0 If Value is larger than the bitmask value range specified by S= tartBit and
> EndBit, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address=C2=A0 =C2=A0The PCI configuration registe= r to write.
>
> +=C2=A0 @param=C2=A0 StartBit=C2=A0 The ordinal of the least significa= nt bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..15.
>
> +=C2=A0 @param=C2=A0 EndBit=C2=A0 =C2=A0 The ordinal of the most signi= ficant bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..15.
>
> +=C2=A0 @param=C2=A0 Value=C2=A0 =C2=A0 =C2=A0The new value of the bit= field.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT16
>
> +EFIAPI
>
> +PciExpressBitFieldWrite16 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT16=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Value
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 ASSERT_INVALID_PCI_ADDRESS (Address);
>
> +=C2=A0 return MmioBitFieldWrite16 (
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(UINTN) GetPciExpressBaseAdd= ress () + Address,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Value
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0);
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Reads a bit field in a 16-bit PCI configuration, performs a bi= twise OR, and
>
> +=C2=A0 writes the result back to the bit field in the 16-bit port. >
> +
>
> +=C2=A0 Reads the 16-bit PCI configuration register specified by Addre= ss, performs
> a
>
> +=C2=A0 bitwise OR between the read result and the value specified by<= br> >
> +=C2=A0 OrData, and writes the result to the 16-bit PCI configuration = register
>
> +=C2=A0 specified by Address. The value written to the PCI configurati= on register is
>
> +=C2=A0 returned. This function must guarantee that all PCI read and w= rite
> operations
>
> +=C2=A0 are serialized. Extra left bits in OrData are stripped.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 16-bit boundary, then ASSERT().=
>
> +=C2=A0 If StartBit is greater than 15, then ASSERT().
>
> +=C2=A0 If EndBit is greater than 15, then ASSERT().
>
> +=C2=A0 If EndBit is less than StartBit, then ASSERT().
>
> +=C2=A0 If OrData is larger than the bitmask value range specified by = StartBit and
> EndBit, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address=C2=A0 =C2=A0The PCI configuration registe= r to write.
>
> +=C2=A0 @param=C2=A0 StartBit=C2=A0 The ordinal of the least significa= nt bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..15.
>
> +=C2=A0 @param=C2=A0 EndBit=C2=A0 =C2=A0 The ordinal of the most signi= ficant bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..15.
>
> +=C2=A0 @param=C2=A0 OrData=C2=A0 =C2=A0 The value to OR with the PCI = configuration register.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT16
>
> +EFIAPI
>
> +PciExpressBitFieldOr16 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT16=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 OrData
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 ASSERT_INVALID_PCI_ADDRESS (Address);
>
> +=C2=A0 return MmioBitFieldOr16 (
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(UINTN) GetPciExpressBaseAdd= ress () + Address,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0OrData
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0);
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Reads a bit field in a 16-bit PCI configuration register, perf= orms a bitwise
>
> +=C2=A0 AND, and writes the result back to the bit field in the 16-bit= register.
>
> +
>
> +=C2=A0 Reads the 16-bit PCI configuration register specified by Addre= ss, performs
> a
>
> +=C2=A0 bitwise AND between the read result and the value specified by= AndData,
> and
>
> +=C2=A0 writes the result to the 16-bit PCI configuration register spe= cified by
>
> +=C2=A0 Address. The value written to the PCI configuration register i= s returned.
>
> +=C2=A0 This function must guarantee that all PCI read and write opera= tions are
>
> +=C2=A0 serialized. Extra left bits in AndData are stripped.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 16-bit boundary, then ASSERT().=
>
> +=C2=A0 If StartBit is greater than 15, then ASSERT().
>
> +=C2=A0 If EndBit is greater than 15, then ASSERT().
>
> +=C2=A0 If EndBit is less than StartBit, then ASSERT().
>
> +=C2=A0 If AndData is larger than the bitmask value range specified by= StartBit and
> EndBit, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address=C2=A0 =C2=A0The PCI configuration registe= r to write.
>
> +=C2=A0 @param=C2=A0 StartBit=C2=A0 The ordinal of the least significa= nt bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..15.
>
> +=C2=A0 @param=C2=A0 EndBit=C2=A0 =C2=A0 The ordinal of the most signi= ficant bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..15.
>
> +=C2=A0 @param=C2=A0 AndData=C2=A0 =C2=A0The value to AND with the PCI= configuration register.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT16
>
> +EFIAPI
>
> +PciExpressBitFieldAnd16 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT16=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 AndData
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 ASSERT_INVALID_PCI_ADDRESS (Address);
>
> +=C2=A0 return MmioBitFieldAnd16 (
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(UINTN) GetPciExpressBaseAdd= ress () + Address,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0AndData
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0);
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Reads a bit field in a 16-bit port, performs a bitwise AND fol= lowed by a
>
> +=C2=A0 bitwise OR, and writes the result back to the bit field in the=
>
> +=C2=A0 16-bit port.
>
> +
>
> +=C2=A0 Reads the 16-bit PCI configuration register specified by Addre= ss, performs
> a
>
> +=C2=A0 bitwise AND followed by a bitwise OR between the read result a= nd
>
> +=C2=A0 the value specified by AndData, and writes the result to the 1= 6-bit PCI
>
> +=C2=A0 configuration register specified by Address. The value written= to the PCI
>
> +=C2=A0 configuration register is returned. This function must guarant= ee that all PCI
>
> +=C2=A0 read and write operations are serialized. Extra left bits in b= oth AndData and
>
> +=C2=A0 OrData are stripped.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 16-bit boundary, then ASSERT().=
>
> +=C2=A0 If StartBit is greater than 15, then ASSERT().
>
> +=C2=A0 If EndBit is greater than 15, then ASSERT().
>
> +=C2=A0 If EndBit is less than StartBit, then ASSERT().
>
> +=C2=A0 If AndData is larger than the bitmask value range specified by= StartBit and
> EndBit, then ASSERT().
>
> +=C2=A0 If OrData is larger than the bitmask value range specified by = StartBit and
> EndBit, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address=C2=A0 =C2=A0The PCI configuration registe= r to write.
>
> +=C2=A0 @param=C2=A0 StartBit=C2=A0 The ordinal of the least significa= nt bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..15.
>
> +=C2=A0 @param=C2=A0 EndBit=C2=A0 =C2=A0 The ordinal of the most signi= ficant bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..15.
>
> +=C2=A0 @param=C2=A0 AndData=C2=A0 =C2=A0The value to AND with the PCI= configuration register.
>
> +=C2=A0 @param=C2=A0 OrData=C2=A0 =C2=A0 The value to OR with the resu= lt of the AND operation.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT16
>
> +EFIAPI
>
> +PciExpressBitFieldAndThenOr16 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT16=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 AndData,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT16=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 OrData
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 ASSERT_INVALID_PCI_ADDRESS (Address);
>
> +=C2=A0 return MmioBitFieldAndThenOr16 (
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(UINTN) GetPciExpressBaseAdd= ress () + Address,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0AndData,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0OrData
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0);
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Reads a 32-bit PCI configuration register.
>
> +
>
> +=C2=A0 Reads and returns the 32-bit PCI configuration register specif= ied by
> Address.
>
> +=C2=A0 This function must guarantee that all PCI read and write opera= tions are
>
> +=C2=A0 serialized.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 32-bit boundary, then ASSERT().=
>
> +
>
> +=C2=A0 @param=C2=A0 Address The address that encodes the PCI Bus, Dev= ice, Function
> and
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Regist= er.
>
> +
>
> +=C2=A0 @return The read value from the PCI configuration register. >
> +
>
> +**/
>
> +UINT32
>
> +EFIAPI
>
> +PciExpressRead32 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 ASSERT_INVALID_PCI_ADDRESS (Address);
>
> +=C2=A0 return MmioRead32 ((UINTN) GetPciExpressBaseAddress () + Addre= ss);
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Writes a 32-bit PCI configuration register.
>
> +
>
> +=C2=A0 Writes the 32-bit PCI configuration register specified by Addr= ess with the
>
> +=C2=A0 value specified by Value. Value is returned. This function mus= t guarantee
>
> +=C2=A0 that all PCI read and write operations are serialized.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 32-bit boundary, then ASSERT().=
>
> +
>
> +=C2=A0 @param=C2=A0 Address The address that encodes the PCI Bus, Dev= ice, Function
> and
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Regist= er.
>
> +=C2=A0 @param=C2=A0 Value=C2=A0 =C2=A0The value to write.
>
> +
>
> +=C2=A0 @return The value written to the PCI configuration register. >
> +
>
> +**/
>
> +UINT32
>
> +EFIAPI
>
> +PciExpressWrite32 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Value
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 ASSERT_INVALID_PCI_ADDRESS (Address);
>
> +=C2=A0 return MmioWrite32 ((UINTN) GetPciExpressBaseAddress () + Addr= ess,
> Value);
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Performs a bitwise OR of a 32-bit PCI configuration register w= ith
>
> +=C2=A0 a 32-bit value.
>
> +
>
> +=C2=A0 Reads the 32-bit PCI configuration register specified by Addre= ss, performs
> a
>
> +=C2=A0 bitwise OR between the read result and the value specified by<= br> >
> +=C2=A0 OrData, and writes the result to the 32-bit PCI configuration = register
>
> +=C2=A0 specified by Address. The value written to the PCI configurati= on register is
>
> +=C2=A0 returned. This function must guarantee that all PCI read and w= rite
> operations
>
> +=C2=A0 are serialized.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 32-bit boundary, then ASSERT().=
>
> +
>
> +=C2=A0 @param=C2=A0 Address The address that encodes the PCI Bus, Dev= ice, Function
> and
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Regist= er.
>
> +=C2=A0 @param=C2=A0 OrData=C2=A0 The value to OR with the PCI configu= ration register.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT32
>
> +EFIAPI
>
> +PciExpressOr32 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 OrData
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 ASSERT_INVALID_PCI_ADDRESS (Address);
>
> +=C2=A0 return MmioOr32 ((UINTN) GetPciExpressBaseAddress () + Address= ,
> OrData);
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Performs a bitwise AND of a 32-bit PCI configuration register = with a 32-bit
>
> +=C2=A0 value.
>
> +
>
> +=C2=A0 Reads the 32-bit PCI configuration register specified by Addre= ss, performs
> a
>
> +=C2=A0 bitwise AND between the read result and the value specified by= AndData,
> and
>
> +=C2=A0 writes the result to the 32-bit PCI configuration register spe= cified by
>
> +=C2=A0 Address. The value written to the PCI configuration register i= s returned.
>
> +=C2=A0 This function must guarantee that all PCI read and write opera= tions are
>
> +=C2=A0 serialized.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 32-bit boundary, then ASSERT().=
>
> +
>
> +=C2=A0 @param=C2=A0 Address The address that encodes the PCI Bus, Dev= ice, Function
> and
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Regist= er.
>
> +=C2=A0 @param=C2=A0 AndData The value to AND with the PCI configurati= on register.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT32
>
> +EFIAPI
>
> +PciExpressAnd32 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 AndData
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 ASSERT_INVALID_PCI_ADDRESS (Address);
>
> +=C2=A0 return MmioAnd32 ((UINTN) GetPciExpressBaseAddress () + Addres= s,
> AndData);
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Performs a bitwise AND of a 32-bit PCI configuration register = with a 32-bit
>
> +=C2=A0 value, followed a=C2=A0 bitwise OR with another 32-bit value.<= br> >
> +
>
> +=C2=A0 Reads the 32-bit PCI configuration register specified by Addre= ss, performs
> a
>
> +=C2=A0 bitwise AND between the read result and the value specified by= AndData,
>
> +=C2=A0 performs a bitwise OR between the result of the AND operation = and
>
> +=C2=A0 the value specified by OrData, and writes the result to the 32= -bit PCI
>
> +=C2=A0 configuration register specified by Address. The value written= to the PCI
>
> +=C2=A0 configuration register is returned. This function must guarant= ee that all PCI
>
> +=C2=A0 read and write operations are serialized.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 32-bit boundary, then ASSERT().=
>
> +
>
> +=C2=A0 @param=C2=A0 Address The address that encodes the PCI Bus, Dev= ice, Function
> and
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Regist= er.
>
> +=C2=A0 @param=C2=A0 AndData The value to AND with the PCI configurati= on register.
>
> +=C2=A0 @param=C2=A0 OrData=C2=A0 The value to OR with the result of t= he AND operation.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT32
>
> +EFIAPI
>
> +PciExpressAndThenOr32 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 AndData,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 OrData
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 ASSERT_INVALID_PCI_ADDRESS (Address);
>
> +=C2=A0 return MmioAndThenOr32 (
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(UINTN) GetPciExpressBaseAdd= ress () + Address,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0AndData,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0OrData
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0);
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Reads a bit field of a PCI configuration register.
>
> +
>
> +=C2=A0 Reads the bit field in a 32-bit PCI configuration register. Th= e bit field is
>
> +=C2=A0 specified by the StartBit and the EndBit. The value of the bit= field is
>
> +=C2=A0 returned.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 32-bit boundary, then ASSERT().=
>
> +=C2=A0 If StartBit is greater than 31, then ASSERT().
>
> +=C2=A0 If EndBit is greater than 31, then ASSERT().
>
> +=C2=A0 If EndBit is less than StartBit, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address=C2=A0 =C2=A0The PCI configuration registe= r to read.
>
> +=C2=A0 @param=C2=A0 StartBit=C2=A0 The ordinal of the least significa= nt bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..31.
>
> +=C2=A0 @param=C2=A0 EndBit=C2=A0 =C2=A0 The ordinal of the most signi= ficant bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..31.
>
> +
>
> +=C2=A0 @return The value of the bit field read from the PCI configura= tion register.
>
> +
>
> +**/
>
> +UINT32
>
> +EFIAPI
>
> +PciExpressBitFieldRead32 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 ASSERT_INVALID_PCI_ADDRESS (Address);
>
> +=C2=A0 return MmioBitFieldRead32 (
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(UINTN) GetPciExpressBaseAdd= ress () + Address,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0);
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Writes a bit field to a PCI configuration register.
>
> +
>
> +=C2=A0 Writes Value to the bit field of the PCI configuration registe= r. The bit
>
> +=C2=A0 field is specified by the StartBit and the EndBit. All other b= its in the
>
> +=C2=A0 destination PCI configuration register are preserved. The new = value of the
>
> +=C2=A0 32-bit register is returned.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 32-bit boundary, then ASSERT().=
>
> +=C2=A0 If StartBit is greater than 31, then ASSERT().
>
> +=C2=A0 If EndBit is greater than 31, then ASSERT().
>
> +=C2=A0 If EndBit is less than StartBit, then ASSERT().
>
> +=C2=A0 If Value is larger than the bitmask value range specified by S= tartBit and
> EndBit, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address=C2=A0 =C2=A0The PCI configuration registe= r to write.
>
> +=C2=A0 @param=C2=A0 StartBit=C2=A0 The ordinal of the least significa= nt bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..31.
>
> +=C2=A0 @param=C2=A0 EndBit=C2=A0 =C2=A0 The ordinal of the most signi= ficant bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..31.
>
> +=C2=A0 @param=C2=A0 Value=C2=A0 =C2=A0 =C2=A0The new value of the bit= field.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT32
>
> +EFIAPI
>
> +PciExpressBitFieldWrite32 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Value
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 ASSERT_INVALID_PCI_ADDRESS (Address);
>
> +=C2=A0 return MmioBitFieldWrite32 (
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(UINTN) GetPciExpressBaseAdd= ress () + Address,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Value
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0);
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Reads a bit field in a 32-bit PCI configuration, performs a bi= twise OR, and
>
> +=C2=A0 writes the result back to the bit field in the 32-bit port. >
> +
>
> +=C2=A0 Reads the 32-bit PCI configuration register specified by Addre= ss, performs
> a
>
> +=C2=A0 bitwise OR between the read result and the value specified by<= br> >
> +=C2=A0 OrData, and writes the result to the 32-bit PCI configuration = register
>
> +=C2=A0 specified by Address. The value written to the PCI configurati= on register is
>
> +=C2=A0 returned. This function must guarantee that all PCI read and w= rite
> operations
>
> +=C2=A0 are serialized. Extra left bits in OrData are stripped.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 32-bit boundary, then ASSERT().=
>
> +=C2=A0 If StartBit is greater than 31, then ASSERT().
>
> +=C2=A0 If EndBit is greater than 31, then ASSERT().
>
> +=C2=A0 If EndBit is less than StartBit, then ASSERT().
>
> +=C2=A0 If OrData is larger than the bitmask value range specified by = StartBit and
> EndBit, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address=C2=A0 =C2=A0The PCI configuration registe= r to write.
>
> +=C2=A0 @param=C2=A0 StartBit=C2=A0 The ordinal of the least significa= nt bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..31.
>
> +=C2=A0 @param=C2=A0 EndBit=C2=A0 =C2=A0 The ordinal of the most signi= ficant bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..31.
>
> +=C2=A0 @param=C2=A0 OrData=C2=A0 =C2=A0 The value to OR with the PCI = configuration register.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT32
>
> +EFIAPI
>
> +PciExpressBitFieldOr32 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 OrData
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 ASSERT_INVALID_PCI_ADDRESS (Address);
>
> +=C2=A0 return MmioBitFieldOr32 (
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(UINTN) GetPciExpressBaseAdd= ress () + Address,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0OrData
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0);
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Reads a bit field in a 32-bit PCI configuration register, perf= orms a bitwise
>
> +=C2=A0 AND, and writes the result back to the bit field in the 32-bit= register.
>
> +
>
> +=C2=A0 Reads the 32-bit PCI configuration register specified by Addre= ss, performs
> a
>
> +=C2=A0 bitwise AND between the read result and the value specified by= AndData,
> and
>
> +=C2=A0 writes the result to the 32-bit PCI configuration register spe= cified by
>
> +=C2=A0 Address. The value written to the PCI configuration register i= s returned.
>
> +=C2=A0 This function must guarantee that all PCI read and write opera= tions are
>
> +=C2=A0 serialized. Extra left bits in AndData are stripped.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 32-bit boundary, then ASSERT().=
>
> +=C2=A0 If StartBit is greater than 31, then ASSERT().
>
> +=C2=A0 If EndBit is greater than 31, then ASSERT().
>
> +=C2=A0 If EndBit is less than StartBit, then ASSERT().
>
> +=C2=A0 If AndData is larger than the bitmask value range specified by= StartBit and
> EndBit, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address=C2=A0 =C2=A0The PCI configuration registe= r to write.
>
> +=C2=A0 @param=C2=A0 StartBit=C2=A0 The ordinal of the least significa= nt bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..31.
>
> +=C2=A0 @param=C2=A0 EndBit=C2=A0 =C2=A0 The ordinal of the most signi= ficant bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..31.
>
> +=C2=A0 @param=C2=A0 AndData=C2=A0 =C2=A0The value to AND with the PCI= configuration register.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT32
>
> +EFIAPI
>
> +PciExpressBitFieldAnd32 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 AndData
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 ASSERT_INVALID_PCI_ADDRESS (Address);
>
> +=C2=A0 return MmioBitFieldAnd32 (
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(UINTN) GetPciExpressBaseAdd= ress () + Address,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0AndData
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0);
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Reads a bit field in a 32-bit port, performs a bitwise AND fol= lowed by a
>
> +=C2=A0 bitwise OR, and writes the result back to the bit field in the=
>
> +=C2=A0 32-bit port.
>
> +
>
> +=C2=A0 Reads the 32-bit PCI configuration register specified by Addre= ss, performs
> a
>
> +=C2=A0 bitwise AND followed by a bitwise OR between the read result a= nd
>
> +=C2=A0 the value specified by AndData, and writes the result to the 3= 2-bit PCI
>
> +=C2=A0 configuration register specified by Address. The value written= to the PCI
>
> +=C2=A0 configuration register is returned. This function must guarant= ee that all PCI
>
> +=C2=A0 read and write operations are serialized. Extra left bits in b= oth AndData and
>
> +=C2=A0 OrData are stripped.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 32-bit boundary, then ASSERT().=
>
> +=C2=A0 If StartBit is greater than 31, then ASSERT().
>
> +=C2=A0 If EndBit is greater than 31, then ASSERT().
>
> +=C2=A0 If EndBit is less than StartBit, then ASSERT().
>
> +=C2=A0 If AndData is larger than the bitmask value range specified by= StartBit and
> EndBit, then ASSERT().
>
> +=C2=A0 If OrData is larger than the bitmask value range specified by = StartBit and
> EndBit, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address=C2=A0 =C2=A0The PCI configuration registe= r to write.
>
> +=C2=A0 @param=C2=A0 StartBit=C2=A0 The ordinal of the least significa= nt bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..31.
>
> +=C2=A0 @param=C2=A0 EndBit=C2=A0 =C2=A0 The ordinal of the most signi= ficant bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..31.
>
> +=C2=A0 @param=C2=A0 AndData=C2=A0 =C2=A0The value to AND with the PCI= configuration register.
>
> +=C2=A0 @param=C2=A0 OrData=C2=A0 =C2=A0 The value to OR with the resu= lt of the AND operation.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT32
>
> +EFIAPI
>
> +PciExpressBitFieldAndThenOr32 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 AndData,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 OrData
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 ASSERT_INVALID_PCI_ADDRESS (Address);
>
> +=C2=A0 return MmioBitFieldAndThenOr32 (
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(UINTN) GetPciExpressBaseAdd= ress () + Address,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0AndData,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0OrData
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0);
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Reads a range of PCI configuration registers into a caller sup= plied buffer.
>
> +
>
> +=C2=A0 Reads the range of PCI configuration registers specified by St= artAddress
> and
>
> +=C2=A0 Size into the buffer specified by Buffer. This function only a= llows the PCI
>
> +=C2=A0 configuration registers from a single PCI function to be read.= Size is
>
> +=C2=A0 returned. When possible 32-bit PCI configuration read cycles a= re used to
> read
>
> +=C2=A0 from StartAdress to StartAddress + Size. Due to alignment rest= rictions, 8-
> bit
>
> +=C2=A0 and 16-bit PCI configuration read cycles may be used at the be= ginning and
> the
>
> +=C2=A0 end of the range.
>
> +
>
> +=C2=A0 If StartAddress > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSER= T().
>
> +=C2=A0 If Size > 0 and Buffer is NULL, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 StartAddress=C2=A0 The starting address that enco= des the PCI Bus,
> Device,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 Function and Register.
>
> +=C2=A0 @param=C2=A0 Size=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 The size i= n bytes of the transfer.
>
> +=C2=A0 @param=C2=A0 Buffer=C2=A0 =C2=A0 =C2=A0 =C2=A0 The pointer to = a buffer receiving the data read.
>
> +
>
> +=C2=A0 @return Size read data from StartAddress.
>
> +
>
> +**/
>
> +UINTN
>
> +EFIAPI
>
> +PciExpressReadBuffer (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartAddress,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Size,
>
> +=C2=A0 OUT=C2=A0 =C2=A0 =C2=A0VOID=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 *Buffer
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 UINTN=C2=A0 =C2=A0ReturnValue;
>
> +
>
> +=C2=A0 ASSERT_INVALID_PCI_ADDRESS (StartAddress);
>
> +=C2=A0 ASSERT (((StartAddress & 0xFFF) + Size) <=3D 0x1000); >
> +
>
> +=C2=A0 if (Size =3D=3D 0) {
>
> +=C2=A0 =C2=A0 return Size;
>
> +=C2=A0 }
>
> +
>
> +=C2=A0 ASSERT (Buffer !=3D NULL);
>
> +
>
> +=C2=A0 //
>
> +=C2=A0 // Save Size for return
>
> +=C2=A0 //
>
> +=C2=A0 ReturnValue =3D Size;
>
> +
>
> +=C2=A0 if ((StartAddress & 1) !=3D 0) {
>
> +=C2=A0 =C2=A0 //
>
> +=C2=A0 =C2=A0 // Read a byte if StartAddress is byte aligned
>
> +=C2=A0 =C2=A0 //
>
> +=C2=A0 =C2=A0 *(volatile UINT8 *)Buffer =3D PciExpressRead8 (StartAdd= ress);
>
> +=C2=A0 =C2=A0 StartAddress +=3D sizeof (UINT8);
>
> +=C2=A0 =C2=A0 Size -=3D sizeof (UINT8);
>
> +=C2=A0 =C2=A0 Buffer =3D (UINT8*)Buffer + 1;
>
> +=C2=A0 }
>
> +
>
> +=C2=A0 if (Size >=3D sizeof (UINT16) && (StartAddress &= ; 2) !=3D 0) {
>
> +=C2=A0 =C2=A0 //
>
> +=C2=A0 =C2=A0 // Read a word if StartAddress is word aligned
>
> +=C2=A0 =C2=A0 //
>
> +=C2=A0 =C2=A0 WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpres= sRead16
> (StartAddress));
>
> +
>
> +=C2=A0 =C2=A0 StartAddress +=3D sizeof (UINT16);
>
> +=C2=A0 =C2=A0 Size -=3D sizeof (UINT16);
>
> +=C2=A0 =C2=A0 Buffer =3D (UINT16*)Buffer + 1;
>
> +=C2=A0 }
>
> +
>
> +=C2=A0 while (Size >=3D sizeof (UINT32)) {
>
> +=C2=A0 =C2=A0 //
>
> +=C2=A0 =C2=A0 // Read as many double words as possible
>
> +=C2=A0 =C2=A0 //
>
> +=C2=A0 =C2=A0 WriteUnaligned32 ((UINT32 *) Buffer, (UINT32) PciExpres= sRead32
> (StartAddress));
>
> +
>
> +=C2=A0 =C2=A0 StartAddress +=3D sizeof (UINT32);
>
> +=C2=A0 =C2=A0 Size -=3D sizeof (UINT32);
>
> +=C2=A0 =C2=A0 Buffer =3D (UINT32*)Buffer + 1;
>
> +=C2=A0 }
>
> +
>
> +=C2=A0 if (Size >=3D sizeof (UINT16)) {
>
> +=C2=A0 =C2=A0 //
>
> +=C2=A0 =C2=A0 // Read the last remaining word if exist
>
> +=C2=A0 =C2=A0 //
>
> +=C2=A0 =C2=A0 WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpres= sRead16
> (StartAddress));
>
> +=C2=A0 =C2=A0 StartAddress +=3D sizeof (UINT16);
>
> +=C2=A0 =C2=A0 Size -=3D sizeof (UINT16);
>
> +=C2=A0 =C2=A0 Buffer =3D (UINT16*)Buffer + 1;
>
> +=C2=A0 }
>
> +
>
> +=C2=A0 if (Size >=3D sizeof (UINT8)) {
>
> +=C2=A0 =C2=A0 //
>
> +=C2=A0 =C2=A0 // Read the last remaining byte if exist
>
> +=C2=A0 =C2=A0 //
>
> +=C2=A0 =C2=A0 *(volatile UINT8 *)Buffer =3D PciExpressRead8 (StartAdd= ress);
>
> +=C2=A0 }
>
> +
>
> +=C2=A0 return ReturnValue;
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Copies the data in a caller supplied buffer to a specified ran= ge of PCI
>
> +=C2=A0 configuration space.
>
> +
>
> +=C2=A0 Writes the range of PCI configuration registers specified by S= tartAddress
> and
>
> +=C2=A0 Size from the buffer specified by Buffer. This function only a= llows the PCI
>
> +=C2=A0 configuration registers from a single PCI function to be writt= en. Size is
>
> +=C2=A0 returned. When possible 32-bit PCI configuration write cycles = are used to
>
> +=C2=A0 write from StartAdress to StartAddress + Size. Due to alignmen= t
> restrictions,
>
> +=C2=A0 8-bit and 16-bit PCI configuration write cycles may be used at= the beginning
>
> +=C2=A0 and the end of the range.
>
> +
>
> +=C2=A0 If StartAddress > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSER= T().
>
> +=C2=A0 If Size > 0 and Buffer is NULL, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 StartAddress=C2=A0 The starting address that enco= des the PCI Bus,
> Device,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 Function and Register.
>
> +=C2=A0 @param=C2=A0 Size=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 The size i= n bytes of the transfer.
>
> +=C2=A0 @param=C2=A0 Buffer=C2=A0 =C2=A0 =C2=A0 =C2=A0 The pointer to = a buffer containing the data to write.
>
> +
>
> +=C2=A0 @return Size written to StartAddress.
>
> +
>
> +**/
>
> +UINTN
>
> +EFIAPI
>
> +PciExpressWriteBuffer (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartAddress,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Size,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 VOID=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 *Buffer
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ReturnValue;
>
> +
>
> +=C2=A0 ASSERT_INVALID_PCI_ADDRESS (StartAddress);
>
> +=C2=A0 ASSERT (((StartAddress & 0xFFF) + Size) <=3D 0x1000); >
> +
>
> +=C2=A0 if (Size =3D=3D 0) {
>
> +=C2=A0 =C2=A0 return 0;
>
> +=C2=A0 }
>
> +
>
> +=C2=A0 ASSERT (Buffer !=3D NULL);
>
> +
>
> +=C2=A0 //
>
> +=C2=A0 // Save Size for return
>
> +=C2=A0 //
>
> +=C2=A0 ReturnValue =3D Size;
>
> +
>
> +=C2=A0 if ((StartAddress & 1) !=3D 0) {
>
> +=C2=A0 =C2=A0 //
>
> +=C2=A0 =C2=A0 // Write a byte if StartAddress is byte aligned
>
> +=C2=A0 =C2=A0 //
>
> +=C2=A0 =C2=A0 PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);
>
> +=C2=A0 =C2=A0 StartAddress +=3D sizeof (UINT8);
>
> +=C2=A0 =C2=A0 Size -=3D sizeof (UINT8);
>
> +=C2=A0 =C2=A0 Buffer =3D (UINT8*)Buffer + 1;
>
> +=C2=A0 }
>
> +
>
> +=C2=A0 if (Size >=3D sizeof (UINT16) && (StartAddress &= ; 2) !=3D 0) {
>
> +=C2=A0 =C2=A0 //
>
> +=C2=A0 =C2=A0 // Write a word if StartAddress is word aligned
>
> +=C2=A0 =C2=A0 //
>
> +=C2=A0 =C2=A0 PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT= 16*)Buffer));
>
> +=C2=A0 =C2=A0 StartAddress +=3D sizeof (UINT16);
>
> +=C2=A0 =C2=A0 Size -=3D sizeof (UINT16);
>
> +=C2=A0 =C2=A0 Buffer =3D (UINT16*)Buffer + 1;
>
> +=C2=A0 }
>
> +
>
> +=C2=A0 while (Size >=3D sizeof (UINT32)) {
>
> +=C2=A0 =C2=A0 //
>
> +=C2=A0 =C2=A0 // Write as many double words as possible
>
> +=C2=A0 =C2=A0 //
>
> +=C2=A0 =C2=A0 PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT= 32*)Buffer));
>
> +=C2=A0 =C2=A0 StartAddress +=3D sizeof (UINT32);
>
> +=C2=A0 =C2=A0 Size -=3D sizeof (UINT32);
>
> +=C2=A0 =C2=A0 Buffer =3D (UINT32*)Buffer + 1;
>
> +=C2=A0 }
>
> +
>
> +=C2=A0 if (Size >=3D sizeof (UINT16)) {
>
> +=C2=A0 =C2=A0 //
>
> +=C2=A0 =C2=A0 // Write the last remaining word if exist
>
> +=C2=A0 =C2=A0 //
>
> +=C2=A0 =C2=A0 PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT= 16*)Buffer));
>
> +=C2=A0 =C2=A0 StartAddress +=3D sizeof (UINT16);
>
> +=C2=A0 =C2=A0 Size -=3D sizeof (UINT16);
>
> +=C2=A0 =C2=A0 Buffer =3D (UINT16*)Buffer + 1;
>
> +=C2=A0 }
>
> +
>
> +=C2=A0 if (Size >=3D sizeof (UINT8)) {
>
> +=C2=A0 =C2=A0 //
>
> +=C2=A0 =C2=A0 // Write the last remaining byte if exist
>
> +=C2=A0 =C2=A0 //
>
> +=C2=A0 =C2=A0 PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);
>
> +=C2=A0 }
>
> +
>
> +=C2=A0 return ReturnValue;
>
> +}
>
> diff --git a/UefiPayloadPkg/Library/BasePciLibPciExpress/PciLib.c
> b/UefiPayloadPkg/Library/BasePciLibPciExpress/PciLib.c
> new file mode 100644
> index 000000000000..fba5914462c8
> --- /dev/null
> +++ b/UefiPayloadPkg/Library/BasePciLibPciExpress/PciLib.c
> @@ -0,0 +1,1302 @@
> +/** @file
>
> +=C2=A0 PCI Library functions that use the 256 MB PCI Express MMIO win= dow to
> perform PCI
>
> +=C2=A0 Configuration cycles. Layers on PCI Express Library.
>
> +
>
> +=C2=A0 Copyright (c) 2006 - 2018, Intel Corporation. All rights reser= ved.<BR>
>
> +=C2=A0 SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +
>
> +**/
>
> +
>
> +
>
> +#include <Base.h>
>
> +
>
> +#include <Library/PciLib.h>
>
> +#include <Library/PciExpressLib.h>
>
> +#include <Library/PciCf8Lib.h>
>
> +
>
> +#include <Pi/PiBootMode.h>
>
> +#include <Uefi/UefiBaseType.h>
>
> +#include <Uefi/UefiMultiPhase.h>
>
> +#include <Pi/PiHob.h>
>
> +
>
> +#include <Library/HobLib.h>
>
> +#include <Guid/AcpiBoardInfoGuid.h>
>
> +
>
> +STATIC BOOLEAN mMMCONFEnabled;
>
> +
>
> +/**
>
> +=C2=A0 Registers a PCI device so PCI configuration registers may be a= ccessed after
>
> +=C2=A0 SetVirtualAddressMap().
>
> +
>
> +=C2=A0 Registers the PCI device specified by Address so all the PCI c= onfiguration
> registers
>
> +=C2=A0 associated with that PCI device may be accessed after
> SetVirtualAddressMap() is called.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address The address that encodes the PCI Bus, Dev= ice, Function
> and
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Regist= er.
>
> +
>
> +=C2=A0 @retval RETURN_SUCCESS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0The PCI device was registered for runtime
> access.
>
> +=C2=A0 @retval RETURN_UNSUPPORTED=C2=A0 =C2=A0 =C2=A0 =C2=A0An attemp= t was made to call this
> function
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0after ExitBootServi= ces().
>
> +=C2=A0 @retval RETURN_UNSUPPORTED=C2=A0 =C2=A0 =C2=A0 =C2=A0The resou= rces required to access the
> PCI device
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0at runtime could no= t be mapped.
>
> +=C2=A0 @retval RETURN_OUT_OF_RESOURCES=C2=A0 There are not enough res= ources
> available to
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0complete the regist= ration.
>
> +
>
> +**/
>
> +RETURN_STATUS
>
> +EFIAPI
>
> +PciRegisterForRuntimeAccess (
>
> +=C2=A0 IN UINTN=C2=A0 Address
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 return PciExpressRegisterForRuntimeAccess (Address);
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Performs platform specific initialization required for the CPU= to access
>
> +=C2=A0 the MMCONF space.=C2=A0 This function does not initialize the = MMCONF itself.
>
> +
>
> +=C2=A0 @retval RETURN_SUCCESS=C2=A0 =C2=A0 =C2=A0 =C2=A0The platform = specific initialization succeeded.
>
> +=C2=A0 @retval RETURN_DEVICE_ERROR=C2=A0 The platform specific initia= lization could
> not be completed.
>
> +
>
> +**/
>
> +RETURN_STATUS
>
> +EFIAPI
>
> +PciLibInitialize (
>
> +=C2=A0 VOID
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 EFI_HOB_GUID_TYPE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*GuidHob; >
> +=C2=A0 ACPI_BOARD_INFO=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*AcpiB= oardInfoPtr;
>
> +
>
> +=C2=A0 //
>
> +=C2=A0 // Find the acpi board information guid hob
>
> +=C2=A0 //
>
> +=C2=A0 GuidHob =3D GetFirstGuidHob (&gUefiAcpiBoardInfoGuid);
>
> +=C2=A0 if (GuidHob =3D=3D NULL) {
>
> +=C2=A0 =C2=A0 return EFI_SUCCESS;
>
> +=C2=A0 }
>
> +=C2=A0 AcpiBoardInfoPtr =3D (ACPI_BOARD_INFO *)GET_GUID_HOB_DATA
> (GuidHob);
>
> +
>
> +=C2=A0 mMMCONFEnabled =3D AcpiBoardInfoPtr->PcieBaseAddress !=3D 0= &&
>
> +=C2=A0 =C2=A0 =C2=A0 AcpiBoardInfoPtr->PcieBaseSize !=3D 0;
>
> +=C2=A0 return EFI_SUCCESS;
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Reads an 8-bit PCI configuration register.
>
> +
>
> +=C2=A0 Reads and returns the 8-bit PCI configuration register specifi= ed by Address.
>
> +=C2=A0 This function must guarantee that all PCI read and write opera= tions are
>
> +=C2=A0 serialized.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address The address that encodes the PCI Bus, Dev= ice, Function
> and
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Regist= er.
>
> +
>
> +=C2=A0 @return The read value from the PCI configuration register. >
> +
>
> +**/
>
> +UINT8
>
> +EFIAPI
>
> +PciRead8 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 if (mMMCONFEnabled) {
>
> +=C2=A0 =C2=A0 return PciExpressRead8 (Address);
>
> +=C2=A0 } else {
>
> +=C2=A0 =C2=A0 return PciCf8Read8 (Address);
>
> +=C2=A0 }
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Writes an 8-bit PCI configuration register.
>
> +
>
> +=C2=A0 Writes the 8-bit PCI configuration register specified by Addre= ss with the
>
> +=C2=A0 value specified by Value. Value is returned. This function mus= t guarantee
>
> +=C2=A0 that all PCI read and write operations are serialized.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address The address that encodes the PCI Bus, Dev= ice, Function
> and
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Regist= er.
>
> +=C2=A0 @param=C2=A0 Value=C2=A0 =C2=A0The value to write.
>
> +
>
> +=C2=A0 @return The value written to the PCI configuration register. >
> +
>
> +**/
>
> +UINT8
>
> +EFIAPI
>
> +PciWrite8 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Value
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 if (mMMCONFEnabled) {
>
> +=C2=A0 =C2=A0 return PciExpressWrite8 (Address, Value);
>
> +=C2=A0 } else {
>
> +=C2=A0 =C2=A0 return PciCf8Write8 (Address, Value);
>
> +=C2=A0 }
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Performs a bitwise OR of an 8-bit PCI configuration register w= ith
>
> +=C2=A0 an 8-bit value.
>
> +
>
> +=C2=A0 Reads the 8-bit PCI configuration register specified by Addres= s, performs a
>
> +=C2=A0 bitwise OR between the read result and the value specified by<= br> >
> +=C2=A0 OrData, and writes the result to the 8-bit PCI configuration r= egister
>
> +=C2=A0 specified by Address. The value written to the PCI configurati= on register is
>
> +=C2=A0 returned. This function must guarantee that all PCI read and w= rite
> operations
>
> +=C2=A0 are serialized.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address The address that encodes the PCI Bus, Dev= ice, Function
> and
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Regist= er.
>
> +=C2=A0 @param=C2=A0 OrData=C2=A0 The value to OR with the PCI configu= ration register.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT8
>
> +EFIAPI
>
> +PciOr8 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0OrData
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 if (mMMCONFEnabled) {
>
> +=C2=A0 =C2=A0 return PciExpressOr8 (Address, OrData);
>
> +=C2=A0 } else {
>
> +=C2=A0 =C2=A0 return PciCf8Or8 (Address, OrData);
>
> +=C2=A0 }
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Performs a bitwise AND of an 8-bit PCI configuration register = with an 8-bit
>
> +=C2=A0 value.
>
> +
>
> +=C2=A0 Reads the 8-bit PCI configuration register specified by Addres= s, performs a
>
> +=C2=A0 bitwise AND between the read result and the value specified by= AndData,
> and
>
> +=C2=A0 writes the result to the 8-bit PCI configuration register spec= ified by
>
> +=C2=A0 Address. The value written to the PCI configuration register i= s returned.
>
> +=C2=A0 This function must guarantee that all PCI read and write opera= tions are
>
> +=C2=A0 serialized.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address The address that encodes the PCI Bus, Dev= ice, Function
> and
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Regist= er.
>
> +=C2=A0 @param=C2=A0 AndData The value to AND with the PCI configurati= on register.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT8
>
> +EFIAPI
>
> +PciAnd8 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0AndData
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 if (mMMCONFEnabled) {
>
> +=C2=A0 =C2=A0 return PciExpressAnd8 (Address, AndData);
>
> +=C2=A0 } else {
>
> +=C2=A0 =C2=A0 return PciCf8And8 (Address, AndData);
>
> +=C2=A0 }
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Performs a bitwise AND of an 8-bit PCI configuration register = with an 8-bit
>
> +=C2=A0 value, followed a=C2=A0 bitwise OR with another 8-bit value. >
> +
>
> +=C2=A0 Reads the 8-bit PCI configuration register specified by Addres= s, performs a
>
> +=C2=A0 bitwise AND between the read result and the value specified by= AndData,
>
> +=C2=A0 performs a bitwise OR between the result of the AND operation = and
>
> +=C2=A0 the value specified by OrData, and writes the result to the 8-= bit PCI
>
> +=C2=A0 configuration register specified by Address. The value written= to the PCI
>
> +=C2=A0 configuration register is returned. This function must guarant= ee that all PCI
>
> +=C2=A0 read and write operations are serialized.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address The address that encodes the PCI Bus, Dev= ice, Function
> and
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Regist= er.
>
> +=C2=A0 @param=C2=A0 AndData The value to AND with the PCI configurati= on register.
>
> +=C2=A0 @param=C2=A0 OrData=C2=A0 The value to OR with the result of t= he AND operation.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT8
>
> +EFIAPI
>
> +PciAndThenOr8 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0AndData,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0OrData
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 if (mMMCONFEnabled) {
>
> +=C2=A0 =C2=A0 return PciExpressAndThenOr8 (Address, AndData, OrData);=
>
> +=C2=A0 } else {
>
> +=C2=A0 =C2=A0 return PciCf8AndThenOr8 (Address, AndData, OrData);
>
> +=C2=A0 }
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Reads a bit field of a PCI configuration register.
>
> +
>
> +=C2=A0 Reads the bit field in an 8-bit PCI configuration register. Th= e bit field is
>
> +=C2=A0 specified by the StartBit and the EndBit. The value of the bit= field is
>
> +=C2=A0 returned.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If StartBit is greater than 7, then ASSERT().
>
> +=C2=A0 If EndBit is greater than 7, then ASSERT().
>
> +=C2=A0 If EndBit is less than StartBit, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address=C2=A0 =C2=A0The PCI configuration registe= r to read.
>
> +=C2=A0 @param=C2=A0 StartBit=C2=A0 The ordinal of the least significa= nt bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..7.
>
> +=C2=A0 @param=C2=A0 EndBit=C2=A0 =C2=A0 The ordinal of the most signi= ficant bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..7.
>
> +
>
> +=C2=A0 @return The value of the bit field read from the PCI configura= tion register.
>
> +
>
> +**/
>
> +UINT8
>
> +EFIAPI
>
> +PciBitFieldRead8 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 if (mMMCONFEnabled) {
>
> +=C2=A0 =C2=A0 return PciExpressBitFieldRead8 (Address, StartBit, EndB= it);
>
> +=C2=A0 } else {
>
> +=C2=A0 =C2=A0 return PciCf8BitFieldRead8 (Address, StartBit, EndBit);=
>
> +=C2=A0 }
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Writes a bit field to a PCI configuration register.
>
> +
>
> +=C2=A0 Writes Value to the bit field of the PCI configuration registe= r. The bit
>
> +=C2=A0 field is specified by the StartBit and the EndBit. All other b= its in the
>
> +=C2=A0 destination PCI configuration register are preserved. The new = value of the
>
> +=C2=A0 8-bit register is returned.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If StartBit is greater than 7, then ASSERT().
>
> +=C2=A0 If EndBit is greater than 7, then ASSERT().
>
> +=C2=A0 If EndBit is less than StartBit, then ASSERT().
>
> +=C2=A0 If Value is larger than the bitmask value range specified by S= tartBit and
> EndBit, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address=C2=A0 =C2=A0The PCI configuration registe= r to write.
>
> +=C2=A0 @param=C2=A0 StartBit=C2=A0 The ordinal of the least significa= nt bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..7.
>
> +=C2=A0 @param=C2=A0 EndBit=C2=A0 =C2=A0 The ordinal of the most signi= ficant bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..7.
>
> +=C2=A0 @param=C2=A0 Value=C2=A0 =C2=A0 =C2=A0The new value of the bit= field.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT8
>
> +EFIAPI
>
> +PciBitFieldWrite8 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Value
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 if (mMMCONFEnabled) {
>
> +=C2=A0 =C2=A0 return PciExpressBitFieldWrite8 (Address, StartBit, End= Bit, Value);
>
> +=C2=A0 } else {
>
> +=C2=A0 =C2=A0 return PciCf8BitFieldWrite8 (Address, StartBit, EndBit,= Value);
>
> +=C2=A0 }
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Reads a bit field in an 8-bit PCI configuration, performs a bi= twise OR, and
>
> +=C2=A0 writes the result back to the bit field in the 8-bit port.
>
> +
>
> +=C2=A0 Reads the 8-bit PCI configuration register specified by Addres= s, performs a
>
> +=C2=A0 bitwise OR between the read result and the value specified by<= br> >
> +=C2=A0 OrData, and writes the result to the 8-bit PCI configuration r= egister
>
> +=C2=A0 specified by Address. The value written to the PCI configurati= on register is
>
> +=C2=A0 returned. This function must guarantee that all PCI read and w= rite
> operations
>
> +=C2=A0 are serialized. Extra left bits in OrData are stripped.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If StartBit is greater than 7, then ASSERT().
>
> +=C2=A0 If EndBit is greater than 7, then ASSERT().
>
> +=C2=A0 If EndBit is less than StartBit, then ASSERT().
>
> +=C2=A0 If OrData is larger than the bitmask value range specified by = StartBit and
> EndBit, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address=C2=A0 =C2=A0The PCI configuration registe= r to write.
>
> +=C2=A0 @param=C2=A0 StartBit=C2=A0 The ordinal of the least significa= nt bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..7.
>
> +=C2=A0 @param=C2=A0 EndBit=C2=A0 =C2=A0 The ordinal of the most signi= ficant bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..7.
>
> +=C2=A0 @param=C2=A0 OrData=C2=A0 =C2=A0 The value to OR with the PCI = configuration register.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT8
>
> +EFIAPI
>
> +PciBitFieldOr8 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0OrData
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 if (mMMCONFEnabled) {
>
> +=C2=A0 =C2=A0 return PciExpressBitFieldOr8 (Address, StartBit, EndBit= , OrData);
>
> +=C2=A0 } else {
>
> +=C2=A0 =C2=A0 return PciCf8BitFieldOr8 (Address, StartBit, EndBit, Or= Data);
>
> +=C2=A0 }
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Reads a bit field in an 8-bit PCI configuration register, perf= orms a bitwise
>
> +=C2=A0 AND, and writes the result back to the bit field in the 8-bit = register.
>
> +
>
> +=C2=A0 Reads the 8-bit PCI configuration register specified by Addres= s, performs a
>
> +=C2=A0 bitwise AND between the read result and the value specified by= AndData,
> and
>
> +=C2=A0 writes the result to the 8-bit PCI configuration register spec= ified by
>
> +=C2=A0 Address. The value written to the PCI configuration register i= s returned.
>
> +=C2=A0 This function must guarantee that all PCI read and write opera= tions are
>
> +=C2=A0 serialized. Extra left bits in AndData are stripped.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If StartBit is greater than 7, then ASSERT().
>
> +=C2=A0 If EndBit is greater than 7, then ASSERT().
>
> +=C2=A0 If EndBit is less than StartBit, then ASSERT().
>
> +=C2=A0 If AndData is larger than the bitmask value range specified by= StartBit and
> EndBit, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address=C2=A0 =C2=A0The PCI configuration registe= r to write.
>
> +=C2=A0 @param=C2=A0 StartBit=C2=A0 The ordinal of the least significa= nt bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..7.
>
> +=C2=A0 @param=C2=A0 EndBit=C2=A0 =C2=A0 The ordinal of the most signi= ficant bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..7.
>
> +=C2=A0 @param=C2=A0 AndData=C2=A0 =C2=A0The value to AND with the PCI= configuration register.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT8
>
> +EFIAPI
>
> +PciBitFieldAnd8 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0AndData
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 if (mMMCONFEnabled) {
>
> +=C2=A0 =C2=A0 return PciExpressBitFieldAnd8 (Address, StartBit, EndBi= t, AndData);
>
> +=C2=A0 } else {
>
> +=C2=A0 =C2=A0 return PciCf8BitFieldAnd8 (Address, StartBit, EndBit, A= ndData);
>
> +=C2=A0 }
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Reads a bit field in an 8-bit port, performs a bitwise AND fol= lowed by a
>
> +=C2=A0 bitwise OR, and writes the result back to the bit field in the=
>
> +=C2=A0 8-bit port.
>
> +
>
> +=C2=A0 Reads the 8-bit PCI configuration register specified by Addres= s, performs a
>
> +=C2=A0 bitwise AND followed by a bitwise OR between the read result a= nd
>
> +=C2=A0 the value specified by AndData, and writes the result to the 8= -bit PCI
>
> +=C2=A0 configuration register specified by Address. The value written= to the PCI
>
> +=C2=A0 configuration register is returned. This function must guarant= ee that all PCI
>
> +=C2=A0 read and write operations are serialized. Extra left bits in b= oth AndData and
>
> +=C2=A0 OrData are stripped.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If StartBit is greater than 7, then ASSERT().
>
> +=C2=A0 If EndBit is greater than 7, then ASSERT().
>
> +=C2=A0 If EndBit is less than StartBit, then ASSERT().
>
> +=C2=A0 If AndData is larger than the bitmask value range specified by= StartBit and
> EndBit, then ASSERT().
>
> +=C2=A0 If OrData is larger than the bitmask value range specified by = StartBit and
> EndBit, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address=C2=A0 =C2=A0The PCI configuration registe= r to write.
>
> +=C2=A0 @param=C2=A0 StartBit=C2=A0 The ordinal of the least significa= nt bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..7.
>
> +=C2=A0 @param=C2=A0 EndBit=C2=A0 =C2=A0 The ordinal of the most signi= ficant bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..7.
>
> +=C2=A0 @param=C2=A0 AndData=C2=A0 =C2=A0The value to AND with the PCI= configuration register.
>
> +=C2=A0 @param=C2=A0 OrData=C2=A0 =C2=A0 The value to OR with the resu= lt of the AND operation.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT8
>
> +EFIAPI
>
> +PciBitFieldAndThenOr8 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0AndData,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0OrData
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 if (mMMCONFEnabled) {
>
> +=C2=A0 =C2=A0 return PciExpressBitFieldAndThenOr8 (Address, StartBit,= EndBit, AndData,
> OrData);
>
> +=C2=A0 } else {
>
> +=C2=A0 =C2=A0 return PciCf8BitFieldAndThenOr8 (Address, StartBit, End= Bit, AndData,
> OrData);
>
> +=C2=A0 }
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Reads a 16-bit PCI configuration register.
>
> +
>
> +=C2=A0 Reads and returns the 16-bit PCI configuration register specif= ied by
> Address.
>
> +=C2=A0 This function must guarantee that all PCI read and write opera= tions are
>
> +=C2=A0 serialized.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 16-bit boundary, then ASSERT().=
>
> +
>
> +=C2=A0 @param=C2=A0 Address The address that encodes the PCI Bus, Dev= ice, Function
> and
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Regist= er.
>
> +
>
> +=C2=A0 @return The read value from the PCI configuration register. >
> +
>
> +**/
>
> +UINT16
>
> +EFIAPI
>
> +PciRead16 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 if (mMMCONFEnabled) {
>
> +=C2=A0 =C2=A0 return PciExpressRead16 (Address);
>
> +=C2=A0 } else {
>
> +=C2=A0 =C2=A0 return PciCf8Read16 (Address);
>
> +=C2=A0 }
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Writes a 16-bit PCI configuration register.
>
> +
>
> +=C2=A0 Writes the 16-bit PCI configuration register specified by Addr= ess with the
>
> +=C2=A0 value specified by Value. Value is returned. This function mus= t guarantee
>
> +=C2=A0 that all PCI read and write operations are serialized.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 16-bit boundary, then ASSERT().=
>
> +
>
> +=C2=A0 @param=C2=A0 Address The address that encodes the PCI Bus, Dev= ice, Function
> and
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Regist= er.
>
> +=C2=A0 @param=C2=A0 Value=C2=A0 =C2=A0The value to write.
>
> +
>
> +=C2=A0 @return The value written to the PCI configuration register. >
> +
>
> +**/
>
> +UINT16
>
> +EFIAPI
>
> +PciWrite16 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT16=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Value
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 if (mMMCONFEnabled) {
>
> +=C2=A0 =C2=A0 return PciExpressWrite16 (Address, Value);
>
> +=C2=A0 } else {
>
> +=C2=A0 =C2=A0 return PciCf8Write16 (Address, Value);
>
> +=C2=A0 }
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Performs a bitwise OR of a 16-bit PCI configuration register w= ith
>
> +=C2=A0 a 16-bit value.
>
> +
>
> +=C2=A0 Reads the 16-bit PCI configuration register specified by Addre= ss, performs
> a
>
> +=C2=A0 bitwise OR between the read result and the value specified by<= br> >
> +=C2=A0 OrData, and writes the result to the 16-bit PCI configuration = register
>
> +=C2=A0 specified by Address. The value written to the PCI configurati= on register is
>
> +=C2=A0 returned. This function must guarantee that all PCI read and w= rite
> operations
>
> +=C2=A0 are serialized.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 16-bit boundary, then ASSERT().=
>
> +
>
> +=C2=A0 @param=C2=A0 Address The address that encodes the PCI Bus, Dev= ice, Function
> and
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Regist= er.
>
> +=C2=A0 @param=C2=A0 OrData=C2=A0 The value to OR with the PCI configu= ration register.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT16
>
> +EFIAPI
>
> +PciOr16 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT16=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 OrData
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 if (mMMCONFEnabled) {
>
> +=C2=A0 =C2=A0 return PciExpressOr16 (Address, OrData);
>
> +=C2=A0 } else {
>
> +=C2=A0 =C2=A0 return PciCf8Or16 (Address, OrData);
>
> +=C2=A0 }
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Performs a bitwise AND of a 16-bit PCI configuration register = with a 16-bit
>
> +=C2=A0 value.
>
> +
>
> +=C2=A0 Reads the 16-bit PCI configuration register specified by Addre= ss, performs
> a
>
> +=C2=A0 bitwise AND between the read result and the value specified by= AndData,
> and
>
> +=C2=A0 writes the result to the 16-bit PCI configuration register spe= cified by
>
> +=C2=A0 Address. The value written to the PCI configuration register i= s returned.
>
> +=C2=A0 This function must guarantee that all PCI read and write opera= tions are
>
> +=C2=A0 serialized.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 16-bit boundary, then ASSERT().=
>
> +
>
> +=C2=A0 @param=C2=A0 Address The address that encodes the PCI Bus, Dev= ice, Function
> and
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Regist= er.
>
> +=C2=A0 @param=C2=A0 AndData The value to AND with the PCI configurati= on register.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT16
>
> +EFIAPI
>
> +PciAnd16 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT16=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 AndData
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 if (mMMCONFEnabled) {
>
> +=C2=A0 =C2=A0 return PciExpressAnd16 (Address, AndData);
>
> +=C2=A0 } else {
>
> +=C2=A0 =C2=A0 return PciCf8And16 (Address, AndData);
>
> +=C2=A0 }
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Performs a bitwise AND of a 16-bit PCI configuration register = with a 16-bit
>
> +=C2=A0 value, followed a=C2=A0 bitwise OR with another 16-bit value.<= br> >
> +
>
> +=C2=A0 Reads the 16-bit PCI configuration register specified by Addre= ss, performs
> a
>
> +=C2=A0 bitwise AND between the read result and the value specified by= AndData,
>
> +=C2=A0 performs a bitwise OR between the result of the AND operation = and
>
> +=C2=A0 the value specified by OrData, and writes the result to the 16= -bit PCI
>
> +=C2=A0 configuration register specified by Address. The value written= to the PCI
>
> +=C2=A0 configuration register is returned. This function must guarant= ee that all PCI
>
> +=C2=A0 read and write operations are serialized.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 16-bit boundary, then ASSERT().=
>
> +
>
> +=C2=A0 @param=C2=A0 Address The address that encodes the PCI Bus, Dev= ice, Function
> and
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Regist= er.
>
> +=C2=A0 @param=C2=A0 AndData The value to AND with the PCI configurati= on register.
>
> +=C2=A0 @param=C2=A0 OrData=C2=A0 The value to OR with the result of t= he AND operation.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT16
>
> +EFIAPI
>
> +PciAndThenOr16 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT16=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 AndData,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT16=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 OrData
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 if (mMMCONFEnabled) {
>
> +=C2=A0 =C2=A0 return PciExpressAndThenOr16 (Address, AndData, OrData)= ;
>
> +=C2=A0 } else {
>
> +=C2=A0 =C2=A0 return PciCf8AndThenOr16 (Address, AndData, OrData); >
> +=C2=A0 }
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Reads a bit field of a PCI configuration register.
>
> +
>
> +=C2=A0 Reads the bit field in a 16-bit PCI configuration register. Th= e bit field is
>
> +=C2=A0 specified by the StartBit and the EndBit. The value of the bit= field is
>
> +=C2=A0 returned.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 16-bit boundary, then ASSERT().=
>
> +=C2=A0 If StartBit is greater than 15, then ASSERT().
>
> +=C2=A0 If EndBit is greater than 15, then ASSERT().
>
> +=C2=A0 If EndBit is less than StartBit, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address=C2=A0 =C2=A0The PCI configuration registe= r to read.
>
> +=C2=A0 @param=C2=A0 StartBit=C2=A0 The ordinal of the least significa= nt bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..15.
>
> +=C2=A0 @param=C2=A0 EndBit=C2=A0 =C2=A0 The ordinal of the most signi= ficant bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..15.
>
> +
>
> +=C2=A0 @return The value of the bit field read from the PCI configura= tion register.
>
> +
>
> +**/
>
> +UINT16
>
> +EFIAPI
>
> +PciBitFieldRead16 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 if (mMMCONFEnabled) {
>
> +=C2=A0 =C2=A0 return PciExpressBitFieldRead16 (Address, StartBit, End= Bit);
>
> +=C2=A0 } else {
>
> +=C2=A0 =C2=A0 return PciCf8BitFieldRead16 (Address, StartBit, EndBit)= ;
>
> +=C2=A0 }
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Writes a bit field to a PCI configuration register.
>
> +
>
> +=C2=A0 Writes Value to the bit field of the PCI configuration registe= r. The bit
>
> +=C2=A0 field is specified by the StartBit and the EndBit. All other b= its in the
>
> +=C2=A0 destination PCI configuration register are preserved. The new = value of the
>
> +=C2=A0 16-bit register is returned.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 16-bit boundary, then ASSERT().=
>
> +=C2=A0 If StartBit is greater than 15, then ASSERT().
>
> +=C2=A0 If EndBit is greater than 15, then ASSERT().
>
> +=C2=A0 If EndBit is less than StartBit, then ASSERT().
>
> +=C2=A0 If Value is larger than the bitmask value range specified by S= tartBit and
> EndBit, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address=C2=A0 =C2=A0The PCI configuration registe= r to write.
>
> +=C2=A0 @param=C2=A0 StartBit=C2=A0 The ordinal of the least significa= nt bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..15.
>
> +=C2=A0 @param=C2=A0 EndBit=C2=A0 =C2=A0 The ordinal of the most signi= ficant bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..15.
>
> +=C2=A0 @param=C2=A0 Value=C2=A0 =C2=A0 =C2=A0The new value of the bit= field.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT16
>
> +EFIAPI
>
> +PciBitFieldWrite16 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT16=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Value
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 if (mMMCONFEnabled) {
>
> +=C2=A0 =C2=A0 return PciExpressBitFieldWrite16 (Address, StartBit, En= dBit, Value);
>
> +=C2=A0 } else {
>
> +=C2=A0 =C2=A0 return PciCf8BitFieldWrite16 (Address, StartBit, EndBit= , Value);
>
> +=C2=A0 }
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Reads a bit field in a 16-bit PCI configuration, performs a bi= twise OR, and
>
> +=C2=A0 writes the result back to the bit field in the 16-bit port. >
> +
>
> +=C2=A0 Reads the 16-bit PCI configuration register specified by Addre= ss, performs
> a
>
> +=C2=A0 bitwise OR between the read result and the value specified by<= br> >
> +=C2=A0 OrData, and writes the result to the 16-bit PCI configuration = register
>
> +=C2=A0 specified by Address. The value written to the PCI configurati= on register is
>
> +=C2=A0 returned. This function must guarantee that all PCI read and w= rite
> operations
>
> +=C2=A0 are serialized. Extra left bits in OrData are stripped.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 16-bit boundary, then ASSERT().=
>
> +=C2=A0 If StartBit is greater than 15, then ASSERT().
>
> +=C2=A0 If EndBit is greater than 15, then ASSERT().
>
> +=C2=A0 If EndBit is less than StartBit, then ASSERT().
>
> +=C2=A0 If OrData is larger than the bitmask value range specified by = StartBit and
> EndBit, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address=C2=A0 =C2=A0The PCI configuration registe= r to write.
>
> +=C2=A0 @param=C2=A0 StartBit=C2=A0 The ordinal of the least significa= nt bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..15.
>
> +=C2=A0 @param=C2=A0 EndBit=C2=A0 =C2=A0 The ordinal of the most signi= ficant bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..15.
>
> +=C2=A0 @param=C2=A0 OrData=C2=A0 =C2=A0 The value to OR with the PCI = configuration register.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT16
>
> +EFIAPI
>
> +PciBitFieldOr16 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT16=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 OrData
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 if (mMMCONFEnabled) {
>
> +=C2=A0 =C2=A0 return PciExpressBitFieldOr16 (Address, StartBit, EndBi= t, OrData);
>
> +=C2=A0 } else {
>
> +=C2=A0 =C2=A0 return PciCf8BitFieldOr16 (Address, StartBit, EndBit, O= rData);
>
> +=C2=A0 }
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Reads a bit field in a 16-bit PCI configuration register, perf= orms a bitwise
>
> +=C2=A0 AND, and writes the result back to the bit field in the 16-bit= register.
>
> +
>
> +=C2=A0 Reads the 16-bit PCI configuration register specified by Addre= ss, performs
> a
>
> +=C2=A0 bitwise AND between the read result and the value specified by= AndData,
> and
>
> +=C2=A0 writes the result to the 16-bit PCI configuration register spe= cified by
>
> +=C2=A0 Address. The value written to the PCI configuration register i= s returned.
>
> +=C2=A0 This function must guarantee that all PCI read and write opera= tions are
>
> +=C2=A0 serialized. Extra left bits in AndData are stripped.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 16-bit boundary, then ASSERT().=
>
> +=C2=A0 If StartBit is greater than 15, then ASSERT().
>
> +=C2=A0 If EndBit is greater than 15, then ASSERT().
>
> +=C2=A0 If EndBit is less than StartBit, then ASSERT().
>
> +=C2=A0 If AndData is larger than the bitmask value range specified by= StartBit and
> EndBit, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address=C2=A0 =C2=A0The PCI configuration registe= r to write.
>
> +=C2=A0 @param=C2=A0 StartBit=C2=A0 The ordinal of the least significa= nt bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..15.
>
> +=C2=A0 @param=C2=A0 EndBit=C2=A0 =C2=A0 The ordinal of the most signi= ficant bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..15.
>
> +=C2=A0 @param=C2=A0 AndData=C2=A0 =C2=A0The value to AND with the PCI= configuration register.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT16
>
> +EFIAPI
>
> +PciBitFieldAnd16 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT16=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 AndData
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 if (mMMCONFEnabled) {
>
> +=C2=A0 =C2=A0 return PciExpressBitFieldAnd16 (Address, StartBit, EndB= it, AndData);
>
> +=C2=A0 } else {
>
> +=C2=A0 =C2=A0 return PciCf8BitFieldAnd16 (Address, StartBit, EndBit, = AndData);
>
> +=C2=A0 }
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Reads a bit field in a 16-bit port, performs a bitwise AND fol= lowed by a
>
> +=C2=A0 bitwise OR, and writes the result back to the bit field in the=
>
> +=C2=A0 16-bit port.
>
> +
>
> +=C2=A0 Reads the 16-bit PCI configuration register specified by Addre= ss, performs
> a
>
> +=C2=A0 bitwise AND followed by a bitwise OR between the read result a= nd
>
> +=C2=A0 the value specified by AndData, and writes the result to the 1= 6-bit PCI
>
> +=C2=A0 configuration register specified by Address. The value written= to the PCI
>
> +=C2=A0 configuration register is returned. This function must guarant= ee that all PCI
>
> +=C2=A0 read and write operations are serialized. Extra left bits in b= oth AndData and
>
> +=C2=A0 OrData are stripped.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 16-bit boundary, then ASSERT().=
>
> +=C2=A0 If StartBit is greater than 15, then ASSERT().
>
> +=C2=A0 If EndBit is greater than 15, then ASSERT().
>
> +=C2=A0 If EndBit is less than StartBit, then ASSERT().
>
> +=C2=A0 If AndData is larger than the bitmask value range specified by= StartBit and
> EndBit, then ASSERT().
>
> +=C2=A0 If OrData is larger than the bitmask value range specified by = StartBit and
> EndBit, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address=C2=A0 =C2=A0The PCI configuration registe= r to write.
>
> +=C2=A0 @param=C2=A0 StartBit=C2=A0 The ordinal of the least significa= nt bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..15.
>
> +=C2=A0 @param=C2=A0 EndBit=C2=A0 =C2=A0 The ordinal of the most signi= ficant bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..15.
>
> +=C2=A0 @param=C2=A0 AndData=C2=A0 =C2=A0The value to AND with the PCI= configuration register.
>
> +=C2=A0 @param=C2=A0 OrData=C2=A0 =C2=A0 The value to OR with the resu= lt of the AND operation.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT16
>
> +EFIAPI
>
> +PciBitFieldAndThenOr16 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT16=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 AndData,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT16=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 OrData
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 if (mMMCONFEnabled) {
>
> +=C2=A0 =C2=A0 return PciExpressBitFieldAndThenOr16 (Address, StartBit= , EndBit,
> AndData, OrData);
>
> +=C2=A0 } else {
>
> +=C2=A0 =C2=A0 return PciCf8BitFieldAndThenOr16 (Address, StartBit, En= dBit, AndData,
> OrData);
>
> +=C2=A0 }
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Reads a 32-bit PCI configuration register.
>
> +
>
> +=C2=A0 Reads and returns the 32-bit PCI configuration register specif= ied by
> Address.
>
> +=C2=A0 This function must guarantee that all PCI read and write opera= tions are
>
> +=C2=A0 serialized.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 32-bit boundary, then ASSERT().=
>
> +
>
> +=C2=A0 @param=C2=A0 Address The address that encodes the PCI Bus, Dev= ice, Function
> and
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Regist= er.
>
> +
>
> +=C2=A0 @return The read value from the PCI configuration register. >
> +
>
> +**/
>
> +UINT32
>
> +EFIAPI
>
> +PciRead32 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 if (mMMCONFEnabled) {
>
> +=C2=A0 =C2=A0 return PciExpressRead32 (Address);
>
> +=C2=A0 } else {
>
> +=C2=A0 =C2=A0 return PciCf8Read32 (Address);
>
> +=C2=A0 }
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Writes a 32-bit PCI configuration register.
>
> +
>
> +=C2=A0 Writes the 32-bit PCI configuration register specified by Addr= ess with the
>
> +=C2=A0 value specified by Value. Value is returned. This function mus= t guarantee
>
> +=C2=A0 that all PCI read and write operations are serialized.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 32-bit boundary, then ASSERT().=
>
> +
>
> +=C2=A0 @param=C2=A0 Address The address that encodes the PCI Bus, Dev= ice, Function
> and
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Regist= er.
>
> +=C2=A0 @param=C2=A0 Value=C2=A0 =C2=A0The value to write.
>
> +
>
> +=C2=A0 @return The value written to the PCI configuration register. >
> +
>
> +**/
>
> +UINT32
>
> +EFIAPI
>
> +PciWrite32 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Value
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 if (mMMCONFEnabled) {
>
> +=C2=A0 =C2=A0 return PciExpressWrite32 (Address, Value);
>
> +=C2=A0 } else {
>
> +=C2=A0 =C2=A0 return PciCf8Write32 (Address, Value);
>
> +=C2=A0 }
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Performs a bitwise OR of a 32-bit PCI configuration register w= ith
>
> +=C2=A0 a 32-bit value.
>
> +
>
> +=C2=A0 Reads the 32-bit PCI configuration register specified by Addre= ss, performs
> a
>
> +=C2=A0 bitwise OR between the read result and the value specified by<= br> >
> +=C2=A0 OrData, and writes the result to the 32-bit PCI configuration = register
>
> +=C2=A0 specified by Address. The value written to the PCI configurati= on register is
>
> +=C2=A0 returned. This function must guarantee that all PCI read and w= rite
> operations
>
> +=C2=A0 are serialized.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 32-bit boundary, then ASSERT().=
>
> +
>
> +=C2=A0 @param=C2=A0 Address The address that encodes the PCI Bus, Dev= ice, Function
> and
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Regist= er.
>
> +=C2=A0 @param=C2=A0 OrData=C2=A0 The value to OR with the PCI configu= ration register.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT32
>
> +EFIAPI
>
> +PciOr32 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 OrData
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 if (mMMCONFEnabled) {
>
> +=C2=A0 =C2=A0 return PciExpressOr32 (Address, OrData);
>
> +=C2=A0 } else {
>
> +=C2=A0 =C2=A0 return PciCf8Or32 (Address, OrData);
>
> +=C2=A0 }
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Performs a bitwise AND of a 32-bit PCI configuration register = with a 32-bit
>
> +=C2=A0 value.
>
> +
>
> +=C2=A0 Reads the 32-bit PCI configuration register specified by Addre= ss, performs
> a
>
> +=C2=A0 bitwise AND between the read result and the value specified by= AndData,
> and
>
> +=C2=A0 writes the result to the 32-bit PCI configuration register spe= cified by
>
> +=C2=A0 Address. The value written to the PCI configuration register i= s returned.
>
> +=C2=A0 This function must guarantee that all PCI read and write opera= tions are
>
> +=C2=A0 serialized.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 32-bit boundary, then ASSERT().=
>
> +
>
> +=C2=A0 @param=C2=A0 Address The address that encodes the PCI Bus, Dev= ice, Function
> and
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Regist= er.
>
> +=C2=A0 @param=C2=A0 AndData The value to AND with the PCI configurati= on register.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT32
>
> +EFIAPI
>
> +PciAnd32 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 AndData
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 if (mMMCONFEnabled) {
>
> +=C2=A0 =C2=A0 return PciExpressAnd32 (Address, AndData);
>
> +=C2=A0 } else {
>
> +=C2=A0 =C2=A0 return PciCf8And32 (Address, AndData);
>
> +=C2=A0 }
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Performs a bitwise AND of a 32-bit PCI configuration register = with a 32-bit
>
> +=C2=A0 value, followed a=C2=A0 bitwise OR with another 32-bit value.<= br> >
> +
>
> +=C2=A0 Reads the 32-bit PCI configuration register specified by Addre= ss, performs
> a
>
> +=C2=A0 bitwise AND between the read result and the value specified by= AndData,
>
> +=C2=A0 performs a bitwise OR between the result of the AND operation = and
>
> +=C2=A0 the value specified by OrData, and writes the result to the 32= -bit PCI
>
> +=C2=A0 configuration register specified by Address. The value written= to the PCI
>
> +=C2=A0 configuration register is returned. This function must guarant= ee that all PCI
>
> +=C2=A0 read and write operations are serialized.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 32-bit boundary, then ASSERT().=
>
> +
>
> +=C2=A0 @param=C2=A0 Address The address that encodes the PCI Bus, Dev= ice, Function
> and
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Regist= er.
>
> +=C2=A0 @param=C2=A0 AndData The value to AND with the PCI configurati= on register.
>
> +=C2=A0 @param=C2=A0 OrData=C2=A0 The value to OR with the result of t= he AND operation.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT32
>
> +EFIAPI
>
> +PciAndThenOr32 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 AndData,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 OrData
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 if (mMMCONFEnabled) {
>
> +=C2=A0 =C2=A0 return PciExpressAndThenOr32 (Address, AndData, OrData)= ;
>
> +=C2=A0 } else {
>
> +=C2=A0 =C2=A0 return PciCf8AndThenOr32 (Address, AndData, OrData); >
> +=C2=A0 }
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Reads a bit field of a PCI configuration register.
>
> +
>
> +=C2=A0 Reads the bit field in a 32-bit PCI configuration register. Th= e bit field is
>
> +=C2=A0 specified by the StartBit and the EndBit. The value of the bit= field is
>
> +=C2=A0 returned.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 32-bit boundary, then ASSERT().=
>
> +=C2=A0 If StartBit is greater than 31, then ASSERT().
>
> +=C2=A0 If EndBit is greater than 31, then ASSERT().
>
> +=C2=A0 If EndBit is less than StartBit, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address=C2=A0 =C2=A0The PCI configuration registe= r to read.
>
> +=C2=A0 @param=C2=A0 StartBit=C2=A0 The ordinal of the least significa= nt bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..31.
>
> +=C2=A0 @param=C2=A0 EndBit=C2=A0 =C2=A0 The ordinal of the most signi= ficant bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..31.
>
> +
>
> +=C2=A0 @return The value of the bit field read from the PCI configura= tion register.
>
> +
>
> +**/
>
> +UINT32
>
> +EFIAPI
>
> +PciBitFieldRead32 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 if (mMMCONFEnabled) {
>
> +=C2=A0 =C2=A0 return PciExpressBitFieldRead32 (Address, StartBit, End= Bit);
>
> +=C2=A0 } else {
>
> +=C2=A0 =C2=A0 return PciCf8BitFieldRead32 (Address, StartBit, EndBit)= ;
>
> +=C2=A0 }
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Writes a bit field to a PCI configuration register.
>
> +
>
> +=C2=A0 Writes Value to the bit field of the PCI configuration registe= r. The bit
>
> +=C2=A0 field is specified by the StartBit and the EndBit. All other b= its in the
>
> +=C2=A0 destination PCI configuration register are preserved. The new = value of the
>
> +=C2=A0 32-bit register is returned.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 32-bit boundary, then ASSERT().=
>
> +=C2=A0 If StartBit is greater than 31, then ASSERT().
>
> +=C2=A0 If EndBit is greater than 31, then ASSERT().
>
> +=C2=A0 If EndBit is less than StartBit, then ASSERT().
>
> +=C2=A0 If Value is larger than the bitmask value range specified by S= tartBit and
> EndBit, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address=C2=A0 =C2=A0The PCI configuration registe= r to write.
>
> +=C2=A0 @param=C2=A0 StartBit=C2=A0 The ordinal of the least significa= nt bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..31.
>
> +=C2=A0 @param=C2=A0 EndBit=C2=A0 =C2=A0 The ordinal of the most signi= ficant bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..31.
>
> +=C2=A0 @param=C2=A0 Value=C2=A0 =C2=A0 =C2=A0The new value of the bit= field.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT32
>
> +EFIAPI
>
> +PciBitFieldWrite32 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Value
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 if (mMMCONFEnabled) {
>
> +=C2=A0 =C2=A0 return PciExpressBitFieldWrite32 (Address, StartBit, En= dBit, Value);
>
> +=C2=A0 } else {
>
> +=C2=A0 =C2=A0 return PciCf8BitFieldWrite32 (Address, StartBit, EndBit= , Value);
>
> +=C2=A0 }
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Reads a bit field in a 32-bit PCI configuration, performs a bi= twise OR, and
>
> +=C2=A0 writes the result back to the bit field in the 32-bit port. >
> +
>
> +=C2=A0 Reads the 32-bit PCI configuration register specified by Addre= ss, performs
> a
>
> +=C2=A0 bitwise OR between the read result and the value specified by<= br> >
> +=C2=A0 OrData, and writes the result to the 32-bit PCI configuration = register
>
> +=C2=A0 specified by Address. The value written to the PCI configurati= on register is
>
> +=C2=A0 returned. This function must guarantee that all PCI read and w= rite
> operations
>
> +=C2=A0 are serialized. Extra left bits in OrData are stripped.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 32-bit boundary, then ASSERT().=
>
> +=C2=A0 If StartBit is greater than 31, then ASSERT().
>
> +=C2=A0 If EndBit is greater than 31, then ASSERT().
>
> +=C2=A0 If EndBit is less than StartBit, then ASSERT().
>
> +=C2=A0 If OrData is larger than the bitmask value range specified by = StartBit and
> EndBit, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address=C2=A0 =C2=A0The PCI configuration registe= r to write.
>
> +=C2=A0 @param=C2=A0 StartBit=C2=A0 The ordinal of the least significa= nt bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..31.
>
> +=C2=A0 @param=C2=A0 EndBit=C2=A0 =C2=A0 The ordinal of the most signi= ficant bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..31.
>
> +=C2=A0 @param=C2=A0 OrData=C2=A0 =C2=A0 The value to OR with the PCI = configuration register.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT32
>
> +EFIAPI
>
> +PciBitFieldOr32 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 OrData
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 if (mMMCONFEnabled) {
>
> +=C2=A0 =C2=A0 return PciExpressBitFieldOr32 (Address, StartBit, EndBi= t, OrData);
>
> +=C2=A0 } else {
>
> +=C2=A0 =C2=A0 return PciCf8BitFieldOr32 (Address, StartBit, EndBit, O= rData);
>
> +=C2=A0 }
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Reads a bit field in a 32-bit PCI configuration register, perf= orms a bitwise
>
> +=C2=A0 AND, and writes the result back to the bit field in the 32-bit= register.
>
> +
>
> +=C2=A0 Reads the 32-bit PCI configuration register specified by Addre= ss, performs
> a
>
> +=C2=A0 bitwise AND between the read result and the value specified by= AndData,
> and
>
> +=C2=A0 writes the result to the 32-bit PCI configuration register spe= cified by
>
> +=C2=A0 Address. The value written to the PCI configuration register i= s returned.
>
> +=C2=A0 This function must guarantee that all PCI read and write opera= tions are
>
> +=C2=A0 serialized. Extra left bits in AndData are stripped.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 32-bit boundary, then ASSERT().=
>
> +=C2=A0 If StartBit is greater than 31, then ASSERT().
>
> +=C2=A0 If EndBit is greater than 31, then ASSERT().
>
> +=C2=A0 If EndBit is less than StartBit, then ASSERT().
>
> +=C2=A0 If AndData is larger than the bitmask value range specified by= StartBit and
> EndBit, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address=C2=A0 =C2=A0The PCI configuration registe= r to write.
>
> +=C2=A0 @param=C2=A0 StartBit=C2=A0 The ordinal of the least significa= nt bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..31.
>
> +=C2=A0 @param=C2=A0 EndBit=C2=A0 =C2=A0 The ordinal of the most signi= ficant bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..31.
>
> +=C2=A0 @param=C2=A0 AndData=C2=A0 =C2=A0The value to AND with the PCI= configuration register.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT32
>
> +EFIAPI
>
> +PciBitFieldAnd32 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 AndData
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 if (mMMCONFEnabled) {
>
> +=C2=A0 =C2=A0 return PciExpressBitFieldAnd32 (Address, StartBit, EndB= it, AndData);
>
> +=C2=A0 } else {
>
> +=C2=A0 =C2=A0 return PciCf8BitFieldAnd32 (Address, StartBit, EndBit, = AndData);
>
> +=C2=A0 }
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Reads a bit field in a 32-bit port, performs a bitwise AND fol= lowed by a
>
> +=C2=A0 bitwise OR, and writes the result back to the bit field in the=
>
> +=C2=A0 32-bit port.
>
> +
>
> +=C2=A0 Reads the 32-bit PCI configuration register specified by Addre= ss, performs
> a
>
> +=C2=A0 bitwise AND followed by a bitwise OR between the read result a= nd
>
> +=C2=A0 the value specified by AndData, and writes the result to the 3= 2-bit PCI
>
> +=C2=A0 configuration register specified by Address. The value written= to the PCI
>
> +=C2=A0 configuration register is returned. This function must guarant= ee that all PCI
>
> +=C2=A0 read and write operations are serialized. Extra left bits in b= oth AndData and
>
> +=C2=A0 OrData are stripped.
>
> +
>
> +=C2=A0 If Address > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If Address is not aligned on a 32-bit boundary, then ASSERT().=
>
> +=C2=A0 If StartBit is greater than 31, then ASSERT().
>
> +=C2=A0 If EndBit is greater than 31, then ASSERT().
>
> +=C2=A0 If EndBit is less than StartBit, then ASSERT().
>
> +=C2=A0 If AndData is larger than the bitmask value range specified by= StartBit and
> EndBit, then ASSERT().
>
> +=C2=A0 If OrData is larger than the bitmask value range specified by = StartBit and
> EndBit, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 Address=C2=A0 =C2=A0The PCI configuration registe= r to write.
>
> +=C2=A0 @param=C2=A0 StartBit=C2=A0 The ordinal of the least significa= nt bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..31.
>
> +=C2=A0 @param=C2=A0 EndBit=C2=A0 =C2=A0 The ordinal of the most signi= ficant bit in the bit field.
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= Range 0..31.
>
> +=C2=A0 @param=C2=A0 AndData=C2=A0 =C2=A0The value to AND with the PCI= configuration register.
>
> +=C2=A0 @param=C2=A0 OrData=C2=A0 =C2=A0 The value to OR with the resu= lt of the AND operation.
>
> +
>
> +=C2=A0 @return The value written back to the PCI configuration regist= er.
>
> +
>
> +**/
>
> +UINT32
>
> +EFIAPI
>
> +PciBitFieldAndThenOr32 (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Address,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EndBit,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 AndData,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 OrData
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 if (mMMCONFEnabled) {
>
> +=C2=A0 =C2=A0 return PciExpressBitFieldAndThenOr32 (Address, StartBit= , EndBit,
> AndData, OrData);
>
> +=C2=A0 } else {
>
> +=C2=A0 =C2=A0 return PciCf8BitFieldAndThenOr32 (Address, StartBit, En= dBit, AndData,
> OrData);
>
> +=C2=A0 }
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Reads a range of PCI configuration registers into a caller sup= plied buffer.
>
> +
>
> +=C2=A0 Reads the range of PCI configuration registers specified by St= artAddress
> and
>
> +=C2=A0 Size into the buffer specified by Buffer. This function only a= llows the PCI
>
> +=C2=A0 configuration registers from a single PCI function to be read.= Size is
>
> +=C2=A0 returned. When possible 32-bit PCI configuration read cycles a= re used to
> read
>
> +=C2=A0 from StartAdress to StartAddress + Size. Due to alignment rest= rictions, 8-
> bit
>
> +=C2=A0 and 16-bit PCI configuration read cycles may be used at the be= ginning and
> the
>
> +=C2=A0 end of the range.
>
> +
>
> +=C2=A0 If StartAddress > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSER= T().
>
> +=C2=A0 If Size > 0 and Buffer is NULL, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 StartAddress=C2=A0 The starting address that enco= des the PCI Bus,
> Device,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 Function and Register.
>
> +=C2=A0 @param=C2=A0 Size=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 The size i= n bytes of the transfer.
>
> +=C2=A0 @param=C2=A0 Buffer=C2=A0 =C2=A0 =C2=A0 =C2=A0 The pointer to = a buffer receiving the data read.
>
> +
>
> +=C2=A0 @return Size
>
> +
>
> +**/
>
> +UINTN
>
> +EFIAPI
>
> +PciReadBuffer (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartAddress,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Size,
>
> +=C2=A0 OUT=C2=A0 =C2=A0 =C2=A0VOID=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 *Buffer
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 if (mMMCONFEnabled) {
>
> +=C2=A0 =C2=A0 return PciExpressReadBuffer (StartAddress, Size, Buffer= );
>
> +=C2=A0 } else {
>
> +=C2=A0 =C2=A0 return PciCf8ReadBuffer (StartAddress, Size, Buffer); >
> +=C2=A0 }
>
> +}
>
> +
>
> +/**
>
> +=C2=A0 Copies the data in a caller supplied buffer to a specified ran= ge of PCI
>
> +=C2=A0 configuration space.
>
> +
>
> +=C2=A0 Writes the range of PCI configuration registers specified by S= tartAddress
> and
>
> +=C2=A0 Size from the buffer specified by Buffer. This function only a= llows the PCI
>
> +=C2=A0 configuration registers from a single PCI function to be writt= en. Size is
>
> +=C2=A0 returned. When possible 32-bit PCI configuration write cycles = are used to
>
> +=C2=A0 write from StartAdress to StartAddress + Size. Due to alignmen= t
> restrictions,
>
> +=C2=A0 8-bit and 16-bit PCI configuration write cycles may be used at= the beginning
>
> +=C2=A0 and the end of the range.
>
> +
>
> +=C2=A0 If StartAddress > 0x0FFFFFFF, then ASSERT().
>
> +=C2=A0 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSER= T().
>
> +=C2=A0 If Size > 0 and Buffer is NULL, then ASSERT().
>
> +
>
> +=C2=A0 @param=C2=A0 StartAddress=C2=A0 The starting address that enco= des the PCI Bus,
> Device,
>
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 Function and Register.
>
> +=C2=A0 @param=C2=A0 Size=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 The size i= n bytes of the transfer.
>
> +=C2=A0 @param=C2=A0 Buffer=C2=A0 =C2=A0 =C2=A0 =C2=A0 The pointer to = a buffer containing the data to write.
>
> +
>
> +=C2=A0 @return Size written to StartAddress.
>
> +
>
> +**/
>
> +UINTN
>
> +EFIAPI
>
> +PciWriteBuffer (
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StartAddress,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Size,
>
> +=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 VOID=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 *Buffer
>
> +=C2=A0 )
>
> +{
>
> +=C2=A0 if (mMMCONFEnabled) {
>
> +=C2=A0 =C2=A0 return PciExpressWriteBuffer (StartAddress, Size, Buffe= r);
>
> +=C2=A0 } else {
>
> +=C2=A0 =C2=A0 return PciCf8WriteBuffer (StartAddress, Size, Buffer);<= br> >
> +=C2=A0 }
>
> +}
>
> diff --git a/UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLi= b.uni
> b/UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLib.uni
> new file mode 100644
> index 000000000000..98010ef2f929
> --- /dev/null
> +++ b/UefiPayloadPkg/Library/BasePciExpressLib/BasePciExpressLib.uni > @@ -0,0 +1,17 @@
> +// /** @file
>
> +// Instance of PCI Express Library using the 256 MB PCI Express MMIO<= br> > window.
>
> +//
>
> +// PCI Express Library that uses the 256 MB PCI Express MMIO window t= o
> perform
>
> +// PCI Configuration cycles. Layers on top of an I/O Library instance= .
>
> +//
>
> +// Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.= <BR>
>
> +//
>
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +//
>
> +// **/
>
> +
>
> +
>
> +#string STR_MODULE_ABSTRACT=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0#language en-US "Instance of PCI
> Express Library using the 256 MB PCI Express MMIO window"
>
> +
>
> +#string STR_MODULE_DESCRIPTION=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 #lan= guage en-US "PCI Express
> Library that uses the 256 MB PCI Express MMIO window to perform PCI > Configuration cycles. Layers on top of an I/O Library instance."<= br> >
> +
>
> diff --git
> a/UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.uni=
> b/UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.uni=
> new file mode 100644
> index 000000000000..ccc456356cf2
> --- /dev/null
> +++
> b/UefiPayloadPkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.uni=
> @@ -0,0 +1,17 @@
> +// /** @file
>
> +// Instance of PCI Library based on PCI Express Library.
>
> +//
>
> +// PCI Library that uses the 256 MB PCI Express MMIO window to perfor= m
> PCI
>
> +// Configuration cycles. Layers on one PCI Express Library instance.<= br> >
> +//
>
> +// Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.= <BR>
>
> +//
>
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +//
>
> +// **/
>
> +
>
> +
>
> +#string STR_MODULE_ABSTRACT=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0#language en-US "Instance of PCI
> Library based on PCI Express Library"
>
> +
>
> +#string STR_MODULE_DESCRIPTION=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 #lan= guage en-US "PCI Library that
> uses the 256 MB PCI Express MMIO window to perform PCI Configuration > cycles. Layers on an PCI Express Library instance."
>
> +
>
> --
> 2.25.4
>
>
> -=3D-=3D-=3D-=3D-=3D-=3D
> Groups.io Links: You receive all messages sent to this group.
>
> View/Reply Online (#61655): https://edk2.groups.io/= g/devel/message/61655
> Mute This Topic: https://groups.io/mt/75080104/1781375=
> Group Owner: devel+owner@edk2.groups.io
> Unsubscribe: https://edk2.groups.io/g/devel/unsub=C2=A0= [guo.dong@intel.co= m]
> -=3D-=3D-=3D-=3D-=3D-=3D



--
[Marcello Sylvester Bauer]<= /b>=C2=A0



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Email:=C2=A0=C2=A0[DEINE EMA= IL ADDRESSE]
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