From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-vs1-f52.google.com (mail-vs1-f52.google.com [209.85.217.52]) by mx.groups.io with SMTP id smtpd.web10.18081.1595422568425733159 for ; Wed, 22 Jul 2020 05:56:08 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@9elements.com header.s=google header.b=gPWX1R1l; spf=pass (domain: 9elements.com, ip: 209.85.217.52, mailfrom: marcello.bauer@9elements.com) Received: by mail-vs1-f52.google.com with SMTP id d11so1086811vsq.3 for ; Wed, 22 Jul 2020 05:56:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=9elements.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=n5YmUXUVBJ66HOmXmYATlgmfPsc87A1o36Eod05RSLc=; b=gPWX1R1l9NwBwU4qGCFLLqy/T9YrP3sQiKzvNFTQ5Z0VKYwHZSQgFionAp9m0esiX/ WJDrK2FJgo7DMSRW8sHEjucAGxkCiAIUgvZYfDrFhzJyQHn99DejIj6yisgZDMyWZqi3 BpgcedhrzEEZqsFTWJ7YjSrWZuBJ/fCyFjNInV4b3bHurzFTWb/WZMS7AQ5ytMktXA3A HpeaY/TorDIEBGWWiITOwQivs6Jj7XUqZ9VM4BbpNGWx+1f6cuTr/qaBbkHUj9zRsP3s xBrtIyDiD/BZRdIoRSrLUk0TLEEg1Acif1venvppkHHKKZBR4sE/Tb4cxmmAgF3dY1TR YHzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=n5YmUXUVBJ66HOmXmYATlgmfPsc87A1o36Eod05RSLc=; b=CA2xHHhuyUkAN/zMEbLaO8WlRk+f1PeA/F1oDC5GnF1OM1ZiLehJW3s+SHBXrmuOVQ qvpCZK1ZfbAxdKlOC0dfxpg2GcCNA8X8KBp8gRevhdZSknMf4Y54TrGpFslQhdJNNn6i jZQ4X5cny4RsVh5wcAqnjc1dCM/QuJPWBxQkix3Ycn1gPcwZbf5eSdQgcVZRAQMELiIK sEgxjNKkKKCNbtN9uEEFrjn3AD3oJHwMeLuzXBObBJD3kUITPKdbPn45BN4ExbFWSiNw vIPikqFd3qTJ9ljFKmCim4pidltPehfDg/qw+QxulwbPL1lU5g4Yh0KsFT7SqXmUiyHx dmSQ== X-Gm-Message-State: AOAM530ZolGc87LHmc+QAV/wC0PLzVX7yz/aExHxnFXyL6wOGRniTJn1 JI3twq9yZ/cgMLkPJ1RCs89c42gx7nHJNenwLMGWnvyYafY= X-Google-Smtp-Source: ABdhPJzjhZxe2XeTBUlLa9QoDJ1Qh9Wgfk6htZVaNxi6zhTZoNjrBX8mPFMoq+/lhiDLqEpB1fY/Ic//hiVVGCh0pWg= X-Received: by 2002:a67:fd1a:: with SMTP id f26mr22964292vsr.78.1595422567183; Wed, 22 Jul 2020 05:56:07 -0700 (PDT) MIME-Version: 1.0 References: <20200716114820.14211-1-marcello.bauer@9elements.com> <20200716114820.14211-3-marcello.bauer@9elements.com> In-Reply-To: From: "Marcello Sylvester Bauer" Date: Wed, 22 Jul 2020 14:55:56 +0200 Message-ID: Subject: Re: [edk2-devel] [PATCH v2 2/2] MdePkg: Add support for variable size MMCONF space To: devel@edk2.groups.io, Liming Gao Cc: "Ma, Maurice" , Patrick Rudolph , Christian Walter , "Desimone, Nathaniel L" , "Zeng, Star" , "Kinney, Michael D" Content-Type: multipart/alternative; boundary="000000000000624de805ab074383" --000000000000624de805ab074383 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hallo, the second patch will be divided accordingly. 1) act (done for v3) 2) the other libraries are not required for the patch series. I will adapt the commit message. 3) I will undo this change. 4) act (done for v3) 5) Indeed, my bad. On Tue, Jul 21, 2020 at 2:49 AM Liming Gao wrote: > Marcello: > Besides separate the patch for the different packages, I have some > comments on the change in PciExpressLib. > > 1) PciExpressxx() API description should be updated to include the inval= id > return value 0xFF, 0xFFFF or 0xFFFFFFFF in PciExpressLib.h and > PciExpressLib library implementation. > 2) There are three PciExprssion library instancs BasePciExpressLib, > DxeRuntimePciExpressLib and SmmPciExpressLib. They are required to be > updated. > 3) For the change in MdePkg\Library\BasePciExpressLib, why remove ASSERT= () > in PciExpressRegisterForRuntimeAccess() function? > 4) For the change in MdePkg\Library\BasePciExpressLib, > PcdPciExpressBaseSize() function header return value description is > incorrect. > 5) For the change in MdePkg\Library\BasePciExpressLib, > PciExpressAndThenOr32() function should return UINT32, but the code uses > return (UINT16) ~0;. There are similar issues in other function > implementation. Please check them. > > Thanks > Liming > -----Original Message----- > From: Ma, Maurice > Sent: 2020=E5=B9=B47=E6=9C=8820=E6=97=A5 23:26 > To: Marcello Sylvester Bauer ; > devel@edk2.groups.io > Cc: Patrick Rudolph ; Christian Walter < > christian.walter@9elements.com>; Desimone, Nathaniel L < > nathaniel.l.desimone@intel.com>; Zeng, Star ; > Kinney, Michael D ; Gao, Liming < > liming.gao@intel.com> > Subject: RE: [PATCH v2 2/2] MdePkg: Add support for variable size MMCONF > space > > Hi Marcello, > > Since this patch mixes changes for both UefiPayloadPkg and MdePkg. I > think you might want to split this patch into two so that it can be > reviewed by the proper package maintainers. > > Thanks > Maurice > > -----Original Message----- > > From: Marcello Sylvester Bauer > > Sent: Thursday, July 16, 2020 4:48 > > To: devel@edk2.groups.io > > Cc: Patrick Rudolph ; Christian Walter > > ; Ma, Maurice ; > > Desimone, Nathaniel L ; Zeng, Star > > ; Kinney, Michael D ; > > Gao, Liming > > Subject: [PATCH v2 2/2] MdePkg: Add support for variable size MMCONF > > space > > > > From: Patrick Rudolph > > > > On embedded AMD platforms the MMCONF window is usually only 64MiB. > > > > Add support for arbitrary sized MMCONF by introducing a new PCD. > > The default size is still 256MiB, but will be overwritten by > > UefiPayloadPkg with the real MMCONF size. > > > > Fixes crash on platforms not exposing 256 buses. > > > > Tested on: > > * AMD Stoney Ridge > > > > Signed-off-by: Patrick Rudolph > > Signed-off-by: Marcello Sylvester Bauer > > Cc: Patrick Rudolph > > Cc: Christian Walter > > Cc: Maurice Ma > > Cc: Nate DeSimone > > Cc: Star Zeng > > Cc: Michael D Kinney > > Cc: Liming Gao > > --- > > MdePkg/MdePkg.dec | 4 + > > UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc | 1 + > > MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf | 6 +- > > UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf | 1 + > > MdePkg/Include/Library/PciExpressLib.h | 5 +- > > MdePkg/Library/BasePciExpressLib/PciExpressLib.c | 118 > > +++++++++++++++++++- > > UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c | 4 +- > > 7 files changed, 131 insertions(+), 8 deletions(-) > > > > diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index > > 73f6c2407357..02e736a01126 100644 > > --- a/MdePkg/MdePkg.dec > > +++ b/MdePkg/MdePkg.dec > > @@ -2274,6 +2274,10 @@ [PcdsFixedAtBuild, PcdsPatchableInModule, > > PcdsDynamic, PcdsDynamicEx] > > # @Prompt PCI Express Base Address. > > gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000|UINT64| > > 0x0000000a + ## This value is used to set the size of PCI express > > hierarchy. The default is 256 MB.+ # @Prompt PCI Express Base Size.+ > > gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize|0x0FFFFFFF|UINT64|0x00 > > 00000f+ ## Default current ISO 639-2 language: English & French. # > > @Prompt Default Value of LangCodes Variable. > > gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultLangCodes|"engfraengfra= " > > |VOID*|0x0000001cdiff --git a/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc > > b/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc > > index a768a8702c66..162cbf47a83f 100644 > > --- a/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc > > +++ b/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc > > @@ -363,6 +363,7 @@ [PcdsDynamicDefault] > > gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|31 > > gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100 > > gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0+ > > gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize|0 > > ############################################################# > > ################### #diff --git > > a/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf > > b/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf > > index a7edb74cde71..12734b022ac7 100644 > > --- a/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf > > +++ b/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf > > @@ -1,7 +1,7 @@ > > ## @file-# Instance of PCI Express Library using the 256 MB PCI > > Express MMIO window.+# Instance of PCI Express Library using the > > variable size PCI Express MMIO window. #-# PCI Express Library that > > uses the 256 MB PCI Express MMIO window to perform+# PCI Express > > Library that uses the variable size PCI Express MMIO window to perform > > # PCI Configuration cycles. Layers on top of an I/O Library instance. > > # # Copyright (c) 2007 - 2018, Intel Corporation. All rights > reserved.
@@ -38,4 +38,4 @@ [LibraryClasses] > > [Pcd] gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## > > CONSUMES-+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize ## > > CONSUMESdiff --git a/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf > > b/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf > > index 1371d5eb7952..cebc81135565 100644 > > --- a/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf > > +++ b/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf > > @@ -54,6 +54,7 @@ [Pcd] > > gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution > > gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution > > gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress+ > > gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize [Depex] TRUEdiff --g= it > > a/MdePkg/Include/Library/PciExpressLib.h > > b/MdePkg/Include/Library/PciExpressLib.h > > index 826fdcf7db6c..d78193a0a352 100644 > > --- a/MdePkg/Include/Library/PciExpressLib.h > > +++ b/MdePkg/Include/Library/PciExpressLib.h > > @@ -2,8 +2,9 @@ > > Provides services to access PCI Configuration Space using the MMIO = PCI > > Express window. This library is identical to the PCI Library, excep= t > the access > > method for performing PCI- configuration cycles must be through the > > 256 MB PCI Express MMIO window whose base address- is defined by > > PcdPciExpressBaseAddress.+ configuration cycles must be through the > > PCI Express MMIO window whose base address+ is defined by > > PcdPciExpressBaseAddress and size defined by PcdPciExpressBaseSize.+ > > Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
> > SPDX- > > License-Identifier: BSD-2-Clause-Patentdiff --git > > a/MdePkg/Library/BasePciExpressLib/PciExpressLib.c > > b/MdePkg/Library/BasePciExpressLib/PciExpressLib.c > > index 99a166c3609b..4d099f2c575e 100644 > > --- a/MdePkg/Library/BasePciExpressLib/PciExpressLib.c > > +++ b/MdePkg/Library/BasePciExpressLib/PciExpressLib.c > > @@ -22,7 +22,8 @@ > > /** Assert the validity of a PCI address. A valid PCI address shou= ld > contain 1's- > > only in the low 28 bits.+ only in the low 28 bits. > PcdPciExpressBaseSize limits the > > size to the real+ number of PCI busses in this segment. @param A > The address > > to validate. @@ -58,7 +59,6 @@ PciExpressRegisterForRuntimeAccess ( > > IN UINTN Address ) {- ASSERT_INVALID_PCI_ADDRESS (Address); > return > > RETURN_UNSUPPORTED; } @@ -79,6 +79,24 @@ GetPciExpressBaseAddress ( > > return (VOID*)(UINTN) PcdGet64 (PcdPciExpressBaseAddress); } +/**+ > > Gets the size of PCI Express.++ This internal functions retrieves PCI > > Express Base Size via a PCD entry+ PcdPciExpressBaseSize.++ @return > > The base address of PCI Express.++**/+STATIC+UINTN+PcdPciExpressBaseSi= ze > (+ VOID+ )+{+ return > > (UINTN) PcdGet64 (PcdPciExpressBaseSize);+}+ /** Reads an 8-bit PCI > > configuration register. @@ -101,6 +119,9 @@ PciExpressRead8 ( > > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > > PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return MmioRea= d8 > > ((UINTN) GetPciExpressBaseAddress () + Address); } @@ -128,6 +149,9 @@ > > PciExpressWrite8 ( > > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > > PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return MmioWri= te8 > > ((UINTN) GetPciExpressBaseAddress () + Address, Value); } @@ -159,6 > > +183,9 @@ PciExpressOr8 ( > > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > > PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return MmioOr8 > ((UINTN) > > GetPciExpressBaseAddress () + Address, OrData); } @@ -190,6 +217,9 @@ > > PciExpressAnd8 ( > > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > > PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return MmioAnd= 8 > ((UINTN) > > GetPciExpressBaseAddress () + Address, AndData); } @@ -224,6 +254,9 @@ > > PciExpressAndThenOr8 ( > > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > > PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return > MmioAndThenOr8 > > ( (UINTN) GetPciExpressBaseAddress () + Address, > AndData,@@ - > > 261,6 +294,9 @@ PciExpressBitFieldRead8 ( > > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > > PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return > MmioBitFieldRead8 > > ( (UINTN) GetPciExpressBaseAddress () + Address, > StartBit,@@ - > > 302,6 +338,9 @@ PciExpressBitFieldWrite8 ( > > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > > PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return > MmioBitFieldWrite8 > > ( (UINTN) GetPciExpressBaseAddress () + Address, > StartBit,@@ - > > 347,6 +386,9 @@ PciExpressBitFieldOr8 ( > > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > > PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return > MmioBitFieldOr8 > > ( (UINTN) GetPciExpressBaseAddress () + Address, > StartBit,@@ - > > 392,6 +434,9 @@ PciExpressBitFieldAnd8 ( > > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > > PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return > MmioBitFieldAnd8 > > ( (UINTN) GetPciExpressBaseAddress () + Address, > StartBit,@@ - > > 442,6 +487,9 @@ PciExpressBitFieldAndThenOr8 ( > > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > > PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return > > MmioBitFieldAndThenOr8 ( (UINTN) GetPciExpressBaseAddress (= ) + > > Address, StartBit,@@ -474,6 +522,9 @@ PciExpressRead16 ( > > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > > PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return > MmioRead16 > > ((UINTN) GetPciExpressBaseAddress () + Address); } @@ -502,6 +553,9 @@ > > PciExpressWrite16 ( > > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > > PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return > MmioWrite16 > > ((UINTN) GetPciExpressBaseAddress () + Address, Value); } @@ -534,6 > > +588,9 @@ PciExpressOr16 ( > > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > > PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return MmioOr= 16 > > ((UINTN) GetPciExpressBaseAddress () + Address, OrData); } @@ -566,6 > > +623,9 @@ PciExpressAnd16 ( > > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > > PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return MmioAn= d16 > > ((UINTN) GetPciExpressBaseAddress () + Address, AndData); } @@ -601,6 > > +661,9 @@ PciExpressAndThenOr16 ( > > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > > PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return > > MmioAndThenOr16 ( (UINTN) GetPciExpressBaseAddress () + > Address, > > AndData,@@ -639,6 +702,9 @@ PciExpressBitFieldRead16 ( > > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > > PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return > > MmioBitFieldRead16 ( (UINTN) GetPciExpressBaseAddress () + > Address, > > StartBit,@@ -681,6 +747,9 @@ PciExpressBitFieldWrite16 ( > > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > > PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return > > MmioBitFieldWrite16 ( (UINTN) GetPciExpressBaseAddress () + > Address, > > StartBit,@@ -727,6 +796,9 @@ PciExpressBitFieldOr16 ( > > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > > PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return > MmioBitFieldOr16 > > ( (UINTN) GetPciExpressBaseAddress () + Address, > StartBit,@@ - > > 773,6 +845,9 @@ PciExpressBitFieldAnd16 ( > > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > > PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return > > MmioBitFieldAnd16 ( (UINTN) GetPciExpressBaseAddress () + > Address, > > StartBit,@@ -824,6 +899,9 @@ PciExpressBitFieldAndThenOr16 ( > > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > > PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return > > MmioBitFieldAndThenOr16 ( (UINTN) GetPciExpressBaseAddress = () > + > > Address, StartBit,@@ -856,6 +934,9 @@ PciExpressRead32 ( > > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > > PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return > MmioRead32 > > ((UINTN) GetPciExpressBaseAddress () + Address); } @@ -884,6 +965,9 @@ > > PciExpressWrite32 ( > > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > > PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return > MmioWrite32 > > ((UINTN) GetPciExpressBaseAddress () + Address, Value); } @@ -916,6 > > +1000,9 @@ PciExpressOr32 ( > > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > > PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return MmioOr= 32 > > ((UINTN) GetPciExpressBaseAddress () + Address, OrData); } @@ -948,6 > > +1035,9 @@ PciExpressAnd32 ( > > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > > PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return MmioAn= d32 > > ((UINTN) GetPciExpressBaseAddress () + Address, AndData); } @@ -983,6 > > +1073,9 @@ PciExpressAndThenOr32 ( > > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > > PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return > > MmioAndThenOr32 ( (UINTN) GetPciExpressBaseAddress () + > Address, > > AndData,@@ -1021,6 +1114,9 @@ PciExpressBitFieldRead32 ( > > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > > PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return > > MmioBitFieldRead32 ( (UINTN) GetPciExpressBaseAddress () + > Address, > > StartBit,@@ -1063,6 +1159,9 @@ PciExpressBitFieldWrite32 ( > > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > > PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return > > MmioBitFieldWrite32 ( (UINTN) GetPciExpressBaseAddress () + > Address, > > StartBit,@@ -1109,6 +1208,9 @@ PciExpressBitFieldOr32 ( > > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > > PcdPciExpressBaseSize()) {+ return (UINT32) ~0;+ } return > MmioBitFieldOr32 > > ( (UINTN) GetPciExpressBaseAddress () + Address, > StartBit,@@ - > > 1155,6 +1257,9 @@ PciExpressBitFieldAnd32 ( > > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > > PcdPciExpressBaseSize()) {+ return (UINT32) ~0;+ } return > > MmioBitFieldAnd32 ( (UINTN) GetPciExpressBaseAddress () + > Address, > > StartBit,@@ -1206,6 +1311,9 @@ PciExpressBitFieldAndThenOr32 ( > > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > > PcdPciExpressBaseSize()) {+ return (UINT32) ~0;+ } return > > MmioBitFieldAndThenOr32 ( (UINTN) GetPciExpressBaseAddress = () > + > > Address, StartBit,@@ -1249,6 +1357,9 @@ PciExpressReadBuffe= r ( > > UINTN ReturnValue; ASSERT_INVALID_PCI_ADDRESS (StartAddress);+ > if > > (StartAddress >=3D PcdPciExpressBaseSize()) {+ return (UINTN) ~0;+ = } > ASSERT > > (((StartAddress & 0xFFF) + Size) <=3D 0x1000); if (Size =3D=3D 0) {= @@ > -1349,6 > > +1460,9 @@ PciExpressWriteBuffer ( > > UINTN ReturnValue; > ASSERT_INVALID_PCI_ADDRESS > > (StartAddress);+ if (StartAddress >=3D PcdPciExpressBaseSize()) {+ > return > > (UINTN) ~0;+ } ASSERT (((StartAddress & 0xFFF) + Size) <=3D 0x1000)= ; > if (Size > > =3D=3D 0) {diff --git a/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c > > b/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c > > index a3974dcc02f8..a746d0581ee3 100644 > > --- a/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c > > +++ b/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c > > @@ -155,13 +155,15 @@ BlDxeEntryPoint ( > > } //- // Set PcdPciExpressBaseAddress by HOB info+ // Set > > PcdPciExpressBaseAddress and PcdPciExpressBaseSize by HOB info // > > GuidHob =3D GetFirstGuidHob (&gUefiAcpiBoardInfoGuid); if (GuidHob != = =3D > NULL) > > { AcpiBoardInfo =3D (ACPI_BOARD_INFO *)GET_GUID_HOB_DATA (GuidHob)= ; > > Status =3D PcdSet64S (PcdPciExpressBaseAddress, AcpiBoardInfo- > > >PcieBaseAddress); ASSERT_EFI_ERROR (Status);+ Status =3D PcdSe= t64S > > (PcdPciExpressBaseSize, AcpiBoardInfo->PcieBaseSize);+ > ASSERT_EFI_ERROR > > (Status); } return EFI_SUCCESS;-- > > 2.27.0 > > >=20 > > --=20 *[Marcello Sylvester Bauer]* 9elements Agency GmbH, Kortumstra=C3=9Fe 19-21, 44787 Bochum, Germany Email: [DEINE EMAIL ADDRESSE] Phone: *+49 234 68 94 188 <+492346894188>* Mobile: *+49 1722847618 <+491722847618>* Sitz der Gesellschaft: Bochum Handelsregister: Amtsgericht Bochum, HRB 17519 Gesch=C3=A4ftsf=C3=BChrung: Sebastian Deutsch, Eray Basar Datenschutzhinweise nach Art. 13 DSGVO --000000000000624de805ab074383 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hallo,

the second patch will be divided accordingly= .

1) act (done for v3)
2) the other libraries=C2=A0are not requir= ed for the patch series. I will adapt the commit message.
3) I will undo= this change.
4) act (done for v3)
5) Indeed, my bad.

On Tue, Jul = 21, 2020 at 2:49 AM Liming Gao <= liming.gao@intel.com> wrote:
Marcello:
=C2=A0 Besides separate the patch for the different packages, I have some = comments on the change in PciExpressLib.

1) PciExpressxx() API description should be updated to include the invalid= return value 0xFF, 0xFFFF or 0xFFFFFFFF in PciExpressLib.h and PciExpressL= ib library implementation.
2) There are three PciExprssion library instancs BasePciExpressLib, DxeRun= timePciExpressLib and SmmPciExpressLib. They are required to be updated. 3) For the change in MdePkg\Library\BasePciExpressLib, why remove ASSERT()= in PciExpressRegisterForRuntimeAccess() function?
4) For the change in MdePkg\Library\BasePciExpressLib, PcdPciExpressBaseSi= ze() function header return value description is incorrect.
5) For the change in MdePkg\Library\BasePciExpressLib, PciExpressAndThenOr= 32() function should return UINT32, but the code uses return (UINT16) ~0;. = There are similar issues in other function implementation. Please check the= m.

Thanks
Liming
-----Original Message-----
From: Ma, Maurice <maurice.ma@intel.com>
Sent: 2020=E5=B9=B47=E6=9C=8820=E6=97=A5 23:26
To: Marcello Sylvester Bauer <marcello.bauer@9elements.com>; devel@edk2.groups.io
Cc: Patrick Rudolph <patrick.rudolph@9elements.com>; Christian Walter &l= t;chris= tian.walter@9elements.com>; Desimone, Nathaniel L <nathaniel.l.desimone@= intel.com>; Zeng, Star <star.zeng@intel.com>; Kinney, Michael D <michael.d.kinney@= intel.com>; Gao, Liming <liming.gao@intel.com>
Subject: RE: [PATCH v2 2/2] MdePkg: Add support for variable size MMCONF s= pace

Hi Marcello,

Since this patch mixes changes for both UefiPayloadPkg=C2=A0 and MdePkg.= =C2=A0 I think you might want to split this patch into two so that it can = be reviewed by the proper package maintainers.

Thanks
Maurice
> -----Original Message-----
> From: Marcello Sylvester Bauer <marcello.bauer@9elements.com>
> Sent: Thursday, July 16, 2020 4:48
> To: devel@e= dk2.groups.io
> Cc: Patrick Rudolph <patrick.rudolph@9elements.com>; Christian Walt= er
> <christian.walter@9elements.com>; Ma, Maurice <maurice.ma@intel.com>; > Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Zeng, Star=
> <star.zen= g@intel.com>; Kinney, Michael D <michael.d.kinney@intel.com>;
> Gao, Liming <liming.gao@intel.com>
> Subject: [PATCH v2 2/2] MdePkg: Add support for variable size MMCONF =
> space
>
> From: Patrick Rudolph <patrick.rudolph@9elements.com>
>
> On embedded AMD platforms the MMCONF window is usually only 64MiB. >
> Add support for arbitrary sized MMCONF by introducing a new PCD.
> The default size is still 256MiB, but will be overwritten by
> UefiPayloadPkg with the real MMCONF size.
>
> Fixes crash on platforms not exposing 256 buses.
>
> Tested on:
> * AMD Stoney Ridge
>
> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
> Signed-off-by: Marcello Sylvester Bauer <marcello.bauer@9elements.com&g= t;
> Cc: Patrick Rudolph <patrick.rudolph@9elements.com>
> Cc: Christian Walter <christian.walter@9elements.com>
> Cc: Maurice Ma <maurice.ma@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Star Zeng <star.zeng@intel.com>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> ---
>=C2=A0 MdePkg/MdePkg.dec=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = = =C2=A0 =C2=A0 |=C2=A0 =C2=A04 +
>=C2=A0 UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A01 +
>=C2=A0 MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf |=C2=A0 = = =C2=A06 +-
>=C2=A0 UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A01 +
>=C2=A0 MdePkg/Include/Library/PciExpressLib.h=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A05 +-
>=C2=A0 MdePkg/Library/BasePciExpressLib/PciExpressLib.c=C2=A0 =C2=A0 = =C2=A0 =C2=A0| 118
> +++++++++++++++++++-
>=C2=A0 UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c=C2=A0 =C2=A0 =C2=A0 = = =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A04 +-
>=C2=A0 7 files changed, 131 insertions(+), 8 deletions(-)
>
> diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index
> 73f6c2407357..02e736a01126 100644
> --- a/MdePkg/MdePkg.dec
> +++ b/MdePkg/MdePkg.dec
> @@ -2274,6 +2274,10 @@ [PcdsFixedAtBuild, PcdsPatchableInModule,
> PcdsDynamic, PcdsDynamicEx]
>=C2=A0 =C2=A0 # @Prompt PCI Express Base Address.
> gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000|UINT64|<= br> > 0x0000000a +=C2=A0 ## This value is used to set the size of PCI expre= ss
> hierarchy. The default is 256 MB.+=C2=A0 # @Prompt PCI Express Base S= ize.+
> gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize|0x0FFFFFFF|UINT64|0x00=
> 00000f+=C2=A0 =C2=A0## Default current ISO 639-2 language: English &a= mp; French.=C2=A0 =C2=A0#
> @Prompt Default Value of LangCodes Variable.
> gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultLangCodes|"engfra= engfra"
> |VOID*|0x0000001cdiff --git a/UefiPayloadPkg/UefiPayloadPkgIa32X64.ds= c
> b/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc
> index a768a8702c66..162cbf47a83f 100644
> --- a/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc
> +++ b/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc
> @@ -363,6 +363,7 @@ [PcdsDynamicDefault]
>=C2=A0 =C2=A0 gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|31
> gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100
> gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0+
> gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize|0
> #############################################################
> ################### #diff --git
> a/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
> b/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
> index a7edb74cde71..12734b022ac7 100644
> --- a/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
> +++ b/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
> @@ -1,7 +1,7 @@
>=C2=A0 ## @file-#=C2=A0 Instance of PCI Express Library using the 256 = MB PCI
> Express MMIO window.+#=C2=A0 Instance of PCI Express Library using th= e
> variable size PCI Express MMIO window. #-#=C2=A0 PCI Express Library = that
> uses the 256 MB PCI Express MMIO window to perform+#=C2=A0 PCI Expres= s
> Library that uses the variable size PCI Express MMIO window to perfor= m
> #=C2=A0 PCI Configuration cycles. Layers on top of an I/O Library ins= tance.
> # #=C2=A0 Copyright (c) 2007 - 2018, Intel Corporation. All rights re= served.<BR>@@ -38,4 +38,4 @@ [LibraryClasses]
>=C2=A0 =C2=A0[Pcd]=C2=A0 =C2=A0gEfiMdePkgTokenSpaceGuid.PcdPciExpressB= aseAddress=C2=A0 ##
> CONSUMES-+=C2=A0 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize=C2=A0= ##
> CONSUMESdiff --git a/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf
> b/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf
> index 1371d5eb7952..cebc81135565 100644
> --- a/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf
> +++ b/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf
> @@ -54,6 +54,7 @@ [Pcd]
>=C2=A0 =C2=A0 gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalRe= solution
> gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution
> gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress+
> gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize=C2=A0 [Depex]=C2=A0 = =C2=A0TRUEdiff --git
> a/MdePkg/Include/Library/PciExpressLib.h
> b/MdePkg/Include/Library/PciExpressLib.h
> index 826fdcf7db6c..d78193a0a352 100644
> --- a/MdePkg/Include/Library/PciExpressLib.h
> +++ b/MdePkg/Include/Library/PciExpressLib.h
> @@ -2,8 +2,9 @@
>=C2=A0 =C2=A0 Provides services to access PCI Configuration Space usin= g the MMIO PCI
> Express window.=C2=A0 =C2=A0 This library is identical to the PCI Lib= rary, except the access
> method for performing PCI-=C2=A0 configuration cycles must be through= the
> 256 MB PCI Express MMIO window whose base address-=C2=A0 is defined b= y
> PcdPciExpressBaseAddress.+=C2=A0 configuration cycles must be through= the
> PCI Express MMIO window whose base address+=C2=A0 is defined by
> PcdPciExpressBaseAddress and size defined by PcdPciExpressBaseSize.+ =
> Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<= ;BR>
> SPDX-
> License-Identifier: BSD-2-Clause-Patentdiff --git
> a/MdePkg/Library/BasePciExpressLib/PciExpressLib.c
> b/MdePkg/Library/BasePciExpressLib/PciExpressLib.c
> index 99a166c3609b..4d099f2c575e 100644
> --- a/MdePkg/Library/BasePciExpressLib/PciExpressLib.c
> +++ b/MdePkg/Library/BasePciExpressLib/PciExpressLib.c
> @@ -22,7 +22,8 @@
>=C2=A0 =C2=A0/**=C2=A0 =C2=A0Assert the validity of a PCI address. A v= alid PCI address should contain 1's-
> only in the low 28 bits.+=C2=A0 only in the low 28 bits. PcdPciExpres= sBaseSize limits the
> size to the real+=C2=A0 number of PCI busses in this segment.=C2=A0 = =C2=A0 @param=C2=A0 A The address
> to validate. @@ -58,7 +59,6 @@ PciExpressRegisterForRuntimeAccess ( >=C2=A0 =C2=A0 IN UINTN=C2=A0 Address=C2=A0 =C2=A0) {-=C2=A0 ASSERT_INV= ALID_PCI_ADDRESS (Address);=C2=A0 =C2=A0return
> RETURN_UNSUPPORTED; } @@ -79,6 +79,24 @@ GetPciExpressBaseAddress ( >=C2=A0 =C2=A0 return (VOID*)(UINTN) PcdGet64 (PcdPciExpressBaseAddress= ); } +/**+=C2=A0
> Gets the size of PCI Express.++=C2=A0 This internal functions retriev= es PCI
> Express Base Size via a PCD entry+=C2=A0 PcdPciExpressBaseSize.++=C2= =A0 @return
> The base address of PCI Express.++**/+STATIC+UINTN+PcdPciExpressBaseS= ize (+=C2=A0 VOID+=C2=A0 )+{+=C2=A0 return
> (UINTN) PcdGet64 (PcdPciExpressBaseSize);+}+ /**=C2=A0 =C2=A0Reads an= 8-bit PCI
> configuration register. @@ -101,6 +119,9 @@ PciExpressRead8 (
>=C2=A0 =C2=A0 ) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+= =C2=A0 if (Address >=3D
> PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT8) ~0;+=C2=A0 }= =C2=A0 =C2=A0return MmioRead8
> ((UINTN) GetPciExpressBaseAddress () + Address); } @@ -128,6 +149,9 @= @
> PciExpressWrite8 (
>=C2=A0 =C2=A0 ) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+= =C2=A0 if (Address >=3D
> PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT8) ~0;+=C2=A0 }= =C2=A0 =C2=A0return MmioWrite8
> ((UINTN) GetPciExpressBaseAddress () + Address, Value); } @@ -159,6 <= br> > +183,9 @@ PciExpressOr8 (
>=C2=A0 =C2=A0 ) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+= =C2=A0 if (Address >=3D
> PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT8) ~0;+=C2=A0 }= =C2=A0 =C2=A0return MmioOr8 ((UINTN)
> GetPciExpressBaseAddress () + Address, OrData); } @@ -190,6 +217,9 @@=
> PciExpressAnd8 (
>=C2=A0 =C2=A0 ) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+= =C2=A0 if (Address >=3D
> PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT8) ~0;+=C2=A0 }= =C2=A0 =C2=A0return MmioAnd8 ((UINTN)
> GetPciExpressBaseAddress () + Address, AndData); } @@ -224,6 +254,9 @= @
> PciExpressAndThenOr8 (
>=C2=A0 =C2=A0 ) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+= =C2=A0 if (Address >=3D
> PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT8) ~0;+=C2=A0 }= =C2=A0 =C2=A0return MmioAndThenOr8
> (=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (UINTN) GetPciExpressBaseA= ddress () + Address,=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 AndData,@@ -<= br> > 261,6 +294,9 @@ PciExpressBitFieldRead8 (
>=C2=A0 =C2=A0 ) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+= =C2=A0 if (Address >=3D
> PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT8) ~0;+=C2=A0 }= =C2=A0 =C2=A0return MmioBitFieldRead8
> (=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (UINTN) GetPciExpressBaseA= ddress () + Address,=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 StartBit,@@ -=
> 302,6 +338,9 @@ PciExpressBitFieldWrite8 (
>=C2=A0 =C2=A0 ) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+= =C2=A0 if (Address >=3D
> PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT8) ~0;+=C2=A0 }= =C2=A0 =C2=A0return MmioBitFieldWrite8
> (=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (UINTN) GetPciExpressBaseA= ddress () + Address,=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 StartBit,@@ -=
> 347,6 +386,9 @@ PciExpressBitFieldOr8 (
>=C2=A0 =C2=A0 ) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+= =C2=A0 if (Address >=3D
> PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT8) ~0;+=C2=A0 }= =C2=A0 =C2=A0return MmioBitFieldOr8
> (=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (UINTN) GetPciExpressBaseA= ddress () + Address,=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 StartBit,@@ -=
> 392,6 +434,9 @@ PciExpressBitFieldAnd8 (
>=C2=A0 =C2=A0 ) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+= =C2=A0 if (Address >=3D
> PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT8) ~0;+=C2=A0 }= =C2=A0 =C2=A0return MmioBitFieldAnd8
> (=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (UINTN) GetPciExpressBaseA= ddress () + Address,=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 StartBit,@@ -=
> 442,6 +487,9 @@ PciExpressBitFieldAndThenOr8 (
>=C2=A0 =C2=A0 ) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+= =C2=A0 if (Address >=3D
> PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT8) ~0;+=C2=A0 }= =C2=A0 =C2=A0return
> MmioBitFieldAndThenOr8 (=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (UI= NTN) GetPciExpressBaseAddress () +
> Address,=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 StartBit,@@ -474,6 = +522,9 @@ PciExpressRead16 (
>=C2=A0 =C2=A0 ) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+= =C2=A0 if (Address >=3D
> PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT16) ~0;+=C2=A0 }= = =C2=A0 =C2=A0return MmioRead16
> ((UINTN) GetPciExpressBaseAddress () + Address); } @@ -502,6 +553,9 @= @
> PciExpressWrite16 (
>=C2=A0 =C2=A0 ) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+= =C2=A0 if (Address >=3D
> PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT16) ~0;+=C2=A0 }= = =C2=A0 =C2=A0return MmioWrite16
> ((UINTN) GetPciExpressBaseAddress () + Address, Value); } @@ -534,6 <= br> > +588,9 @@ PciExpressOr16 (
>=C2=A0 =C2=A0 ) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+= =C2=A0 if (Address >=3D
> PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT16) ~0;+=C2=A0 }= = =C2=A0 =C2=A0return MmioOr16
> ((UINTN) GetPciExpressBaseAddress () + Address, OrData); } @@ -566,6 =
> +623,9 @@ PciExpressAnd16 (
>=C2=A0 =C2=A0 ) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+= =C2=A0 if (Address >=3D
> PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT16) ~0;+=C2=A0 }= = =C2=A0 =C2=A0return MmioAnd16
> ((UINTN) GetPciExpressBaseAddress () + Address, AndData); } @@ -601,6=
> +661,9 @@ PciExpressAndThenOr16 (
>=C2=A0 =C2=A0 ) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+= =C2=A0 if (Address >=3D
> PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT16) ~0;+=C2=A0 }= = =C2=A0 =C2=A0return
> MmioAndThenOr16 (=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (UINTN) Ge= tPciExpressBaseAddress () + Address,
> AndData,@@ -639,6 +702,9 @@ PciExpressBitFieldRead16 (
>=C2=A0 =C2=A0 ) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+= =C2=A0 if (Address >=3D
> PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT16) ~0;+=C2=A0 }= = =C2=A0 =C2=A0return
> MmioBitFieldRead16 (=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (UINTN)= GetPciExpressBaseAddress () + Address,
> StartBit,@@ -681,6 +747,9 @@ PciExpressBitFieldWrite16 (
>=C2=A0 =C2=A0 ) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+= =C2=A0 if (Address >=3D
> PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT16) ~0;+=C2=A0 }= = =C2=A0 =C2=A0return
> MmioBitFieldWrite16 (=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (UINTN= ) GetPciExpressBaseAddress () + Address,
> StartBit,@@ -727,6 +796,9 @@ PciExpressBitFieldOr16 (
>=C2=A0 =C2=A0 ) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+= =C2=A0 if (Address >=3D
> PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT16) ~0;+=C2=A0 }= = =C2=A0 =C2=A0return MmioBitFieldOr16
> (=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (UINTN) GetPciExpressBaseA= ddress () + Address,=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 StartBit,@@ -=
> 773,6 +845,9 @@ PciExpressBitFieldAnd16 (
>=C2=A0 =C2=A0 ) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+= =C2=A0 if (Address >=3D
> PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT16) ~0;+=C2=A0 }= = =C2=A0 =C2=A0return
> MmioBitFieldAnd16 (=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (UINTN) = GetPciExpressBaseAddress () + Address,
> StartBit,@@ -824,6 +899,9 @@ PciExpressBitFieldAndThenOr16 (
>=C2=A0 =C2=A0 ) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+= =C2=A0 if (Address >=3D
> PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT16) ~0;+=C2=A0 }= = =C2=A0 =C2=A0return
> MmioBitFieldAndThenOr16 (=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (U= INTN) GetPciExpressBaseAddress () +
> Address,=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 StartBit,@@ -856,6 = +934,9 @@ PciExpressRead32 (
>=C2=A0 =C2=A0 ) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+= =C2=A0 if (Address >=3D
> PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT16) ~0;+=C2=A0 }= = =C2=A0 =C2=A0return MmioRead32
> ((UINTN) GetPciExpressBaseAddress () + Address); } @@ -884,6 +965,9 @= @
> PciExpressWrite32 (
>=C2=A0 =C2=A0 ) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+= =C2=A0 if (Address >=3D
> PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT16) ~0;+=C2=A0 }= = =C2=A0 =C2=A0return MmioWrite32
> ((UINTN) GetPciExpressBaseAddress () + Address, Value); } @@ -916,6 <= br> > +1000,9 @@ PciExpressOr32 (
>=C2=A0 =C2=A0 ) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+= =C2=A0 if (Address >=3D
> PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT16) ~0;+=C2=A0 }= = =C2=A0 =C2=A0return MmioOr32
> ((UINTN) GetPciExpressBaseAddress () + Address, OrData); } @@ -948,6<= br> > +1035,9 @@ PciExpressAnd32 (
>=C2=A0 =C2=A0 ) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+= =C2=A0 if (Address >=3D
> PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT16) ~0;+=C2=A0 }= = =C2=A0 =C2=A0return MmioAnd32
> ((UINTN) GetPciExpressBaseAddress () + Address, AndData); } @@ -983,6=
> +1073,9 @@ PciExpressAndThenOr32 (
>=C2=A0 =C2=A0 ) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+= =C2=A0 if (Address >=3D
> PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT16) ~0;+=C2=A0 }= = =C2=A0 =C2=A0return
> MmioAndThenOr32 (=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (UINTN) Ge= tPciExpressBaseAddress () + Address,
> AndData,@@ -1021,6 +1114,9 @@ PciExpressBitFieldRead32 (
>=C2=A0 =C2=A0 ) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+= =C2=A0 if (Address >=3D
> PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT16) ~0;+=C2=A0 }= = =C2=A0 =C2=A0return
> MmioBitFieldRead32 (=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (UINTN)= GetPciExpressBaseAddress () + Address,
> StartBit,@@ -1063,6 +1159,9 @@ PciExpressBitFieldWrite32 (
>=C2=A0 =C2=A0 ) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+= =C2=A0 if (Address >=3D
> PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT16) ~0;+=C2=A0 }= = =C2=A0 =C2=A0return
> MmioBitFieldWrite32 (=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (UINTN= ) GetPciExpressBaseAddress () + Address,
> StartBit,@@ -1109,6 +1208,9 @@ PciExpressBitFieldOr32 (
>=C2=A0 =C2=A0 ) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+= =C2=A0 if (Address >=3D
> PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT32) ~0;+=C2=A0 }= = =C2=A0 =C2=A0return MmioBitFieldOr32
> (=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (UINTN) GetPciExpressBaseA= ddress () + Address,=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 StartBit,@@ -=
> 1155,6 +1257,9 @@ PciExpressBitFieldAnd32 (
>=C2=A0 =C2=A0 ) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+= =C2=A0 if (Address >=3D
> PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT32) ~0;+=C2=A0 }= = =C2=A0 =C2=A0return
> MmioBitFieldAnd32 (=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (UINTN) = GetPciExpressBaseAddress () + Address,
> StartBit,@@ -1206,6 +1311,9 @@ PciExpressBitFieldAndThenOr32 (
>=C2=A0 =C2=A0 ) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+= =C2=A0 if (Address >=3D
> PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT32) ~0;+=C2=A0 }= = =C2=A0 =C2=A0return
> MmioBitFieldAndThenOr32 (=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (U= INTN) GetPciExpressBaseAddress () +
> Address,=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 StartBit,@@ -1249,6= +1357,9 @@ PciExpressReadBuffer (
>=C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0ReturnValue;=C2=A0 =C2=A0 ASSERT_INVAL= ID_PCI_ADDRESS (StartAddress);+=C2=A0 if
> (StartAddress >=3D PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return= (UINTN) ~0;+=C2=A0 }=C2=A0 =C2=A0ASSERT
> (((StartAddress & 0xFFF) + Size) <=3D 0x1000);=C2=A0 =C2=A0 if= (Size =3D=3D 0) {@@ -1349,6
> +1460,9 @@ PciExpressWriteBuffer (
>=C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ReturnValue;=C2=A0 = = =C2=A0 ASSERT_INVALID_PCI_ADDRESS
> (StartAddress);+=C2=A0 if (StartAddress >=3D PcdPciExpressBaseSize= ()) {+=C2=A0 =C2=A0 return
> (UINTN) ~0;+=C2=A0 }=C2=A0 =C2=A0ASSERT (((StartAddress & 0xFFF) = + Size) <=3D 0x1000);=C2=A0 =C2=A0 if (Size
> =3D=3D 0) {diff --git a/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c > b/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c
> index a3974dcc02f8..a746d0581ee3 100644
> --- a/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c
> +++ b/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c
> @@ -155,13 +155,15 @@ BlDxeEntryPoint (
>=C2=A0 =C2=A0 }=C2=A0 =C2=A0 //-=C2=A0 // Set PcdPciExpressBaseAddress= by HOB info+=C2=A0 // Set
> PcdPciExpressBaseAddress and PcdPciExpressBaseSize by HOB info=C2=A0 = = =C2=A0//
> GuidHob =3D GetFirstGuidHob (&gUefiAcpiBoardInfoGuid);=C2=A0 =C2= =A0if (GuidHob !=3D NULL)
> {=C2=A0 =C2=A0 =C2=A0AcpiBoardInfo =3D (ACPI_BOARD_INFO *)GET_GUID_HO= B_DATA (GuidHob);
> Status =3D PcdSet64S (PcdPciExpressBaseAddress, AcpiBoardInfo-
> >PcieBaseAddress);=C2=A0 =C2=A0 =C2=A0ASSERT_EFI_ERROR (Status);+= =C2=A0 =C2=A0 Status =3D PcdSet64S
> (PcdPciExpressBaseSize, AcpiBoardInfo->PcieBaseSize);+=C2=A0 =C2= =A0 ASSERT_EFI_ERROR
> (Status);=C2=A0 =C2=A0}=C2=A0 =C2=A0 return EFI_SUCCESS;--
> 2.27.0






--
= [Marcello Sylvester Bauer]=C2=A0



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