From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-vk1-f182.google.com (mail-vk1-f182.google.com [209.85.221.182]) by mx.groups.io with SMTP id smtpd.web10.51049.1595837381153723815 for ; Mon, 27 Jul 2020 01:09:41 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@9elements.com header.s=google header.b=Ix0D1Shz; spf=pass (domain: 9elements.com, ip: 209.85.221.182, mailfrom: marcello.bauer@9elements.com) Received: by mail-vk1-f182.google.com with SMTP id g22so3561975vke.9 for ; Mon, 27 Jul 2020 01:09:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=9elements.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=jlbfEjhrybdEfc0L7T0fmrYOEGv/ENb5IntbioqaWak=; b=Ix0D1ShzdxTDvbznd4g0NWspq34FabYYjpOrqgefIoWj4YywJJeYAMvvSwfe4ST+M3 4j+duel7chsiOilolsnc9xLR7HeGb1S6RfObS1Q13qp08e417QjbxZGCD9Z+yTMevKAS WABA0BBNDvH4OaOPiCbSpZkZM2VGYbOKRsWzBUsu6oi/ghvlWjeBVIpxmJnIh05EbkNY X+kp5wFZa3rmMyWJOO3ykNVn5bdau+/iIfEnW/vZ2zwcz6IPBed3Yua8lIirD/Gmfodp +8o7wmZ0SbCejOZT/3/xNkRANZYzv4BhCAzdY8m4lWI05Y6GG4jTx9alYlXbLbpLsP+M jKhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=jlbfEjhrybdEfc0L7T0fmrYOEGv/ENb5IntbioqaWak=; b=mK11QhpBKOERdHcODIFzUjSQzGqarefnBD4OrJa/OCvSIGmUmHVIpuPMLzIvJUfDrw icjnujQ4QPDIYeQ/tsm/IPhSAYCAn453+KLjGqKoFCe4+qSro7CTfsc++xVHdWQucOSQ 5JWaxqAV4oRs9S3E01MZ4UFie9QwvDWQ/lI7g6tSOmrL9zc53bSAtCG4YRiQVix2VmKe 8ASOZgfCJigDgAT64D9kBU10Hq8Stt5YM5APTo+idRzE/foPsmBmjrfoMnKBRoyqDNv+ hREXvRz1YQSZC3eDorLzKfPNWgwkARHFHu1v0BEPfaMoSIaXDnpalbLW6Sfsprlu3ohy Pqtg== X-Gm-Message-State: AOAM531TpwFbMl8na+vbaaPNP/XcrbC3hGdfD/R73zU70WxGWExL05Dx ZwcirPObJW0Cukld2Y5/45dpzEoW2H6P3PeILk9Rqg== X-Google-Smtp-Source: ABdhPJx3wVTneVdpf47R4aFbC1+GaiJ9RoSzmJt/h9CR6aZszIuiu41o8459kkQB718IGxGhzR84aJDO8wuYMIRLwu8= X-Received: by 2002:a1f:4393:: with SMTP id q141mr2181989vka.91.1595837379974; Mon, 27 Jul 2020 01:09:39 -0700 (PDT) MIME-Version: 1.0 References: <20200722131543.12530-1-marcello.bauer@9elements.com> <20200722131543.12530-3-marcello.bauer@9elements.com> In-Reply-To: From: "Marcello Sylvester Bauer" Date: Mon, 27 Jul 2020 10:09:29 +0200 Message-ID: Subject: Re: [edk2-devel] [PATCH v3 2/3] MdePkg/BasePciExpressLib: Support variable size MMCONF To: "Gao, Liming" Cc: "devel@edk2.groups.io" , Patrick Rudolph , Christian Walter , "Kinney, Michael D" Content-Type: multipart/alternative; boundary="000000000000272d0e05ab67d864" --000000000000272d0e05ab67d864 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Liming: My mistake. 0x0FFFFFFF is still a valid address offset so default PcdPciExpressBaseSize should be 0x10000000. Thanks, Marcello On Thu, Jul 23, 2020 at 12:04 PM Gao, Liming wrote: > > > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of Marcello > Sylvester Bauer > Sent: 2020=E5=B9=B47=E6=9C=8822=E6=97=A5 21:16 > To: devel@edk2.groups.io > Cc: Patrick Rudolph ; Christian Walter < > christian.walter@9elements.com>; Kinney, Michael D < > michael.d.kinney@intel.com>; Gao, Liming > Subject: [edk2-devel] [PATCH v3 2/3] MdePkg/BasePciExpressLib: Support > variable size MMCONF > > Add support for arbitrary sized MMCONF by introducing a new PCD. > > Signed-off-by: Patrick Rudolph > Signed-off-by: Marcello Sylvester Bauer > Cc: Patrick Rudolph > Cc: Christian Walter > Cc: Michael D Kinney > Cc: Liming Gao > --- > MdePkg/MdePkg.dec | 4 + > MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf | 6 +- > MdePkg/Include/Library/PciExpressLib.h | 5 +- > MdePkg/Library/BasePciExpressLib/PciExpressLib.c | 216 > +++++++++++++++++--- > 4 files changed, 193 insertions(+), 38 deletions(-) > > diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index > 73f6c2407357..02e736a01126 100644 > --- a/MdePkg/MdePkg.dec > +++ b/MdePkg/MdePkg.dec > @@ -2274,6 +2274,10 @@ [PcdsFixedAtBuild, PcdsPatchableInModule, > PcdsDynamic, PcdsDynamicEx] > # @Prompt PCI Express Base Address. > gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000|UINT64|0x00= 00000a > + ## This value is used to set the size of PCI express hierarchy. The > default is 256 MB.+ # @Prompt PCI Express Base Size.+ > gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize|0x0FFFFFFF|UINT64|0x000000= 0f+ > ## Default current ISO 639-2 language: English & French. # @Prompt > Default Value of LangCodes Variable. > gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultLangCodes|"engfraengfra"|= VOID*|0x0000001cdiff > --git a/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf > b/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf > > [Liming] 256M is 0x10000000. PCD value is 0x0FFFFFFF. Does it mean that > the default value is 256M - 1? > > Thanks > Liming > > index a7edb74cde71..12734b022ac7 100644 > --- a/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf > +++ b/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf > @@ -1,7 +1,7 @@ > ## @file-# Instance of PCI Express Library using the 256 MB PCI Express > MMIO window.+# Instance of PCI Express Library using the variable size P= CI > Express MMIO window. #-# PCI Express Library that uses the 256 MB PCI > Express MMIO window to perform+# PCI Express Library that uses the > variable size PCI Express MMIO window to perform # PCI Configuration > cycles. Layers on top of an I/O Library instance. # # Copyright (c) 2007= - > 2018, Intel Corporation. All rights reserved.
@@ -38,4 +38,4 @@ > [LibraryClasses] > [Pcd] gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## > CONSUMES-+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize ## CONSUMESdi= ff > --git a/MdePkg/Include/Library/PciExpressLib.h > b/MdePkg/Include/Library/PciExpressLib.h > index 826fdcf7db6c..d78193a0a352 100644 > --- a/MdePkg/Include/Library/PciExpressLib.h > +++ b/MdePkg/Include/Library/PciExpressLib.h > @@ -2,8 +2,9 @@ > Provides services to access PCI Configuration Space using the MMIO PCI > Express window. This library is identical to the PCI Library, except t= he > access method for performing PCI- configuration cycles must be through t= he > 256 MB PCI Express MMIO window whose base address- is defined by > PcdPciExpressBaseAddress.+ configuration cycles must be through the PCI > Express MMIO window whose base address+ is defined by > PcdPciExpressBaseAddress and size defined by PcdPciExpressBaseSize.+ > Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patentdiff --git > a/MdePkg/Library/BasePciExpressLib/PciExpressLib.c > b/MdePkg/Library/BasePciExpressLib/PciExpressLib.c > index 99a166c3609b..0311ecb3025f 100644 > --- a/MdePkg/Library/BasePciExpressLib/PciExpressLib.c > +++ b/MdePkg/Library/BasePciExpressLib/PciExpressLib.c > @@ -22,7 +22,8 @@ > /** Assert the validity of a PCI address. A valid PCI address should > contain 1's- only in the low 28 bits.+ only in the low 28 bits. > PcdPciExpressBaseSize limits the size to the real+ number of PCI busses = in > this segment. @param A The address to validate. @@ -79,6 +80,24 @@ > GetPciExpressBaseAddress ( > return (VOID*)(UINTN) PcdGet64 (PcdPciExpressBaseAddress); } +/**+ > Gets the size of PCI Express.++ This internal functions retrieves PCI > Express Base Size via a PCD entry+ PcdPciExpressBaseSize.++ @return The > base size of PCI Express.++**/+STATIC+UINTN+PcdPciExpressBaseSize (+ > VOID+ )+{+ return (UINTN) PcdGet64 (PcdPciExpressBaseSize);+}+ /** > Reads an 8-bit PCI configuration register. @@ -91,7 +110,8 @@ > GetPciExpressBaseAddress ( > @param Address The address that encodes the PCI Bus, Device, Function > and Register. - @return The read value from the PCI > configuration register.+ @retval 0xFF Invalid PCI address.+ @retval > other The read value from the PCI configuration register. **/ UINT8@@ > -101,6 +121,9 @@ PciExpressRead8 ( > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return MmioRead8 > ((UINTN) GetPciExpressBaseAddress () + Address); } @@ -117,7 +140,8 @@ > PciExpressRead8 ( > Register. @param Value The value to write. - > @return The value written to the PCI configuration register.+ @retval > 0xFF Invalid PCI address.+ @retval other The value written to the PCI > configuration register. **/ UINT8@@ -128,6 +152,9 @@ PciExpressWrite8 ( > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return MmioWrite8 > ((UINTN) GetPciExpressBaseAddress () + Address, Value); } @@ -148,7 +175,= 8 > @@ PciExpressWrite8 ( > Register. @param OrData The value to OR with the > PCI configuration register. - @return The value written back to the PCI > configuration register.+ @retval 0xFF Invalid PCI address.+ @retval > other The value written to the PCI configuration register. **/ UINT8@@ > -159,6 +187,9 @@ PciExpressOr8 ( > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return MmioOr8 > ((UINTN) GetPciExpressBaseAddress () + Address, OrData); } @@ -179,7 +210= ,8 > @@ PciExpressOr8 ( > Register. @param AndData The value to AND with the > PCI configuration register. - @return The value written back to the PCI > configuration register.+ @retval 0xFF Invalid PCI address.+ @retval > other The value written back to the PCI configuration register. **/ UINT= 8@@ > -190,6 +222,9 @@ PciExpressAnd8 ( > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return MmioAnd8 > ((UINTN) GetPciExpressBaseAddress () + Address, AndData); } @@ -212,7 > +247,8 @@ PciExpressAnd8 ( > @param AndData The value to AND with the PCI configuration register. > @param OrData The value to OR with the result of the AND operation. - > @return The value written back to the PCI configuration register.+ @retv= al > 0xFF Invalid PCI address.+ @retval other The value written back to the > PCI configuration register. **/ UINT8@@ -224,6 +260,9 @@ > PciExpressAndThenOr8 ( > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return > MmioAndThenOr8 ( (UINTN) GetPciExpressBaseAddress () + Address= , > AndData,@@ -249,7 +288,9 @@ PciExpressAndThenOr8 ( > @param EndBit The ordinal of the most significant bit in the bit > field. Range 0..7. - @return The value of the bit > field read from the PCI configuration register.+ @retval 0xFF Invalid P= CI > address.+ @retval other The value of the bit field read from the PCI > configuration+ register. **/ UINT8@@ -261,6 +302,9 @@ > PciExpressBitFieldRead8 ( > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return > MmioBitFieldRead8 ( (UINTN) GetPciExpressBaseAddress () + > Address, StartBit,@@ -289,7 +333,8 @@ PciExpressBitFieldRead8 = ( > Range 0..7. @param Value The new value of the > bit field. - @return The value written back to the PCI configuration > register.+ @retval 0xFF Invalid PCI address.+ @retval other The value > written back to the PCI configuration register. **/ UINT8@@ -302,6 > +347,9 @@ PciExpressBitFieldWrite8 ( > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return > MmioBitFieldWrite8 ( (UINTN) GetPciExpressBaseAddress () + > Address, StartBit,@@ -334,7 +382,8 @@ PciExpressBitFieldWrite8= ( > Range 0..7. @param OrData The value to OR with > the PCI configuration register. - @return The value written back to the > PCI configuration register.+ @retval 0xFF Invalid PCI address.+ @retva= l > other The value written back to the PCI configuration register. **/ UINT= 8@@ > -347,6 +396,9 @@ PciExpressBitFieldOr8 ( > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return > MmioBitFieldOr8 ( (UINTN) GetPciExpressBaseAddress () + > Address, StartBit,@@ -379,7 +431,8 @@ PciExpressBitFieldOr8 ( > Range 0..7. @param AndData The value to AND wit= h > the PCI configuration register. - @return The value written back to the > PCI configuration register.+ @retval 0xFF Invalid PCI address.+ @retva= l > other The value written back to the PCI configuration register. **/ UINT= 8@@ > -392,6 +445,9 @@ PciExpressBitFieldAnd8 ( > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return > MmioBitFieldAnd8 ( (UINTN) GetPciExpressBaseAddress () + > Address, StartBit,@@ -428,7 +484,8 @@ PciExpressBitFieldAnd8 ( > @param AndData The value to AND with the PCI configuration > register. @param OrData The value to OR with the result of the AND > operation. - @return The value written back to the PCI configuration > register.+ @retval 0xFF Invalid PCI address.+ @retval other The value > written back to the PCI configuration register. **/ UINT8@@ -442,6 > +499,9 @@ PciExpressBitFieldAndThenOr8 ( > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return > MmioBitFieldAndThenOr8 ( (UINTN) GetPciExpressBaseAddress () + > Address, StartBit,@@ -464,7 +524,8 @@ > PciExpressBitFieldAndThenOr8 ( > @param Address The address that encodes the PCI Bus, Device, Function > and Register. - @return The read value from the PCI > configuration register.+ @retval 0xFF Invalid PCI address.+ @retval > other The read value from the PCI configuration register. **/ UINT16@@ > -474,6 +535,9 @@ PciExpressRead16 ( > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return MmioRead1= 6 > ((UINTN) GetPciExpressBaseAddress () + Address); } @@ -491,7 +555,8 @@ > PciExpressRead16 ( > Register. @param Value The value to write. - > @return The value written to the PCI configuration register.+ @retval > 0xFFFF Invalid PCI address.+ @retval other The value written to the P= CI > configuration register. **/ UINT16@@ -502,6 +567,9 @@ PciExpressWrite16 = ( > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return MmioWrite= 16 > ((UINTN) GetPciExpressBaseAddress () + Address, Value); } @@ -523,7 +591,= 8 > @@ PciExpressWrite16 ( > Register. @param OrData The value to OR with the > PCI configuration register. - @return The value written back to the PCI > configuration register.+ @retval 0xFFFF Invalid PCI address.+ @retval > other The value written back to the PCI configuration register. **/ > UINT16@@ -534,6 +603,9 @@ PciExpressOr16 ( > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return MmioOr16 > ((UINTN) GetPciExpressBaseAddress () + Address, OrData); } @@ -555,7 +627= ,8 > @@ PciExpressOr16 ( > Register. @param AndData The value to AND with the > PCI configuration register. - @return The value written back to the PCI > configuration register.+ @retval 0xFFFF Invalid PCI address.+ @retval > other The value written back to the PCI configuration register. **/ > UINT16@@ -566,6 +639,9 @@ PciExpressAnd16 ( > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return MmioAnd16 > ((UINTN) GetPciExpressBaseAddress () + Address, AndData); } @@ -589,7 > +665,8 @@ PciExpressAnd16 ( > @param AndData The value to AND with the PCI configuration register. > @param OrData The value to OR with the result of the AND operation. - > @return The value written back to the PCI configuration register.+ @retv= al > 0xFFFF Invalid PCI address.+ @retval other The value written back to > the PCI configuration register. **/ UINT16@@ -601,6 +678,9 @@ > PciExpressAndThenOr16 ( > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return > MmioAndThenOr16 ( (UINTN) GetPciExpressBaseAddress () + > Address, AndData,@@ -627,7 +707,9 @@ PciExpressAndThenOr16 ( > @param EndBit The ordinal of the most significant bit in the bit > field. Range 0..15. - @return The value of the bit > field read from the PCI configuration register.+ @retval 0xFFFF Invalid > PCI address.+ @retval other The value of the bit field read from the P= CI > configuration+ register. **/ UINT16@@ -639,6 +721,9 @@ > PciExpressBitFieldRead16 ( > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return > MmioBitFieldRead16 ( (UINTN) GetPciExpressBaseAddress () + > Address, StartBit,@@ -668,7 +753,8 @@ PciExpressBitFieldRead16= ( > Range 0..15. @param Value The new value of th= e > bit field. - @return The value written back to the PCI configuration > register.+ @retval 0xFFFF Invalid PCI address.+ @retval other The > value written back to the PCI configuration register. **/ UINT16@@ > -681,6 +767,9 @@ PciExpressBitFieldWrite16 ( > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return > MmioBitFieldWrite16 ( (UINTN) GetPciExpressBaseAddress () + > Address, StartBit,@@ -714,7 +803,8 @@ PciExpressBitFieldWrite1= 6 ( > Range 0..15. @param OrData The value to OR wit= h > the PCI configuration register. - @return The value written back to the > PCI configuration register.+ @retval 0xFFFF Invalid PCI address.+ > @retval other The value written back to the PCI configuration register. > **/ UINT16@@ -727,6 +817,9 @@ PciExpressBitFieldOr16 ( > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return > MmioBitFieldOr16 ( (UINTN) GetPciExpressBaseAddress () + > Address, StartBit,@@ -760,7 +853,8 @@ PciExpressBitFieldOr16 ( > Range 0..15. @param AndData The value to AND > with the PCI configuration register. - @return The value written back to > the PCI configuration register.+ @retval 0xFFFF Invalid PCI address.+ > @retval other The value written back to the PCI configuration register. > **/ UINT16@@ -773,6 +867,9 @@ PciExpressBitFieldAnd16 ( > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return > MmioBitFieldAnd16 ( (UINTN) GetPciExpressBaseAddress () + > Address, StartBit,@@ -810,7 +907,8 @@ PciExpressBitFieldAnd16 = ( > @param AndData The value to AND with the PCI configuration > register. @param OrData The value to OR with the result of the AND > operation. - @return The value written back to the PCI configuration > register.+ @retval 0xFFFF Invalid PCI address.+ @retval other The > value written back to the PCI configuration register. **/ UINT16@@ > -824,6 +922,9 @@ PciExpressBitFieldAndThenOr16 ( > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return > MmioBitFieldAndThenOr16 ( (UINTN) GetPciExpressBaseAddress () = + > Address, StartBit,@@ -846,7 +947,8 @@ > PciExpressBitFieldAndThenOr16 ( > @param Address The address that encodes the PCI Bus, Device, Function > and Register. - @return The read value from the PCI > configuration register.+ @retval 0xFFFF Invalid PCI address.+ @retval > other The read value from the PCI configuration register. **/ UINT32@@ > -856,6 +958,9 @@ PciExpressRead32 ( > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > PcdPciExpressBaseSize()) {+ return (UINT32) ~0;+ } return MmioRead3= 2 > ((UINTN) GetPciExpressBaseAddress () + Address); } @@ -873,7 +978,8 @@ > PciExpressRead32 ( > Register. @param Value The value to write. - > @return The value written to the PCI configuration register.+ @retval > 0xFFFFFFFF Invalid PCI address.+ @retval other The value written = to > the PCI configuration register. **/ UINT32@@ -884,6 +990,9 @@ > PciExpressWrite32 ( > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > PcdPciExpressBaseSize()) {+ return (UINT32) ~0;+ } return MmioWrite= 32 > ((UINTN) GetPciExpressBaseAddress () + Address, Value); } @@ -905,7 +1014= ,8 > @@ PciExpressWrite32 ( > Register. @param OrData The value to OR with the > PCI configuration register. - @return The value written back to the PCI > configuration register.+ @retval 0xFFFFFFFF Invalid PCI address.+ > @retval other The value written back to the PCI configuration > register. **/ UINT32@@ -916,6 +1026,9 @@ PciExpressOr32 ( > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > PcdPciExpressBaseSize()) {+ return (UINT32) ~0;+ } return MmioOr32 > ((UINTN) GetPciExpressBaseAddress () + Address, OrData); } @@ -937,7 > +1050,8 @@ PciExpressOr32 ( > Register. @param AndData The value to AND with the > PCI configuration register. - @return The value written back to the PCI > configuration register.+ @retval 0xFFFFFFFF Invalid PCI address.+ > @retval other The value written back to the PCI configuration > register. **/ UINT32@@ -948,6 +1062,9 @@ PciExpressAnd32 ( > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > PcdPciExpressBaseSize()) {+ return (UINT32) ~0;+ } return MmioAnd32 > ((UINTN) GetPciExpressBaseAddress () + Address, AndData); } @@ -971,7 > +1088,8 @@ PciExpressAnd32 ( > @param AndData The value to AND with the PCI configuration register. > @param OrData The value to OR with the result of the AND operation. - > @return The value written back to the PCI configuration register.+ @retv= al > 0xFFFFFFFF Invalid PCI address.+ @retval other The value written > back to the PCI configuration register. **/ UINT32@@ -983,6 +1101,9 @@ > PciExpressAndThenOr32 ( > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > PcdPciExpressBaseSize()) {+ return (UINT32) ~0;+ } return > MmioAndThenOr32 ( (UINTN) GetPciExpressBaseAddress () + > Address, AndData,@@ -1009,7 +1130,9 @@ PciExpressAndThenOr32 ( > @param EndBit The ordinal of the most significant bit in the bit > field. Range 0..31. - @return The value of the bit > field read from the PCI configuration register.+ @retval 0xFFFFFFFF > Invalid PCI address.+ @retval other The value of the bit field rea= d > from the PCI+ configuration register. **/ UINT32@@ > -1021,6 +1144,9 @@ PciExpressBitFieldRead32 ( > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > PcdPciExpressBaseSize()) {+ return (UINT32) ~0;+ } return > MmioBitFieldRead32 ( (UINTN) GetPciExpressBaseAddress () + > Address, StartBit,@@ -1050,7 +1176,8 @@ PciExpressBitFieldRead= 32 > ( > Range 0..31. @param Value The new value of th= e > bit field. - @return The value written back to the PCI configuration > register.+ @retval 0xFFFFFFFF Invalid PCI address.+ @retval other > The value written back to the PCI configuration register. **/ UINT32@@ > -1063,6 +1190,9 @@ PciExpressBitFieldWrite32 ( > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > PcdPciExpressBaseSize()) {+ return (UINT32) ~0;+ } return > MmioBitFieldWrite32 ( (UINTN) GetPciExpressBaseAddress () + > Address, StartBit,@@ -1096,7 +1226,8 @@ > PciExpressBitFieldWrite32 ( > Range 0..31. @param OrData The value to OR wit= h > the PCI configuration register. - @return The value written back to the > PCI configuration register.+ @retval 0xFFFFFFFF Invalid PCI address.+ > @retval other The value written back to the PCI configuration > register. **/ UINT32@@ -1109,6 +1240,9 @@ PciExpressBitFieldOr32 ( > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > PcdPciExpressBaseSize()) {+ return (UINT32) ~0;+ } return > MmioBitFieldOr32 ( (UINTN) GetPciExpressBaseAddress () + > Address, StartBit,@@ -1142,7 +1276,8 @@ PciExpressBitFieldOr32= ( > Range 0..31. @param AndData The value to AND > with the PCI configuration register. - @return The value written back to > the PCI configuration register.+ @retval 0xFFFFFFFF Invalid PCI > address.+ @retval other The value written back to the PCI > configuration register. **/ UINT32@@ -1155,6 +1290,9 @@ > PciExpressBitFieldAnd32 ( > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > PcdPciExpressBaseSize()) {+ return (UINT32) ~0;+ } return > MmioBitFieldAnd32 ( (UINTN) GetPciExpressBaseAddress () + > Address, StartBit,@@ -1192,7 +1330,8 @@ PciExpressBitFieldAnd3= 2 ( > @param AndData The value to AND with the PCI configuration > register. @param OrData The value to OR with the result of the AND > operation. - @return The value written back to the PCI configuration > register.+ @retval 0xFFFFFFFF Invalid PCI address.+ @retval other > The value written back to the PCI configuration register. **/ UINT32@@ > -1206,6 +1345,9 @@ PciExpressBitFieldAndThenOr32 ( > ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D > PcdPciExpressBaseSize()) {+ return (UINT32) ~0;+ } return > MmioBitFieldAndThenOr32 ( (UINTN) GetPciExpressBaseAddress () = + > Address, StartBit,@@ -1235,7 +1377,8 @@ > PciExpressBitFieldAndThenOr32 ( > @param Size The size in bytes of the transfer. @param > Buffer The pointer to a buffer receiving the data read. - @return > Size read data from StartAddress.+ @retval (UINTN)~0 Invalid PCI > address.+ @retval other Size read data from StartAddress. **/ UINT= N@@ > -1249,6 +1392,9 @@ PciExpressReadBuffer ( > UINTN ReturnValue; ASSERT_INVALID_PCI_ADDRESS (StartAddress);+ i= f > (StartAddress >=3D PcdPciExpressBaseSize()) {+ return (UINTN) ~0;+ } > ASSERT (((StartAddress & 0xFFF) + Size) <=3D 0x1000); if (Size =3D=3D= 0) {@@ > -1335,7 +1481,8 @@ PciExpressReadBuffer ( > @param Size The size in bytes of the transfer. @param > Buffer The pointer to a buffer containing the data to write. - > @return Size written to StartAddress.+ @retval (UINTN)~0 Invalid PCI > address.+ @retval other Size written to StartAddress. **/ UINTN@@ > -1349,6 +1496,9 @@ PciExpressWriteBuffer ( > UINTN ReturnValue; > ASSERT_INVALID_PCI_ADDRESS (StartAddress);+ if (StartAddress >=3D > PcdPciExpressBaseSize()) {+ return (UINTN) ~0;+ } ASSERT > (((StartAddress & 0xFFF) + Size) <=3D 0x1000); if (Size =3D=3D 0) {-- > 2.27.0 > > > -=3D-=3D-=3D-=3D-=3D-=3D > Groups.io Links: You receive all messages sent to this group. > > View/Reply Online (#63115): https://edk2.groups.io/g/devel/message/63115 > Mute This Topic: https://groups.io/mt/75724107/1759384 > Group Owner: devel+owner@edk2.groups.io > Unsubscribe: https://edk2.groups.io/g/devel/unsub [liming.gao@intel.com] > -=3D-=3D-=3D-=3D-=3D-=3D > > --=20 *[Marcello Sylvester Bauer]* 9elements Agency GmbH, Kortumstra=C3=9Fe 19-21, 44787 Bochum, Germany Email: [DEINE EMAIL ADDRESSE] Phone: *+49 234 68 94 188 <+492346894188>* Mobile: *+49 1722847618 <+491722847618>* Sitz der Gesellschaft: Bochum Handelsregister: Amtsgericht Bochum, HRB 17519 Gesch=C3=A4ftsf=C3=BChrung: Sebastian Deutsch, Eray Basar Datenschutzhinweise nach Art. 13 DSGVO --000000000000272d0e05ab67d864 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Liming:
My mistake.=C2=A00x0FFFFFFF is= still a valid address offset so default PcdPciExpressBaseSize should be=C2= =A00x10000000.

Thanks,
Marcello

On Thu, Jul 23, 2020 at 12:04 PM G= ao, Liming <liming.gao@intel.com= > wrote:
=

-----Original Message-----
From: devel@edk2.= groups.io <devel@edk2.groups.io> On Behalf Of Marcello Sylvester Bauer
Sent: 2020=E5=B9=B47=E6=9C=8822=E6=97=A5 21:16
To: devel@edk2.gr= oups.io
Cc: Patrick Rudolph <patrick.rudolph@9elements.com>; Christian Walter <= ;christ= ian.walter@9elements.com>; Kinney, Michael D <michael.d.kinney@intel.com= >; Gao, Liming <liming.gao@intel.com>
Subject: [edk2-devel] [PATCH v3 2/3] MdePkg/BasePciExpressLib: Support vari= able size MMCONF

Add support for arbitrary sized MMCONF by introducing a new PCD.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Marcello Sylvester Bauer <marcello.bauer@9elements.com>
Cc: Patrick Rudolph <patrick.rudolph@9elements.com>
Cc: Christian Walter <christian.walter@9elements.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
---
=C2=A0MdePkg/MdePkg.dec=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 |=C2=A0 =C2=A04 +
=C2=A0MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf |=C2=A0 =C2=A0= 6 +-
=C2=A0MdePkg/Include/Library/PciExpressLib.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A05 +-
=C2=A0MdePkg/Library/BasePciExpressLib/PciExpressLib.c=C2=A0 =C2=A0 =C2=A0 = =C2=A0| 216 +++++++++++++++++---
=C2=A04 files changed, 193 insertions(+), 38 deletions(-)

diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index 73f6c2407357..02e7= 36a01126 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -2274,6 +2274,10 @@ [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynami= c, PcdsDynamicEx]
=C2=A0 =C2=A0# @Prompt PCI Express Base Address.=C2=A0 =C2=A0gEfiMdePkgToke= nSpaceGuid.PcdPciExpressBaseAddress|0xE0000000|UINT64|0x0000000a +=C2=A0 ##= This value is used to set the size of PCI express hierarchy. The default i= s 256 MB.+=C2=A0 # @Prompt PCI Express Base Size.+=C2=A0 gEfiMdePkgTokenSpa= ceGuid.PcdPciExpressBaseSize|0x0FFFFFFF|UINT64|0x0000000f+=C2=A0 =C2=A0## D= efault current ISO 639-2 language: English & French.=C2=A0 =C2=A0# @Pro= mpt Default Value of LangCodes Variable.=C2=A0 =C2=A0gEfiMdePkgTokenSpaceGu= id.PcdUefiVariableDefaultLangCodes|"engfraengfra"|VOID*|0x0000001= cdiff --git a/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf b/MdeP= kg/Library/BasePciExpressLib/BasePciExpressLib.inf

[Liming] 256M is 0x10000000. PCD value is 0x0FFFFFFF. Does it mean that the= default value is 256M - 1?

Thanks
Liming

index a7edb74cde71..12734b022ac7 100644
--- a/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
+++ b/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
@@ -1,7 +1,7 @@
=C2=A0## @file-#=C2=A0 Instance of PCI Express Library using the 256 MB PCI= Express MMIO window.+#=C2=A0 Instance of PCI Express Library using the var= iable size PCI Express MMIO window. #-#=C2=A0 PCI Express Library that uses= the 256 MB PCI Express MMIO window to perform+#=C2=A0 PCI Express Library = that uses the variable size PCI Express MMIO window to perform #=C2=A0 PCI = Configuration cycles. Layers on top of an I/O Library instance. # #=C2=A0 C= opyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>= @@ -38,4 +38,4 @@ [LibraryClasses]
=C2=A0 [Pcd]=C2=A0 =C2=A0gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress= =C2=A0 ## CONSUMES-+=C2=A0 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize= =C2=A0 ## CONSUMESdiff --git a/MdePkg/Include/Library/PciExpressLib.h b/Mde= Pkg/Include/Library/PciExpressLib.h
index 826fdcf7db6c..d78193a0a352 100644
--- a/MdePkg/Include/Library/PciExpressLib.h
+++ b/MdePkg/Include/Library/PciExpressLib.h
@@ -2,8 +2,9 @@
=C2=A0 =C2=A0Provides services to access PCI Configuration Space using the = MMIO PCI Express window.=C2=A0 =C2=A0 This library is identical to the PCI = Library, except the access method for performing PCI-=C2=A0 configuration c= ycles must be through the 256 MB PCI Express MMIO window whose base address= -=C2=A0 is defined by PcdPciExpressBaseAddress.+=C2=A0 configuration cycles= must be through the PCI Express MMIO window whose base address+=C2=A0 is d= efined by PcdPciExpressBaseAddress and size defined by PcdPciExpressBaseSiz= e.+=C2=A0 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved= .<BR> SPDX-License-Identifier: BSD-2-Clause-Patentdiff --git a/MdePkg= /Library/BasePciExpressLib/PciExpressLib.c b/MdePkg/Library/BasePciExpressL= ib/PciExpressLib.c
index 99a166c3609b..0311ecb3025f 100644
--- a/MdePkg/Library/BasePciExpressLib/PciExpressLib.c
+++ b/MdePkg/Library/BasePciExpressLib/PciExpressLib.c
@@ -22,7 +22,8 @@
=C2=A0 /**=C2=A0 =C2=A0Assert the validity of a PCI address. A valid PCI ad= dress should contain 1's-=C2=A0 only in the low 28 bits.+=C2=A0 only in= the low 28 bits. PcdPciExpressBaseSize limits the size to the real+=C2=A0 = number of PCI busses in this segment.=C2=A0 =C2=A0 @param=C2=A0 A The addre= ss to validate. @@ -79,6 +80,24 @@ GetPciExpressBaseAddress (
=C2=A0 =C2=A0return (VOID*)(UINTN) PcdGet64 (PcdPciExpressBaseAddress); } += /**+=C2=A0 Gets the size of PCI Express.++=C2=A0 This internal functions re= trieves PCI Express Base Size via a PCD entry+=C2=A0 PcdPciExpressBaseSize.= ++=C2=A0 @return The base size of PCI Express.++**/+STATIC+UINTN+PcdPciExpr= essBaseSize (+=C2=A0 VOID+=C2=A0 )+{+=C2=A0 return (UINTN) PcdGet64 (PcdPci= ExpressBaseSize);+}+ /**=C2=A0 =C2=A0Reads an 8-bit PCI configuration regis= ter. @@ -91,7 +110,8 @@ GetPciExpressBaseAddress (
=C2=A0 =C2=A0@param=C2=A0 Address The address that encodes the PCI Bus, Dev= ice, Function and=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0Register. -=C2=A0 @return The read value from the PCI configur= ation register.+=C2=A0 @retval 0xFF=C2=A0 Invalid PCI address.+=C2=A0 @retv= al other The read value from the PCI configuration register.=C2=A0 **/ UINT= 8@@ -101,6 +121,9 @@ PciExpressRead8 (
=C2=A0 =C2=A0) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+=C2=A0 i= f (Address >=3D PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT8) = ~0;+=C2=A0 }=C2=A0 =C2=A0return MmioRead8 ((UINTN) GetPciExpressBaseAddress= () + Address); } @@ -117,7 +140,8 @@ PciExpressRead8 (
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Regist= er.=C2=A0 =C2=A0@param=C2=A0 Value=C2=A0 =C2=A0The value to write. -=C2=A0 = @return The value written to the PCI configuration register.+=C2=A0 @retval= 0xFF=C2=A0 Invalid PCI address.+=C2=A0 @retval other The value written to = the PCI configuration register.=C2=A0 **/ UINT8@@ -128,6 +152,9 @@ PciExpre= ssWrite8 (
=C2=A0 =C2=A0) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+=C2=A0 i= f (Address >=3D PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT8) = ~0;+=C2=A0 }=C2=A0 =C2=A0return MmioWrite8 ((UINTN) GetPciExpressBaseAddres= s () + Address, Value); } @@ -148,7 +175,8 @@ PciExpressWrite8 (
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Regist= er.=C2=A0 =C2=A0@param=C2=A0 OrData=C2=A0 The value to OR with the PCI conf= iguration register. -=C2=A0 @return The value written back to the PCI confi= guration register.+=C2=A0 @retval 0xFF=C2=A0 Invalid PCI address.+=C2=A0 @r= etval other The value written to the PCI configuration register.=C2=A0 **/ = UINT8@@ -159,6 +187,9 @@ PciExpressOr8 (
=C2=A0 =C2=A0) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+=C2=A0 i= f (Address >=3D PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT8) = ~0;+=C2=A0 }=C2=A0 =C2=A0return MmioOr8 ((UINTN) GetPciExpressBaseAddress (= ) + Address, OrData); } @@ -179,7 +210,8 @@ PciExpressOr8 (
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Regist= er.=C2=A0 =C2=A0@param=C2=A0 AndData The value to AND with the PCI configur= ation register. -=C2=A0 @return The value written back to the PCI configura= tion register.+=C2=A0 @retval 0xFF=C2=A0 Invalid PCI address.+=C2=A0 @retva= l other The value written back to the PCI configuration register.=C2=A0 **/= UINT8@@ -190,6 +222,9 @@ PciExpressAnd8 (
=C2=A0 =C2=A0) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+=C2=A0 i= f (Address >=3D PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT8) = ~0;+=C2=A0 }=C2=A0 =C2=A0return MmioAnd8 ((UINTN) GetPciExpressBaseAddress = () + Address, AndData); } @@ -212,7 +247,8 @@ PciExpressAnd8 (
=C2=A0 =C2=A0@param=C2=A0 AndData The value to AND with the PCI configurati= on register.=C2=A0 =C2=A0@param=C2=A0 OrData=C2=A0 The value to OR with the= result of the AND operation. -=C2=A0 @return The value written back to the= PCI configuration register.+=C2=A0 @retval 0xFF=C2=A0 Invalid PCI address.= +=C2=A0 @retval other The value written back to the PCI configuration regis= ter.=C2=A0 **/ UINT8@@ -224,6 +260,9 @@ PciExpressAndThenOr8 (
=C2=A0 =C2=A0) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+=C2=A0 i= f (Address >=3D PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT8) = ~0;+=C2=A0 }=C2=A0 =C2=A0return MmioAndThenOr8 (=C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 (UINTN) GetPciExpressBaseAddress () + Address,=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 AndData,@@ -249,7 +288,9 @@ PciExpressAndThenOr= 8 (
=C2=A0 =C2=A0@param=C2=A0 EndBit=C2=A0 =C2=A0 The ordinal of the most signi= ficant bit in the bit field.=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Range 0..7. -=C2=A0 @return The value of the= bit field read from the PCI configuration register.+=C2=A0 @retval 0xFF=C2= =A0 Invalid PCI address.+=C2=A0 @retval other The value of the bit field re= ad from the PCI configuration+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 register.=C2=A0 **/ UINT8@@ -261,6 +302,9 @@ PciExpressBitFieldR= ead8 (
=C2=A0 =C2=A0) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+=C2=A0 i= f (Address >=3D PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT8) = ~0;+=C2=A0 }=C2=A0 =C2=A0return MmioBitFieldRead8 (=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 (UINTN) GetPciExpressBaseAddress () + Address,=C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 StartBit,@@ -289,7 +333,8 @@ PciExpressBitF= ieldRead8 (
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0Range 0..7.=C2=A0 =C2=A0@param=C2=A0 Value=C2=A0 =C2=A0 =C2=A0The new va= lue of the bit field. -=C2=A0 @return The value written back to the PCI con= figuration register.+=C2=A0 @retval 0xFF=C2=A0 Invalid PCI address.+=C2=A0 = @retval other The value written back to the PCI configuration register.=C2= =A0 **/ UINT8@@ -302,6 +347,9 @@ PciExpressBitFieldWrite8 (
=C2=A0 =C2=A0) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+=C2=A0 i= f (Address >=3D PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT8) = ~0;+=C2=A0 }=C2=A0 =C2=A0return MmioBitFieldWrite8 (=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 (UINTN) GetPciExpressBaseAddress () + Address,=C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 StartBit,@@ -334,7 +382,8 @@ PciExpressB= itFieldWrite8 (
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0Range 0..7.=C2=A0 =C2=A0@param=C2=A0 OrData=C2=A0 =C2=A0 The value to OR= with the PCI configuration register. -=C2=A0 @return The value written bac= k to the PCI configuration register.+=C2=A0 @retval 0xFF=C2=A0 Invalid PCI = address.+=C2=A0 @retval other The value written back to the PCI configurati= on register.=C2=A0 **/ UINT8@@ -347,6 +396,9 @@ PciExpressBitFieldOr8 (
=C2=A0 =C2=A0) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+=C2=A0 i= f (Address >=3D PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT8) = ~0;+=C2=A0 }=C2=A0 =C2=A0return MmioBitFieldOr8 (=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 (UINTN) GetPciExpressBaseAddress () + Address,=C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 StartBit,@@ -379,7 +431,8 @@ PciExpressBitF= ieldOr8 (
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0Range 0..7.=C2=A0 =C2=A0@param=C2=A0 AndData=C2=A0 =C2=A0The value to AN= D with the PCI configuration register. -=C2=A0 @return The value written ba= ck to the PCI configuration register.+=C2=A0 @retval 0xFF=C2=A0 Invalid PCI= address.+=C2=A0 @retval other The value written back to the PCI configurat= ion register.=C2=A0 **/ UINT8@@ -392,6 +445,9 @@ PciExpressBitFieldAnd8 ( =C2=A0 =C2=A0) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+=C2=A0 i= f (Address >=3D PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT8) = ~0;+=C2=A0 }=C2=A0 =C2=A0return MmioBitFieldAnd8 (=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 (UINTN) GetPciExpressBaseAddress () + Address,=C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 StartBit,@@ -428,7 +484,8 @@ PciExpressBitF= ieldAnd8 (
=C2=A0 =C2=A0@param=C2=A0 AndData=C2=A0 =C2=A0The value to AND with the PCI= configuration register.=C2=A0 =C2=A0@param=C2=A0 OrData=C2=A0 =C2=A0 The v= alue to OR with the result of the AND operation. -=C2=A0 @return The value = written back to the PCI configuration register.+=C2=A0 @retval 0xFF=C2=A0 I= nvalid PCI address.+=C2=A0 @retval other The value written back to the PCI = configuration register.=C2=A0 **/ UINT8@@ -442,6 +499,9 @@ PciExpressBitFie= ldAndThenOr8 (
=C2=A0 =C2=A0) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+=C2=A0 i= f (Address >=3D PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT8) = ~0;+=C2=A0 }=C2=A0 =C2=A0return MmioBitFieldAndThenOr8 (=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 (UINTN) GetPciExpressBaseAddress () + Address,=C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 StartBit,@@ -464,7 +524,8 @@ PciExpr= essBitFieldAndThenOr8 (
=C2=A0 =C2=A0@param=C2=A0 Address The address that encodes the PCI Bus, Dev= ice, Function and=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0Register. -=C2=A0 @return The read value from the PCI configur= ation register.+=C2=A0 @retval 0xFF=C2=A0 Invalid PCI address.+=C2=A0 @retv= al other The read value from the PCI configuration register.=C2=A0 **/ UINT= 16@@ -474,6 +535,9 @@ PciExpressRead16 (
=C2=A0 =C2=A0) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+=C2=A0 i= f (Address >=3D PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT16)= ~0;+=C2=A0 }=C2=A0 =C2=A0return MmioRead16 ((UINTN) GetPciExpressBaseAddre= ss () + Address); } @@ -491,7 +555,8 @@ PciExpressRead16 (
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Regist= er.=C2=A0 =C2=A0@param=C2=A0 Value=C2=A0 =C2=A0The value to write. -=C2=A0 = @return The value written to the PCI configuration register.+=C2=A0 @retval= 0xFFFF=C2=A0 Invalid PCI address.+=C2=A0 @retval other=C2=A0 =C2=A0The val= ue written to the PCI configuration register.=C2=A0 **/ UINT16@@ -502,6 +56= 7,9 @@ PciExpressWrite16 (
=C2=A0 =C2=A0) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+=C2=A0 i= f (Address >=3D PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT16)= ~0;+=C2=A0 }=C2=A0 =C2=A0return MmioWrite16 ((UINTN) GetPciExpressBaseAddr= ess () + Address, Value); } @@ -523,7 +591,8 @@ PciExpressWrite16 (
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Regist= er.=C2=A0 =C2=A0@param=C2=A0 OrData=C2=A0 The value to OR with the PCI conf= iguration register. -=C2=A0 @return The value written back to the PCI confi= guration register.+=C2=A0 @retval 0xFFFF=C2=A0 Invalid PCI address.+=C2=A0 = @retval other=C2=A0 =C2=A0The value written back to the PCI configuration r= egister.=C2=A0 **/ UINT16@@ -534,6 +603,9 @@ PciExpressOr16 (
=C2=A0 =C2=A0) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+=C2=A0 i= f (Address >=3D PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT16)= ~0;+=C2=A0 }=C2=A0 =C2=A0return MmioOr16 ((UINTN) GetPciExpressBaseAddress= () + Address, OrData); } @@ -555,7 +627,8 @@ PciExpressOr16 (
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Regist= er.=C2=A0 =C2=A0@param=C2=A0 AndData The value to AND with the PCI configur= ation register. -=C2=A0 @return The value written back to the PCI configura= tion register.+=C2=A0 @retval 0xFFFF=C2=A0 Invalid PCI address.+=C2=A0 @ret= val other=C2=A0 =C2=A0The value written back to the PCI configuration regis= ter.=C2=A0 **/ UINT16@@ -566,6 +639,9 @@ PciExpressAnd16 (
=C2=A0 =C2=A0) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+=C2=A0 i= f (Address >=3D PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT16)= ~0;+=C2=A0 }=C2=A0 =C2=A0return MmioAnd16 ((UINTN) GetPciExpressBaseAddres= s () + Address, AndData); } @@ -589,7 +665,8 @@ PciExpressAnd16 (
=C2=A0 =C2=A0@param=C2=A0 AndData The value to AND with the PCI configurati= on register.=C2=A0 =C2=A0@param=C2=A0 OrData=C2=A0 The value to OR with the= result of the AND operation. -=C2=A0 @return The value written back to the= PCI configuration register.+=C2=A0 @retval 0xFFFF=C2=A0 Invalid PCI addres= s.+=C2=A0 @retval other=C2=A0 =C2=A0The value written back to the PCI confi= guration register.=C2=A0 **/ UINT16@@ -601,6 +678,9 @@ PciExpressAndThenOr1= 6 (
=C2=A0 =C2=A0) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+=C2=A0 i= f (Address >=3D PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT16)= ~0;+=C2=A0 }=C2=A0 =C2=A0return MmioAndThenOr16 (=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 (UINTN) GetPciExpressBaseAddress () + Address,=C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 AndData,@@ -627,7 +707,9 @@ PciExpressAndTh= enOr16 (
=C2=A0 =C2=A0@param=C2=A0 EndBit=C2=A0 =C2=A0 The ordinal of the most signi= ficant bit in the bit field.=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Range 0..15. -=C2=A0 @return The value of th= e bit field read from the PCI configuration register.+=C2=A0 @retval 0xFFFF= =C2=A0 Invalid PCI address.+=C2=A0 @retval other=C2=A0 =C2=A0The value of t= he bit field read from the PCI configuration+=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 register.=C2=A0 **/ UINT16@@ -639,6 +721= ,9 @@ PciExpressBitFieldRead16 (
=C2=A0 =C2=A0) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+=C2=A0 i= f (Address >=3D PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT16)= ~0;+=C2=A0 }=C2=A0 =C2=A0return MmioBitFieldRead16 (=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 (UINTN) GetPciExpressBaseAddress () + Address,=C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 StartBit,@@ -668,7 +753,8 @@ PciExpressB= itFieldRead16 (
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0Range 0..15.=C2=A0 =C2=A0@param=C2=A0 Value=C2=A0 =C2=A0 =C2=A0The new v= alue of the bit field. -=C2=A0 @return The value written back to the PCI co= nfiguration register.+=C2=A0 @retval 0xFFFF=C2=A0 Invalid PCI address.+=C2= =A0 @retval other=C2=A0 =C2=A0The value written back to the PCI configurati= on register.=C2=A0 **/ UINT16@@ -681,6 +767,9 @@ PciExpressBitFieldWrite16 = (
=C2=A0 =C2=A0) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+=C2=A0 i= f (Address >=3D PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT16)= ~0;+=C2=A0 }=C2=A0 =C2=A0return MmioBitFieldWrite16 (=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 (UINTN) GetPciExpressBaseAddress () + Address,=C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 StartBit,@@ -714,7 +803,8 @@ PciExpressB= itFieldWrite16 (
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0Range 0..15.=C2=A0 =C2=A0@param=C2=A0 OrData=C2=A0 =C2=A0 The value to O= R with the PCI configuration register. -=C2=A0 @return The value written ba= ck to the PCI configuration register.+=C2=A0 @retval 0xFFFF=C2=A0 Invalid P= CI address.+=C2=A0 @retval other=C2=A0 =C2=A0The value written back to the = PCI configuration register.=C2=A0 **/ UINT16@@ -727,6 +817,9 @@ PciExpressB= itFieldOr16 (
=C2=A0 =C2=A0) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+=C2=A0 i= f (Address >=3D PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT16)= ~0;+=C2=A0 }=C2=A0 =C2=A0return MmioBitFieldOr16 (=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 (UINTN) GetPciExpressBaseAddress () + Address,=C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 StartBit,@@ -760,7 +853,8 @@ PciExpressBitF= ieldOr16 (
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0Range 0..15.=C2=A0 =C2=A0@param=C2=A0 AndData=C2=A0 =C2=A0The value to A= ND with the PCI configuration register. -=C2=A0 @return The value written b= ack to the PCI configuration register.+=C2=A0 @retval 0xFFFF=C2=A0 Invalid = PCI address.+=C2=A0 @retval other=C2=A0 =C2=A0The value written back to the= PCI configuration register.=C2=A0 **/ UINT16@@ -773,6 +867,9 @@ PciExpress= BitFieldAnd16 (
=C2=A0 =C2=A0) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+=C2=A0 i= f (Address >=3D PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT16)= ~0;+=C2=A0 }=C2=A0 =C2=A0return MmioBitFieldAnd16 (=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 (UINTN) GetPciExpressBaseAddress () + Address,=C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 StartBit,@@ -810,7 +907,8 @@ PciExpressB= itFieldAnd16 (
=C2=A0 =C2=A0@param=C2=A0 AndData=C2=A0 =C2=A0The value to AND with the PCI= configuration register.=C2=A0 =C2=A0@param=C2=A0 OrData=C2=A0 =C2=A0 The v= alue to OR with the result of the AND operation. -=C2=A0 @return The value = written back to the PCI configuration register.+=C2=A0 @retval 0xFFFF=C2=A0= Invalid PCI address.+=C2=A0 @retval other=C2=A0 =C2=A0The value written ba= ck to the PCI configuration register.=C2=A0 **/ UINT16@@ -824,6 +922,9 @@ P= ciExpressBitFieldAndThenOr16 (
=C2=A0 =C2=A0) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+=C2=A0 i= f (Address >=3D PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT16)= ~0;+=C2=A0 }=C2=A0 =C2=A0return MmioBitFieldAndThenOr16 (=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 (UINTN) GetPciExpressBaseAddress () + Address,=C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 StartBit,@@ -846,7 +947,8 @@ PciExpr= essBitFieldAndThenOr16 (
=C2=A0 =C2=A0@param=C2=A0 Address The address that encodes the PCI Bus, Dev= ice, Function and=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0Register. -=C2=A0 @return The read value from the PCI configur= ation register.+=C2=A0 @retval 0xFFFF=C2=A0 Invalid PCI address.+=C2=A0 @re= tval other=C2=A0 =C2=A0The read value from the PCI configuration register.= =C2=A0 **/ UINT32@@ -856,6 +958,9 @@ PciExpressRead32 (
=C2=A0 =C2=A0) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+=C2=A0 i= f (Address >=3D PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT32)= ~0;+=C2=A0 }=C2=A0 =C2=A0return MmioRead32 ((UINTN) GetPciExpressBaseAddre= ss () + Address); } @@ -873,7 +978,8 @@ PciExpressRead32 (
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Regist= er.=C2=A0 =C2=A0@param=C2=A0 Value=C2=A0 =C2=A0The value to write. -=C2=A0 = @return The value written to the PCI configuration register.+=C2=A0 @retval= 0xFFFFFFFF=C2=A0 Invalid PCI address.+=C2=A0 @retval other=C2=A0 =C2=A0 = =C2=A0 =C2=A0The value written to the PCI configuration register.=C2=A0 **/= UINT32@@ -884,6 +990,9 @@ PciExpressWrite32 (
=C2=A0 =C2=A0) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+=C2=A0 i= f (Address >=3D PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT32)= ~0;+=C2=A0 }=C2=A0 =C2=A0return MmioWrite32 ((UINTN) GetPciExpressBaseAddr= ess () + Address, Value); } @@ -905,7 +1014,8 @@ PciExpressWrite32 (
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Regist= er.=C2=A0 =C2=A0@param=C2=A0 OrData=C2=A0 The value to OR with the PCI conf= iguration register. -=C2=A0 @return The value written back to the PCI confi= guration register.+=C2=A0 @retval 0xFFFFFFFF=C2=A0 Invalid PCI address.+=C2= =A0 @retval other=C2=A0 =C2=A0 =C2=A0 =C2=A0The value written back to the P= CI configuration register.=C2=A0 **/ UINT32@@ -916,6 +1026,9 @@ PciExpressO= r32 (
=C2=A0 =C2=A0) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+=C2=A0 i= f (Address >=3D PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT32)= ~0;+=C2=A0 }=C2=A0 =C2=A0return MmioOr32 ((UINTN) GetPciExpressBaseAddress= () + Address, OrData); } @@ -937,7 +1050,8 @@ PciExpressOr32 (
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Regist= er.=C2=A0 =C2=A0@param=C2=A0 AndData The value to AND with the PCI configur= ation register. -=C2=A0 @return The value written back to the PCI configura= tion register.+=C2=A0 @retval 0xFFFFFFFF=C2=A0 Invalid PCI address.+=C2=A0 = @retval other=C2=A0 =C2=A0 =C2=A0 =C2=A0The value written back to the PCI c= onfiguration register.=C2=A0 **/ UINT32@@ -948,6 +1062,9 @@ PciExpressAnd32= (
=C2=A0 =C2=A0) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+=C2=A0 i= f (Address >=3D PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT32)= ~0;+=C2=A0 }=C2=A0 =C2=A0return MmioAnd32 ((UINTN) GetPciExpressBaseAddres= s () + Address, AndData); } @@ -971,7 +1088,8 @@ PciExpressAnd32 (
=C2=A0 =C2=A0@param=C2=A0 AndData The value to AND with the PCI configurati= on register.=C2=A0 =C2=A0@param=C2=A0 OrData=C2=A0 The value to OR with the= result of the AND operation. -=C2=A0 @return The value written back to the= PCI configuration register.+=C2=A0 @retval 0xFFFFFFFF=C2=A0 Invalid PCI ad= dress.+=C2=A0 @retval other=C2=A0 =C2=A0 =C2=A0 =C2=A0The value written bac= k to the PCI configuration register.=C2=A0 **/ UINT32@@ -983,6 +1101,9 @@ P= ciExpressAndThenOr32 (
=C2=A0 =C2=A0) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+=C2=A0 i= f (Address >=3D PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT32)= ~0;+=C2=A0 }=C2=A0 =C2=A0return MmioAndThenOr32 (=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 (UINTN) GetPciExpressBaseAddress () + Address,=C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 AndData,@@ -1009,7 +1130,9 @@ PciExpressAnd= ThenOr32 (
=C2=A0 =C2=A0@param=C2=A0 EndBit=C2=A0 =C2=A0 The ordinal of the most signi= ficant bit in the bit field.=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Range 0..31. -=C2=A0 @return The value of th= e bit field read from the PCI configuration register.+=C2=A0 @retval 0xFFFF= FFFF=C2=A0 Invalid PCI address.+=C2=A0 @retval other=C2=A0 =C2=A0 =C2=A0 = =C2=A0The value of the bit field read from the PCI+=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 configuration register= .=C2=A0 **/ UINT32@@ -1021,6 +1144,9 @@ PciExpressBitFieldRead32 (
=C2=A0 =C2=A0) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+=C2=A0 i= f (Address >=3D PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT32)= ~0;+=C2=A0 }=C2=A0 =C2=A0return MmioBitFieldRead32 (=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 (UINTN) GetPciExpressBaseAddress () + Address,=C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 StartBit,@@ -1050,7 +1176,8 @@ PciExpres= sBitFieldRead32 (
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0Range 0..31.=C2=A0 =C2=A0@param=C2=A0 Value=C2=A0 =C2=A0 =C2=A0The new v= alue of the bit field. -=C2=A0 @return The value written back to the PCI co= nfiguration register.+=C2=A0 @retval 0xFFFFFFFF=C2=A0 Invalid PCI address.+= =C2=A0 @retval other=C2=A0 =C2=A0 =C2=A0 =C2=A0The value written back to th= e PCI configuration register.=C2=A0 **/ UINT32@@ -1063,6 +1190,9 @@ PciExpr= essBitFieldWrite32 (
=C2=A0 =C2=A0) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+=C2=A0 i= f (Address >=3D PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT32)= ~0;+=C2=A0 }=C2=A0 =C2=A0return MmioBitFieldWrite32 (=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 (UINTN) GetPciExpressBaseAddress () + Address,=C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 StartBit,@@ -1096,7 +1226,8 @@ PciExpres= sBitFieldWrite32 (
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0Range 0..31.=C2=A0 =C2=A0@param=C2=A0 OrData=C2=A0 =C2=A0 The value to O= R with the PCI configuration register. -=C2=A0 @return The value written ba= ck to the PCI configuration register.+=C2=A0 @retval 0xFFFFFFFF=C2=A0 Inval= id PCI address.+=C2=A0 @retval other=C2=A0 =C2=A0 =C2=A0 =C2=A0The value wr= itten back to the PCI configuration register.=C2=A0 **/ UINT32@@ -1109,6 +1= 240,9 @@ PciExpressBitFieldOr32 (
=C2=A0 =C2=A0) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+=C2=A0 i= f (Address >=3D PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT32)= ~0;+=C2=A0 }=C2=A0 =C2=A0return MmioBitFieldOr32 (=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 (UINTN) GetPciExpressBaseAddress () + Address,=C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 StartBit,@@ -1142,7 +1276,8 @@ PciExpressBi= tFieldOr32 (
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0Range 0..31.=C2=A0 =C2=A0@param=C2=A0 AndData=C2=A0 =C2=A0The value to A= ND with the PCI configuration register. -=C2=A0 @return The value written b= ack to the PCI configuration register.+=C2=A0 @retval 0xFFFFFFFF=C2=A0 Inva= lid PCI address.+=C2=A0 @retval other=C2=A0 =C2=A0 =C2=A0 =C2=A0The value w= ritten back to the PCI configuration register.=C2=A0 **/ UINT32@@ -1155,6 += 1290,9 @@ PciExpressBitFieldAnd32 (
=C2=A0 =C2=A0) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+=C2=A0 i= f (Address >=3D PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT32)= ~0;+=C2=A0 }=C2=A0 =C2=A0return MmioBitFieldAnd32 (=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 (UINTN) GetPciExpressBaseAddress () + Address,=C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 StartBit,@@ -1192,7 +1330,8 @@ PciExpres= sBitFieldAnd32 (
=C2=A0 =C2=A0@param=C2=A0 AndData=C2=A0 =C2=A0The value to AND with the PCI= configuration register.=C2=A0 =C2=A0@param=C2=A0 OrData=C2=A0 =C2=A0 The v= alue to OR with the result of the AND operation. -=C2=A0 @return The value = written back to the PCI configuration register.+=C2=A0 @retval 0xFFFFFFFF= =C2=A0 Invalid PCI address.+=C2=A0 @retval other=C2=A0 =C2=A0 =C2=A0 =C2=A0= The value written back to the PCI configuration register.=C2=A0 **/ UINT32@= @ -1206,6 +1345,9 @@ PciExpressBitFieldAndThenOr32 (
=C2=A0 =C2=A0) {=C2=A0 =C2=A0ASSERT_INVALID_PCI_ADDRESS (Address);+=C2=A0 i= f (Address >=3D PcdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINT32)= ~0;+=C2=A0 }=C2=A0 =C2=A0return MmioBitFieldAndThenOr32 (=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 (UINTN) GetPciExpressBaseAddress () + Address,=C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 StartBit,@@ -1235,7 +1377,8 @@ PciEx= pressBitFieldAndThenOr32 (
=C2=A0 =C2=A0@param=C2=A0 Size=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 The size i= n bytes of the transfer.=C2=A0 =C2=A0@param=C2=A0 Buffer=C2=A0 =C2=A0 =C2= =A0 =C2=A0 The pointer to a buffer receiving the data read. -=C2=A0 @return= Size read data from StartAddress.+=C2=A0 @retval (UINTN)~0=C2=A0 Invalid P= CI address.+=C2=A0 @retval other=C2=A0 =C2=A0 =C2=A0 Size read data from St= artAddress.=C2=A0 **/ UINTN@@ -1249,6 +1392,9 @@ PciExpressReadBuffer (
=C2=A0 =C2=A0UINTN=C2=A0 =C2=A0ReturnValue;=C2=A0 =C2=A0 ASSERT_INVALID_PCI= _ADDRESS (StartAddress);+=C2=A0 if (StartAddress >=3D PcdPciExpressBaseS= ize()) {+=C2=A0 =C2=A0 return (UINTN) ~0;+=C2=A0 }=C2=A0 =C2=A0ASSERT (((St= artAddress & 0xFFF) + Size) <=3D 0x1000);=C2=A0 =C2=A0 if (Size =3D= =3D 0) {@@ -1335,7 +1481,8 @@ PciExpressReadBuffer (
=C2=A0 =C2=A0@param=C2=A0 Size=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 The size i= n bytes of the transfer.=C2=A0 =C2=A0@param=C2=A0 Buffer=C2=A0 =C2=A0 =C2= =A0 =C2=A0 The pointer to a buffer containing the data to write. -=C2=A0 @r= eturn Size written to StartAddress.+=C2=A0 @retval (UINTN)~0=C2=A0 Invalid = PCI address.+=C2=A0 @retval other=C2=A0 =C2=A0 =C2=A0 Size written to Start= Address.=C2=A0 **/ UINTN@@ -1349,6 +1496,9 @@ PciExpressWriteBuffer (
=C2=A0 =C2=A0UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ReturnValue;=C2=A0 =C2=A0 A= SSERT_INVALID_PCI_ADDRESS (StartAddress);+=C2=A0 if (StartAddress >=3D P= cdPciExpressBaseSize()) {+=C2=A0 =C2=A0 return (UINTN) ~0;+=C2=A0 }=C2=A0 = =C2=A0ASSERT (((StartAddress & 0xFFF) + Size) <=3D 0x1000);=C2=A0 = =C2=A0 if (Size =3D=3D 0) {--
2.27.0


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