From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id D50DDD80122 for ; Wed, 11 Oct 2023 05:25:55 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=HRRpVOeu8nnjfzndVJ8NdQi4lLLmF0N2mKAK+k1iBq0=; c=relaxed/simple; d=groups.io; h=MIME-Version:References:In-Reply-To:From:Date:Message-ID:Subject:To:Cc:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Transfer-Encoding; s=20140610; t=1697001954; v=1; b=strlae/IhZz5SVX4UD1MOS8XNfcWRi4FedmHNjmYwSgR15YWRIV2+lgXhQK5caEUnOnxa3pX dCFcrLss4WdFY+PDlcFcDgPD948wECztk9v2/FcZS3mpbcIPlADzHvgxskaUGsBpnfYbClpqx5t uTdy8RU/86BArVLHXDzVDipc= X-Received: by 127.0.0.2 with SMTP id x8bnYY7687511xYB58Oz1hPU; Tue, 10 Oct 2023 22:25:54 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.10254.1697001953520171486 for ; Tue, 10 Oct 2023 22:25:54 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 422791477 for ; Tue, 10 Oct 2023 22:26:33 -0700 (PDT) X-Received: from mail-yb1-f179.google.com (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6CC553F917 for ; Tue, 10 Oct 2023 22:25:52 -0700 (PDT) X-Received: by mail-yb1-f179.google.com with SMTP id 3f1490d57ef6-d745689bd71so1594569276.0 for ; Tue, 10 Oct 2023 22:25:52 -0700 (PDT) X-Gm-Message-State: U3AeDX0PC993BthToqroxKfzx7686176AA= X-Google-Smtp-Source: AGHT+IGb5hAhIX+WJNJ4OdJWKZg3xwsNsf5gXmgLusk/6glN6wZXb3qT38hSX3ZjWZnaBLlbdXb7Mx3HCCQdr5wRInY= X-Received: by 2002:a25:a529:0:b0:d49:6718:433c with SMTP id h38-20020a25a529000000b00d496718433cmr13544872ybi.6.1697001951816; Tue, 10 Oct 2023 22:25:51 -0700 (PDT) MIME-Version: 1.0 References: <20230823110318.826467-1-sahil@arm.com> In-Reply-To: <20230823110318.826467-1-sahil@arm.com> From: "chandni cherukuri" Date: Wed, 11 Oct 2023 10:55:34 +0530 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [edk2-devel] [edk2-platforms][PATCH V3 1/1] Platform/ARM/N1sdp: Add support to parse NT_FW_CONFIG To: devel@edk2.groups.io, sahil@arm.com Cc: Ard Biesheuvel , quic_llindhol@quicinc.com, Sami Mujawar Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chandni.cherukuri@arm.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b="strlae/I"; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=arm.com (policy=none) Hi Sahil, These changes look good to me. Reviewed-by: Chandni Cherukuri Regards, Chandni Cherukuri On Wed, Aug 23, 2023 at 4:33=E2=80=AFPM sahil wrote: > > NT_FW_CONFIG DTB contains platform information passed by > Tf-A boot stage. > This information is used for Virtual memory map generation > during PEI phase and passed on to DXE phase as a HOB, where > it is used in ConfigurationManagerDxe. > > This patch adds a PEI to parse NT_FW_CONFIG and pass it to > other PEI modules(as PPI) and DXE modules(as HOB). > > Signed-off-by: sahil > --- > > Notes: > v3: > - Fixed code review comments > - Added a PEI to parse nt_fw_config > > Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec = | 8 +- > Platform/ARM/N1Sdp/N1SdpPlatform.dsc = | 5 +- > Platform/ARM/N1Sdp/N1SdpPlatform.fdf = | 3 +- > Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Configur= ationManagerDxe.inf | 6 +- > Platform/ARM/N1Sdp/Drivers/N1SdpNtFwConfigPei/NtFwConfigPei.inf = | 41 ++++++ > Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf = | 8 +- > Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h = | 14 +-- > Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Configur= ationManager.c | 24 ++-- > Platform/ARM/N1Sdp/Drivers/N1SdpNtFwConfigPei/NtFwConfigPei.c = | 133 ++++++++++++++++++++ > Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c = | 12 +- > Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c = | 33 +++-- > Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S = | 4 +- > 12 files changed, 255 insertions(+), 36 deletions(-) > > diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/Ne= overseN1Soc/NeoverseN1Soc.dec > index d59f25a5b915..7118da25dce0 100644 > --- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec > +++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec > @@ -1,7 +1,7 @@ > ## @file > # Describes the entire platform configuration. > # > -# Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.
> +# Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > @@ -22,6 +22,8 @@ > Include # Root include for the package > > [Guids.common] > + # ARM NeoverseN1Soc Platform Info descriptor > + gArmNeoverseN1SocPlatformInfoDescriptorGuid =3D { 0x9fa16eb5, 0xce13, = 0x4d37, { 0x96, 0xf0, 0x0a, 0xb5, 0xf1, 0xab, 0xff, 0x01 } } > gArmNeoverseN1SocTokenSpaceGuid =3D { 0xab93eb78, 0x60d7, 0x4099, { 0x= ac, 0xeb, 0x6d, 0xb5, 0x02, 0x58, 0x7c, 0x24 } } > > [PcdsFixedAtBuild] > @@ -83,3 +85,7 @@ > gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x40000= 000000|UINT64|0x0000004F > gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000= 000000|UINT64|0x00000050 > gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieSegmentNumber|2|UINT32|0x= 00000051 > + > +[Ppis] > + gArmNeoverseN1SocPlatformInfoDescriptorPpiGuid =3D { 0x21D04AD4, 0x4D2= 3, 0x426D, { 0x8D, 0x3E, 0x92, 0x23, 0x3E, 0xF4, 0xB9, 0x5E } } > + gArmNeoverseN1SocParameterPpiGuid =3D { 0x4DDD5A72, 0x31AD, 0x4B20, { = 0x8F, 0x5F, 0xB3, 0xE8, 0x24, 0x6F, 0x80, 0x2B } } > diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1= SdpPlatform.dsc > index d04b22d3ef51..691d1af3c25c 100644 > --- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc > +++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc > @@ -4,7 +4,7 @@ > # This provides platform specific component descriptions and libraries t= hat > # conform to EFI/Framework standards. > # > -# Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.
> +# Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > @@ -228,6 +228,9 @@ > # Platform driver > Platform/ARM/N1Sdp/Drivers/PlatformDxe/PlatformDxe.inf > > + # PEI Phase modules > + Platform/ARM/N1Sdp/Drivers/N1SdpNtFwConfigPei/NtFwConfigPei.inf > + > # Human Interface Support > MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf > > diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.fdf b/Platform/ARM/N1Sdp/N1= SdpPlatform.fdf > index e5e24ea50294..baac8a3ef727 100644 > --- a/Platform/ARM/N1Sdp/N1SdpPlatform.fdf > +++ b/Platform/ARM/N1Sdp/N1SdpPlatform.fdf > @@ -1,7 +1,7 @@ > ## @file > # FDF file of N1Sdp > # > -# Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.
> +# Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent > ## > @@ -195,6 +195,7 @@ READ_LOCK_STATUS =3D TRUE > INF MdeModulePkg/Core/Pei/PeiMain.inf > INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf > INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf > + INF Platform/ARM/N1Sdp/Drivers/N1SdpNtFwConfigPei/NtFwConfigPei.inf > > FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { > SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUI= RED =3D TRUE { > diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManager= Dxe/ConfigurationManagerDxe.inf b/Platform/ARM/N1Sdp/ConfigurationManager/C= onfigurationManagerDxe/ConfigurationManagerDxe.inf > index 4f8e7f13021a..242490caf860 100644 > --- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Con= figurationManagerDxe.inf > +++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Con= figurationManagerDxe.inf > @@ -1,7 +1,7 @@ > ## @file > # Configuration Manager Dxe > # > -# Copyright (c) 2021, ARM Limited. All rights reserved.
> +# Copyright (c) 2021 - 2023, ARM Limited. All rights reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > @@ -42,6 +42,7 @@ > > [LibraryClasses] > ArmPlatformLib > + HobLib > PrintLib > UefiBootServicesTableLib > UefiDriverEntryPoint > @@ -170,5 +171,8 @@ > gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation > gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieSegmentNumber > > +[Guids] > + gArmNeoverseN1SocPlatformInfoDescriptorGuid > + > [Depex] > TRUE > diff --git a/Platform/ARM/N1Sdp/Drivers/N1SdpNtFwConfigPei/NtFwConfigPei.= inf b/Platform/ARM/N1Sdp/Drivers/N1SdpNtFwConfigPei/NtFwConfigPei.inf > new file mode 100644 > index 000000000000..2eec8c327205 > --- /dev/null > +++ b/Platform/ARM/N1Sdp/Drivers/N1SdpNtFwConfigPei/NtFwConfigPei.inf > @@ -0,0 +1,41 @@ > +## @file > +# This PEI module parse the NtFwConfig for N1Sdp platform and produce > +# the PPI and HOB. > +# > +# Copyright (c) 2023, ARM Limited. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +[Defines] > + INF_VERSION =3D 0x0001001B > + BASE_NAME =3D N1SdpNtFwConfigPei > + FILE_GUID =3D CE76D56C-D3A5-4763-9138-DF09E1D1B61= 4 > + MODULE_TYPE =3D PEIM > + VERSION_STRING =3D 1.0 > + ENTRY_POINT =3D Load > + > +[Sources] > + NtFwConfigPei.c > + > +[Packages] > + EmbeddedPkg/EmbeddedPkg.dec > + MdePkg/MdePkg.dec > + Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec > + > +[LibraryClasses] > + DebugLib > + FdtLib > + HobLib > + PeimEntryPoint > + > +[Ppis] > + gArmNeoverseN1SocPlatformInfoDescriptorPpiGuid > + gArmNeoverseN1SocParameterPpiGuid > + > +[Guids] > + gArmNeoverseN1SocPlatformInfoDescriptorGuid > + > +[Depex] > + gArmNeoverseN1SocParameterPpiGuid > diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.in= f b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf > index 96e590cdd810..6e7e16b86838 100644 > --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf > +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf > @@ -1,7 +1,7 @@ > ## @file > # Platform Library for N1Sdp. > # > -# Copyright (c) 2018-2021, ARM Limited. All rights reserved.
> +# Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > @@ -58,8 +58,8 @@ > > gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress > > -[Guids] > - gEfiHobListGuid ## CONSUMES ## SystemTable > - > [Ppis] > gArmMpCoreInfoPpiGuid > + gArmNeoverseN1SocParameterPpiGuid > + gArmNeoverseN1SocPlatformInfoDescriptorPpiGuid > + > diff --git a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h b/Silicon/= ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h > index 097160c7e2d1..2f83d582ccf3 100644 > --- a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h > +++ b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h > @@ -1,6 +1,6 @@ > /** @file > * > -* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. > +* Copyright (c) 2018 - 2023, ARM Limited. All rights reserved. > * > * SPDX-License-Identifier: BSD-2-Clause-Patent > * > @@ -41,11 +41,6 @@ > #define NEOVERSEN1SOC_EXP_PERIPH_BASE0 0x1C000000 > #define NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ 0x1300000 > > -// Base address to a structure of type NEOVERSEN1SOC_PLAT_INFO which is > -// pre-populated by a earlier boot stage > -#define NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE (NEOVERSEN1SOC_NON_= SECURE_SRAM_BASE + \ > - 0x00008000) > - > /* > * Platform information structure stored in Non-secure SRAM. Platform > * information are passed from the trusted firmware with the below struc= ture > @@ -55,12 +50,15 @@ > typedef struct { > /*! 0 - Single Chip, 1 - Chip to Chip (C2C) */ > UINT8 MultichipMode; > - /*! Slave count in C2C mode */ > - UINT8 SlaveCount; > + /*! Secondary chip count in C2C mode */ > + UINT8 SecondaryChipCount; > /*! Local DDR memory size in GigaBytes */ > UINT8 LocalDdrSize; > /*! Remote DDR memory size in GigaBytes */ > UINT8 RemoteDdrSize; > } NEOVERSEN1SOC_PLAT_INFO; > > +typedef struct { > + CONST VOID *NtFwConfig; > +} NEOVERSEN1SOC_EL3_FW_HANDOFF_PARAM_PPI; > #endif > diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManager= Dxe/ConfigurationManager.c b/Platform/ARM/N1Sdp/ConfigurationManager/Config= urationManagerDxe/ConfigurationManager.c > index fa6408a7dd1e..e248826ec925 100644 > --- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Con= figurationManager.c > +++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Con= figurationManager.c > @@ -1,7 +1,7 @@ > /** @file > Configuration Manager Dxe > > - Copyright (c) 2021, ARM Limited. All rights reserved.
> + Copyright (c) 2021 - 2023, ARM Limited. All rights reserved.
> > SPDX-License-Identifier: BSD-2-Clause-Patent > > @@ -16,6 +16,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -28,6 +29,7 @@ > #include "Platform.h" > > extern struct EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat; > +static NEOVERSEN1SOC_PLAT_INFO *PlatInfo; > > /** The platform configuration repository information. > */ > @@ -1242,13 +1244,21 @@ InitializePlatformRepository ( > IN EDKII_PLATFORM_REPOSITORY_INFO * CONST PlatRepoInfo > ) > { > - NEOVERSEN1SOC_PLAT_INFO *PlatInfo; > UINT64 Dram2Size; > UINT64 RemoteDdrSize; > + VOID *PlatInfoHob; > + > + PlatInfoHob =3D GetFirstGuidHob (&gArmNeoverseN1SocPlatformInfoDescrip= torGuid); > + > + if (PlatInfoHob =3D=3D NULL) { > + DEBUG ((DEBUG_ERROR, "Platform HOB is NULL\n")); > + return EFI_NOT_FOUND; > + } > + > + PlatInfo =3D (NEOVERSEN1SOC_PLAT_INFO *)GET_GUID_HOB_DATA (PlatInfoHob= ); > > RemoteDdrSize =3D 0; > > - PlatInfo =3D (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT= _BASE; > Dram2Size =3D ((PlatInfo->LocalDdrSize - 2) * SIZE_1GB); > > PlatRepoInfo->MemAffInfo[LOCAL_DDR_REGION2].Length =3D Dram2Size; > @@ -1512,7 +1522,6 @@ GetGicCInfo ( > ) > { > EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo; > - NEOVERSEN1SOC_PLAT_INFO *PlatInfo; > UINT32 TotalObjCount; > UINT32 ObjIndex; > > @@ -1523,7 +1532,6 @@ GetGicCInfo ( > } > > PlatformRepo =3D This->PlatRepoInfo; > - PlatInfo =3D (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT= _BASE; > > if (PlatInfo->MultichipMode =3D=3D 1) { > TotalObjCount =3D PLAT_CPU_COUNT * 2; > @@ -1623,7 +1631,6 @@ GetStandardNameSpaceObject ( > { > EFI_STATUS Status; > EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo; > - NEOVERSEN1SOC_PLAT_INFO *PlatInfo; > UINT32 AcpiTableCount; > > if ((This =3D=3D NULL) || (CmObject =3D=3D NULL)) { > @@ -1634,7 +1641,7 @@ GetStandardNameSpaceObject ( > > Status =3D EFI_NOT_FOUND; > PlatformRepo =3D This->PlatRepoInfo; > - PlatInfo =3D (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT= _BASE; > + > AcpiTableCount =3D ARRAY_SIZE (PlatformRepo->CmAcpiTableList); > if (PlatInfo->MultichipMode =3D=3D 0) > AcpiTableCount -=3D 1; > @@ -1697,7 +1704,6 @@ GetArmNameSpaceObject ( > { > EFI_STATUS Status; > EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo; > - NEOVERSEN1SOC_PLAT_INFO *PlatInfo; > UINT32 GicRedistCount; > UINT32 GicCpuCount; > UINT32 ProcHierarchyInfoCount; > @@ -1718,8 +1724,6 @@ GetArmNameSpaceObject ( > Status =3D EFI_NOT_FOUND; > PlatformRepo =3D This->PlatRepoInfo; > > - // Probe for multi chip information > - PlatInfo =3D (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT= _BASE; > if (PlatInfo->MultichipMode =3D=3D 1) { > GicRedistCount =3D 2; > GicCpuCount =3D PLAT_CPU_COUNT * 2; > diff --git a/Platform/ARM/N1Sdp/Drivers/N1SdpNtFwConfigPei/NtFwConfigPei.= c b/Platform/ARM/N1Sdp/Drivers/N1SdpNtFwConfigPei/NtFwConfigPei.c > new file mode 100644 > index 000000000000..ff6a6a7933c3 > --- /dev/null > +++ b/Platform/ARM/N1Sdp/Drivers/N1SdpNtFwConfigPei/NtFwConfigPei.c > @@ -0,0 +1,133 @@ > +/** @file > + > + Copyright (c) 2023, ARM Limited. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > +#include > +#include > + > +#include > +#include > + > +STATIC EFI_PEI_PPI_DESCRIPTOR gPpi; > + > +/** > + The entrypoint of the module, parse NtFwConfig and produce the PPI and= HOB. > + > + @param[in] FileHandle Handle of the file being invoked. > + @param[in] PeiServices Describes the list of possible PEI Services. > + > + @retval EFI_SUCCESS Either no NT_FW_CONFIG was given by EL3 firmw= are > + OR the N1Sdp FDT HOB was successfully created= . > + @retval EFI_UNSUPPORTED FDT header sanity check failed. > + @retval * Other errors are possible. > +**/ > + > +EFI_STATUS > +EFIAPI > +Load ( > + IN EFI_PEI_FILE_HANDLE FileHandle, > + IN CONST EFI_PEI_SERVICES **PeiServices > + ) > +{ > + CONST NEOVERSEN1SOC_EL3_FW_HANDOFF_PARAM_PPI *ParamPpi; > + CONST UINT32 *Property; > + INT32 Offset; > + NEOVERSEN1SOC_PLAT_INFO *PlatInfo; > + INT32 Status; > + > + PlatInfo =3D BuildGuidHob ( > + &gArmNeoverseN1SocPlatformInfoDescriptorGuid, > + sizeof (*PlatInfo) > + ); > + > + if (PlatInfo =3D=3D NULL) { > + DEBUG (( > + DEBUG_ERROR, > + "[%a]: failed to allocate platform info HOB\n", > + gEfiCallerBaseName > + )); > + return EFI_INVALID_PARAMETER; > + } > + > + Status =3D PeiServicesLocatePpi ( > + &gArmNeoverseN1SocParameterPpiGuid, > + 0, > + NULL, > + (VOID **)&ParamPpi > + ); > + > + if (EFI_ERROR (Status)) { > + DEBUG (( > + DEBUG_ERROR, > + "[%a]: failed to locate gArmNeoverseN1SocParameterPpiGuid - %r\n", > + gEfiCallerBaseName, > + Status > + )); > + return EFI_INVALID_PARAMETER; > + } > + > + if (fdt_check_header (ParamPpi->NtFwConfig) !=3D 0) { > + DEBUG ((DEBUG_ERROR, "Invalid DTB file %p passed\n", ParamPpi->NtFwC= onfig)); > + return EFI_INVALID_PARAMETER; > + } > + > + Offset =3D fdt_subnode_offset (ParamPpi->NtFwConfig, 0, "platform-info= "); > + if (Offset =3D=3D -FDT_ERR_NOTFOUND) { > + DEBUG ((DEBUG_ERROR, "Invalid DTB : platform-info node not found\n")= ); > + return EFI_INVALID_PARAMETER; > + } > + > + Property =3D fdt_getprop (ParamPpi->NtFwConfig, Offset, "local-ddr-siz= e", NULL); > + if (Property =3D=3D NULL) { > + DEBUG ((DEBUG_ERROR, "local-ddr-size property not found\n")); > + return EFI_INVALID_PARAMETER; > + } > + > + PlatInfo->LocalDdrSize =3D fdt32_to_cpu (*Property); > + > + Property =3D fdt_getprop (ParamPpi->NtFwConfig, Offset, "remote-ddr-si= ze", NULL); > + if (Property =3D=3D NULL) { > + DEBUG ((DEBUG_ERROR, "remote-ddr-size property not found\n")); > + return EFI_INVALID_PARAMETER; > + } > + > + PlatInfo->RemoteDdrSize =3D fdt32_to_cpu (*Property); > + > + Property =3D fdt_getprop (ParamPpi->NtFwConfig, Offset, "secondary-chi= p-count", NULL); > + if (Property =3D=3D NULL) { > + DEBUG ((DEBUG_ERROR, "secondary-chip-count property not found\n")); > + return EFI_INVALID_PARAMETER; > + } > + > + PlatInfo->SecondaryChipCount =3D fdt32_to_cpu (*Property); > + > + Property =3D fdt_getprop (ParamPpi->NtFwConfig, Offset, "multichip-mod= e", NULL); > + if (Property =3D=3D NULL) { > + DEBUG ((DEBUG_ERROR, "multichip-mode property not found\n")); > + return EFI_INVALID_PARAMETER; > + } > + > + PlatInfo->MultichipMode =3D fdt32_to_cpu (*Property); > + > + gPpi.Flags =3D EFI_PEI_PPI_DESCRIPTOR_PPI > + | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; > + gPpi.Guid =3D &gArmNeoverseN1SocPlatformInfoDescriptorPpiGuid; > + gPpi.Ppi =3D PlatInfo; > + > + Status =3D PeiServicesInstallPpi (&gPpi); > + if (EFI_ERROR (Status)) { > + DEBUG (( > + DEBUG_ERROR, > + "[%a]: failed to install PEI service - %r\n", > + gEfiCallerBaseName, > + Status > + )); > + return EFI_INVALID_PARAMETER; > + } > + > + return EFI_SUCCESS; > +} > diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c = b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c > index c0effd37f333..52ee6299b3fe 100644 > --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c > +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c > @@ -1,6 +1,6 @@ > /** @file > > - Copyright (c) 2018-2021, ARM Limited. All rights reserved.
> + Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.
> > SPDX-License-Identifier: BSD-2-Clause-Patent > > @@ -8,8 +8,12 @@ > > #include > #include > +#include > #include > > +UINT64 gArgNtFwConfigDtPtr; > +STATIC NEOVERSEN1SOC_EL3_FW_HANDOFF_PARAM_PPI mNeoverseN1SocParameterPp= i; > + > STATIC ARM_CORE_INFO mCoreInfoTable[] =3D { > { 0x0, 0x0 }, // Cluster 0, Core 0 > { 0x0, 0x1 }, // Cluster 0, Core 1 > @@ -46,6 +50,7 @@ ArmPlatformInitialize ( > IN UINTN MpId > ) > { > + mNeoverseN1SocParameterPpi.NtFwConfig =3D (VOID *)gArgNtFwConfigDtPtr; > return RETURN_SUCCESS; > } > > @@ -80,6 +85,11 @@ EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] =3D { > EFI_PEI_PPI_DESCRIPTOR_PPI, > &gArmMpCoreInfoPpiGuid, > &mMpCoreInfoPpi > + }, > + { > + EFI_PEI_PPI_DESCRIPTOR_PPI, > + &gArmNeoverseN1SocParameterPpiGuid, > + &mNeoverseN1SocParameterPpi > } > }; > > diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem= .c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c > index 9e8a1efc557d..d6ef92677231 100644 > --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c > +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c > @@ -1,6 +1,6 @@ > /** @file > > - Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.
> + Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.
> > SPDX-License-Identifier: BSD-2-Clause-Patent > > @@ -10,6 +10,7 @@ > #include > #include > #include > +#include > #include > > // The total number of descriptors, including the final "end-of-table" d= escriptor. > @@ -30,15 +31,31 @@ ArmPlatformGetVirtualMemoryMap ( > IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap > ) > { > - UINTN Index; > - ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; > - EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; > - NEOVERSEN1SOC_PLAT_INFO *PlatInfo; > - UINT64 DramBlock2Size; > - UINT64 RemoteDdrSize; > + UINTN Index; > + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; > + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; > + CONST NEOVERSEN1SOC_PLAT_INFO *PlatInfo; > + UINT64 DramBlock2Size; > + UINT64 RemoteDdrSize; > + EFI_STATUS Status; > > Index =3D 0; > - PlatInfo =3D (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT= _BASE; > + > + Status =3D PeiServicesLocatePpi ( > + &gArmNeoverseN1SocPlatformInfoDescriptorPpiGuid, > + 0, > + NULL, > + (VOID **)&PlatInfo > + ); > + if (EFI_ERROR (Status)) { > + DEBUG (( > + DEBUG_ERROR, > + "[%a]: failed to locate gArmNeoverseN1SocPlatformInfoDescriptorPpi= Guid - %r\n", > + gEfiCallerBaseName, > + Status > + )); > + } > + > DramBlock2Size =3D ((UINT64)(PlatInfo->LocalDdrSize - > NEOVERSEN1SOC_DRAM_BLOCK1_SIZE / SIZE_1GB) = * > (UINT64)SIZE_1GB); > diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper= .S b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S > index 8d2069dea837..cbbe7aae9858 100644 > --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S > +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S > @@ -1,6 +1,6 @@ > /** @file > * > -* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. > +* Copyright (c) 2019 - 2023, ARM Limited. All rights reserved. > * > * SPDX-License-Identifier: BSD-2-Clause-Patent > * > @@ -25,6 +25,8 @@ GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) > // the UEFI firmware through the CPU registers. > // > ASM_PFX(ArmPlatformPeiBootAction): > + adr x10, gArgNtFwConfigDtPtr > + str x0, [x10] > ret > > // > -- > 2.25.1 > > > > ------------ > Groups.io Links: You receive all messages sent to this group. > View/Reply Online (#107975): https://edk2.groups.io/g/devel/message/10797= 5 > Mute This Topic: https://groups.io/mt/100912169/5878107 > Group Owner: devel+owner@edk2.groups.io > Unsubscribe: https://edk2.groups.io/g/devel/unsub [ch.chandni@gmail.com] > ------------ > > -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#109516): https://edk2.groups.io/g/devel/message/109516 Mute This Topic: https://groups.io/mt/100912169/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-