From: Bartosz Szczepanek <bsz@semihalf.com>
To: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: "Ni, Ruiyu" <ruiyu.ni@intel.com>,
"edk2-devel@lists.01.org" <edk2-devel@lists.01.org>
Subject: Re: CPU/PCI addressing in PciIoGetAttributes
Date: Wed, 6 Sep 2017 11:34:22 +0200 [thread overview]
Message-ID: <CABLO=+=bNu8=ALZ-9MOE+1U-RZqpzbCYiq4JxAB6Sj=yqEstcA@mail.gmail.com> (raw)
In-Reply-To: <CAKv+Gu-bBSTutZXa9_FjXB+RtQnnEafqqhfGiR5xfR0Yot4Yow@mail.gmail.com>
> The spec is quite clear: the address descriptor should *not* contain
> the raw BAR value, but the CPU's translated view. So I think we should
> fix the implementation to comply with that.
To complicate it a little further, here's what ACPI specification says
about QWORD Address Space Descriptor:
> Address range minimum [...]. For bridges that translate addresses, this is the address space on
> the secondary side of the bridge.
I don't think "secondary" means CPU side here... perhaps it is
something to be discussed in ASWG/USWG?
prev parent reply other threads:[~2017-09-06 9:31 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-04 11:43 CPU/PCI addressing in PciIoGetAttributes Bartosz Szczepanek
2017-09-05 7:07 ` Ni, Ruiyu
2017-09-05 7:44 ` Bartosz Szczepanek
2017-09-05 13:40 ` Ard Biesheuvel
2017-09-06 9:34 ` Bartosz Szczepanek [this message]
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