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From: Bartosz Szczepanek <bsz@semihalf.com>
To: edk2-devel@lists.01.org
Cc: ruiyu.ni@intel.com
Subject: CPU/PCI addressing in PciIoGetAttributes
Date: Mon, 4 Sep 2017 13:43:29 +0200	[thread overview]
Message-ID: <CABLO=+mvg+JAWTiTVbirNyGWvsTTq4a=EeNso5dPqVRQ5-EkPw@mail.gmail.com> (raw)

Hi guys,

I have some doubt about PciIoGetAttributes behaviour on aarch64 platform
with non-uniform CPU:PCI address space mapping. I'll be grateful if you
verify my understanding.

According to UEFI specification, AddrRangeMin in QWORD Address Space
Descriptor returned by PciIoGetAttributes() should be a CPU address, at
least that's what I conclude from:
> Address Translation Offset. Offset to apply to the Starting address of a
> BAR *to convert it to a PCI address*. This value is zero unless the
> HostAddress and DeviceAddress for the BAR are different.
This mentions "Starting address", which I suppose refers to AddrRangeMin.
It needs to be converted to PCI address, so as-is it should be in CPU
address space.

On the other hand, the AddrRangeMin is assigned BaseAddress value obtained
directly from PciBar:
> Descriptor->AddrRangeMin = PciIoDevice->PciBar[BarIndex].BaseAddress;

PciBar is filled in PciParseBar() using original BAR content (thus
BaseAddress is not translated, PCI address). This way value that refers to
PCI space is returned from PciIoGetBarAttributes as CPU address.

Shouldn't there be translation of it somewhere on the way? Or is my
understanding flawed? Either way, please let me know.

Best regards,
Bartosz


             reply	other threads:[~2017-09-04 11:40 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-09-04 11:43 Bartosz Szczepanek [this message]
2017-09-05  7:07 ` CPU/PCI addressing in PciIoGetAttributes Ni, Ruiyu
2017-09-05  7:44   ` Bartosz Szczepanek
2017-09-05 13:40   ` Ard Biesheuvel
2017-09-06  9:34     ` Bartosz Szczepanek

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