Re: [edk2-devel] [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode

["Tuan Phan" <tphan@ventanamicro.com>]

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If we agree that default should be 10 then i will change it in the next
version.

On Wed, Oct 4, 2023 at 4:36 AM Sunil V L <sunilvl@ventanamicro.com> wrote:

> Hi Tuan,
>
> Thanks for the patch!. Adding UefiCpuPkg maintainers.
>
> On Tue, Oct 03, 2023 at 02:00:21PM -0700, Tuan Phan wrote:
> > Introduce a PCD to control the maximum SATP mode that MMU allowed
> > to use. This PCD helps RISC-V platform set bare or minimum SATA mode
>
> SATA -> SATP
>
> > during bring up to debug memory map issue.
> >
> > Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
> > ---
> >  UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c   | 6 +++++-
> >  UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 3 +++
> >  UefiCpuPkg/UefiCpuPkg.dec                              | 8 ++++++++
> >  3 files changed, 16 insertions(+), 1 deletion(-)
> >
> > diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> > index 9cca5fc128af..826a1d32a1d4 100644
> > --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> > +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> > @@ -36,7 +36,7 @@
> >  #define PTE_PPN_SHIFT         10
> >  #define RISCV_MMU_PAGE_SHIFT  12
> >
> > -STATIC UINTN  mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48,
> SATP_MODE_SV39 };
> > +STATIC UINTN  mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48,
> SATP_MODE_SV39, SATP_MODE_OFF };
> >  STATIC UINTN  mMaxRootTableLevel;
> >  STATIC UINTN  mBitPerLevel;
> >  STATIC UINTN  mTableEntryCount;
> > @@ -590,6 +590,10 @@ RiscVMmuSetSatpMode  (
> >    UINTN                            Index;
> >    EFI_STATUS                       Status;
> >
> > +  if (SatpMode > PcdGet32 (PcdCpuRiscVMmuMaxSatpMode)) {
> > +    return EFI_DEVICE_ERROR;
> > +  }
> > +
> >    switch (SatpMode) {
> >      case SATP_MODE_OFF:
> >        return EFI_SUCCESS;
> > diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> > index 9b28a98cb346..51ebe1750e97 100644
> > --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> > +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> > @@ -25,3 +25,6 @@
> >
> >  [LibraryClasses]
> >    BaseLib
> > +
> > +[Pcd]
> > +  gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode  ## CONSUMES
> > diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
> > index 68473fc640e6..79191af18a05 100644
> > --- a/UefiCpuPkg/UefiCpuPkg.dec
> > +++ b/UefiCpuPkg/UefiCpuPkg.dec
> > @@ -396,6 +396,14 @@
> >    # @Prompt Access to non-SMRAM memory is restricted to reserved,
> runtime and ACPI NVS type after SmmReadyToLock.
> >
> gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|BOOLEAN|0x3213210F
> >
> > +[PcdsFixedAtBuild.RISCV64]
> > +  ## Indicate the maximum SATP mode allowed.
> > +  #  0 - Bare mode.
> > +  #  8 - 39bit mode.
> > +  #  9 - 48bit mode.
> > +  #  10 - 57bit mode.
> > +
> gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode|0|UINT32|0x60000021
> > +
> Shouldn't the default value be 10?
>
> Thanks,
> Sunil
>
> >  [PcdsDynamic, PcdsDynamicEx]
> >    ## Contains the pointer to a CPU S3 data buffer of structure
> ACPI_CPU_DATA.
> >    # @Prompt The pointer to a CPU S3 data buffer.
> > --
> > 2.25.1
> >
>


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