From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 0286B7803D2 for ; Wed, 4 Oct 2023 15:27:42 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=0PX6v+AZcb270HlIzDlmdAI4H4MJ65VNNWFJGzTUExw=; c=relaxed/simple; d=groups.io; h=MIME-Version:References:In-Reply-To:From:Date:Message-ID:Subject:To:Cc:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type; s=20140610; t=1696433261; v=1; b=kTTHkraViUetM0/e/2ygQJxkHXn0lbkT8kLsp7+UmG50cickklmFz4pD+vhqSFvLlkUQTNEF xAEAQCWCXaeqEByfR/W9tbUTiwjfn8Z5ElklGK2mT5nBljaQ4LetOBYSU+OJKnPOLAIE3uix8C5 rlFI03m1uM8gLK1Nn1hDQJ+c= X-Received: by 127.0.0.2 with SMTP id 57l4YY7687511xbMCuhTcgVj; Wed, 04 Oct 2023 08:27:41 -0700 X-Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) by mx.groups.io with SMTP id smtpd.web11.21494.1696433260858096456 for ; Wed, 04 Oct 2023 08:27:41 -0700 X-Received: by mail-ej1-f53.google.com with SMTP id a640c23a62f3a-9b2cee55056so431504366b.3 for ; Wed, 04 Oct 2023 08:27:40 -0700 (PDT) X-Gm-Message-State: C5TLtRqqqKMJW3bzPzrFBWVTx7686176AA= X-Google-Smtp-Source: AGHT+IGUO2pgc5cJXwUSqSKmL9NBukXFuAvckHacnBzKqNHFd/Lfq2OjwGxawaen86HdyLXMgqyVtqnpIywknImvANw= X-Received: by 2002:a17:906:10d4:b0:9ae:7943:b0ff with SMTP id v20-20020a17090610d400b009ae7943b0ffmr2144628ejv.27.1696433259150; Wed, 04 Oct 2023 08:27:39 -0700 (PDT) MIME-Version: 1.0 References: <20231003210021.26834-1-tphan@ventanamicro.com> In-Reply-To: From: "Tuan Phan" Date: Wed, 4 Oct 2023 08:27:28 -0700 Message-ID: Subject: Re: [edk2-devel] [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode To: Sunil V L Cc: Eric Dong , Gerd Hoffmann , Rahul Kumar , Ray Ni , andrei.warkentin@intel.com, ardb+tianocore@kernel.org, devel@edk2.groups.io, gaoliming@byosoft.com.cn, git@danielschaefer.me, michael.d.kinney@intel.com, zhiguang.liu@intel.com Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,tphan@ventanamicro.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Type: multipart/alternative; boundary="000000000000cc21790606e5a533" X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=kTTHkraV; dmarc=none; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io --000000000000cc21790606e5a533 Content-Type: text/plain; charset="UTF-8" If we agree that default should be 10 then i will change it in the next version. On Wed, Oct 4, 2023 at 4:36 AM Sunil V L wrote: > Hi Tuan, > > Thanks for the patch!. Adding UefiCpuPkg maintainers. > > On Tue, Oct 03, 2023 at 02:00:21PM -0700, Tuan Phan wrote: > > Introduce a PCD to control the maximum SATP mode that MMU allowed > > to use. This PCD helps RISC-V platform set bare or minimum SATA mode > > SATA -> SATP > > > during bring up to debug memory map issue. > > > > Signed-off-by: Tuan Phan > > --- > > UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 6 +++++- > > UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 3 +++ > > UefiCpuPkg/UefiCpuPkg.dec | 8 ++++++++ > > 3 files changed, 16 insertions(+), 1 deletion(-) > > > > diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c > b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c > > index 9cca5fc128af..826a1d32a1d4 100644 > > --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c > > +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c > > @@ -36,7 +36,7 @@ > > #define PTE_PPN_SHIFT 10 > > #define RISCV_MMU_PAGE_SHIFT 12 > > > > -STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48, > SATP_MODE_SV39 }; > > +STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48, > SATP_MODE_SV39, SATP_MODE_OFF }; > > STATIC UINTN mMaxRootTableLevel; > > STATIC UINTN mBitPerLevel; > > STATIC UINTN mTableEntryCount; > > @@ -590,6 +590,10 @@ RiscVMmuSetSatpMode ( > > UINTN Index; > > EFI_STATUS Status; > > > > + if (SatpMode > PcdGet32 (PcdCpuRiscVMmuMaxSatpMode)) { > > + return EFI_DEVICE_ERROR; > > + } > > + > > switch (SatpMode) { > > case SATP_MODE_OFF: > > return EFI_SUCCESS; > > diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf > b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf > > index 9b28a98cb346..51ebe1750e97 100644 > > --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf > > +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf > > @@ -25,3 +25,6 @@ > > > > [LibraryClasses] > > BaseLib > > + > > +[Pcd] > > + gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode ## CONSUMES > > diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec > > index 68473fc640e6..79191af18a05 100644 > > --- a/UefiCpuPkg/UefiCpuPkg.dec > > +++ b/UefiCpuPkg/UefiCpuPkg.dec > > @@ -396,6 +396,14 @@ > > # @Prompt Access to non-SMRAM memory is restricted to reserved, > runtime and ACPI NVS type after SmmReadyToLock. > > > gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|BOOLEAN|0x3213210F > > > > +[PcdsFixedAtBuild.RISCV64] > > + ## Indicate the maximum SATP mode allowed. > > + # 0 - Bare mode. > > + # 8 - 39bit mode. > > + # 9 - 48bit mode. > > + # 10 - 57bit mode. > > + > gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode|0|UINT32|0x60000021 > > + > Shouldn't the default value be 10? > > Thanks, > Sunil > > > [PcdsDynamic, PcdsDynamicEx] > > ## Contains the pointer to a CPU S3 data buffer of structure > ACPI_CPU_DATA. > > # @Prompt The pointer to a CPU S3 data buffer. > > -- > > 2.25.1 > > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#109323): https://edk2.groups.io/g/devel/message/109323 Mute This Topic: https://groups.io/mt/101742937/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=- --000000000000cc21790606e5a533 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
If we agree that default should be 10 then i will change = it in the next version.

On Wed, Oct 4, 2023 at 4:36 AM Sunil V L <= sunilvl@ventanamicro.com>= ; wrote:
Hi Tuan,

Thanks for the patch!. Adding UefiCpuPkg maintainers.

On Tue, Oct 03, 2023 at 02:00:21PM -0700, Tuan Phan wrote:
> Introduce a PCD to control the maximum SATP mode that MMU allowed
> to use. This PCD helps RISC-V platform set bare or minimum SATA mode
SATA -> SATP

> during bring up to debug memory map issue.
>
> Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
> ---
>=C2=A0 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c=C2=A0 =C2= =A0| 6 +++++-
>=C2=A0 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 3 +++ >=C2=A0 UefiCpuPkg/UefiCpuPkg.dec=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | 8 ++++= ++++
>=C2=A0 3 files changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c b/Ue= fiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> index 9cca5fc128af..826a1d32a1d4 100644
> --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> @@ -36,7 +36,7 @@
>=C2=A0 #define PTE_PPN_SHIFT=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A010
>=C2=A0 #define RISCV_MMU_PAGE_SHIFT=C2=A0 12
>=C2=A0
> -STATIC UINTN=C2=A0 mModeSupport[] =3D { SATP_MODE_SV57, SATP_MODE_SV4= 8, SATP_MODE_SV39 };
> +STATIC UINTN=C2=A0 mModeSupport[] =3D { SATP_MODE_SV57, SATP_MODE_SV4= 8, SATP_MODE_SV39, SATP_MODE_OFF };
>=C2=A0 STATIC UINTN=C2=A0 mMaxRootTableLevel;
>=C2=A0 STATIC UINTN=C2=A0 mBitPerLevel;
>=C2=A0 STATIC UINTN=C2=A0 mTableEntryCount;
> @@ -590,6 +590,10 @@ RiscVMmuSetSatpMode=C2=A0 (
>=C2=A0 =C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Index;
>=C2=A0 =C2=A0 EFI_STATUS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Status;
>=C2=A0
> +=C2=A0 if (SatpMode > PcdGet32 (PcdCpuRiscVMmuMaxSatpMode)) {
> +=C2=A0 =C2=A0 return EFI_DEVICE_ERROR;
> +=C2=A0 }
> +
>=C2=A0 =C2=A0 switch (SatpMode) {
>=C2=A0 =C2=A0 =C2=A0 case SATP_MODE_OFF:
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 return EFI_SUCCESS;
> diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf b/= UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> index 9b28a98cb346..51ebe1750e97 100644
> --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> @@ -25,3 +25,6 @@
>=C2=A0
>=C2=A0 [LibraryClasses]
>=C2=A0 =C2=A0 BaseLib
> +
> +[Pcd]
> +=C2=A0 gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode=C2=A0 ## C= ONSUMES
> diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
> index 68473fc640e6..79191af18a05 100644
> --- a/UefiCpuPkg/UefiCpuPkg.dec
> +++ b/UefiCpuPkg/UefiCpuPkg.dec
> @@ -396,6 +396,14 @@
>=C2=A0 =C2=A0 # @Prompt Access to non-SMRAM memory is restricted to res= erved, runtime and ACPI NVS type after SmmReadyToLock.
>=C2=A0 =C2=A0 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess= |TRUE|BOOLEAN|0x3213210F
>=C2=A0
> +[PcdsFixedAtBuild.RISCV64]
> +=C2=A0 ## Indicate the maximum SATP mode allowed.
> +=C2=A0 #=C2=A0 0 - Bare mode.
> +=C2=A0 #=C2=A0 8 - 39bit mode.
> +=C2=A0 #=C2=A0 9 - 48bit mode.
> +=C2=A0 #=C2=A0 10 - 57bit mode.
> +=C2=A0 gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode|0|UINT32|0= x60000021
> +
Shouldn't the default value be 10?

Thanks,
Sunil

>=C2=A0 [PcdsDynamic, PcdsDynamicEx]
>=C2=A0 =C2=A0 ## Contains the pointer to a CPU S3 data buffer of struct= ure ACPI_CPU_DATA.
>=C2=A0 =C2=A0 # @Prompt The pointer to a CPU S3 data buffer.
> --
> 2.25.1
>
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