From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-ej1-f42.google.com (mail-ej1-f42.google.com [209.85.218.42]) by mx.groups.io with SMTP id smtpd.web11.16198.1684879204802333904 for ; Tue, 23 May 2023 15:00:05 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="signature has expired" header.i=@ventanamicro.com header.s=google header.b=VjQIZFrv; spf=pass (domain: ventanamicro.com, ip: 209.85.218.42, mailfrom: tphan@ventanamicro.com) Received: by mail-ej1-f42.google.com with SMTP id a640c23a62f3a-96fa4a6a79bso18709966b.3 for ; Tue, 23 May 2023 15:00:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1684879203; x=1687471203; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=dxu4dySIbuyQHvRnvJq2yL7pKHrt0LJOEM6cIUFPIzs=; b=VjQIZFrv+C4o/MZV2pM9wL40QDvJyNZDKAo/nAG5ENtj42qAkjE4cl+UL4VJl4Vd+h EfuQeF8ADR3wJdzeVCiIs9DAPO5TioahpnKzSaOiYBSqr8cgFNLj7MZGDmyZVNNNMMB3 U0vB+huXrAPuQwP8WFaJAJ8l59p2xiiqggGyZ8UbLMFnkSbtWLRxCKlBLGUAp5y9y1O2 TrsaDE7M3Q9j+RKXpuI6Q7ZNnn69oCW1aV/lLYxLTKkQOFfdfkUriwQdhlCL8l6WQtMf CUen4RWqAdvhNFvYcLgekoJqYMXUYEOc1qjp2CcdlLaHymADr2vyIrUvIX+3y9EmhMqq QBKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684879203; x=1687471203; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=dxu4dySIbuyQHvRnvJq2yL7pKHrt0LJOEM6cIUFPIzs=; b=X3KlkrmfqB4upeyhyvWsDS8kWzTq6gc86oYg5mc+3EN5VC0k4uN5KbRAlSppX/JZGQ Jeniws4EMz0QUq0AltNBpUPbZPxMY/FpNyyRUvcVhcc6Zcuesw7DW7WvjNHOHY452wLY mAcgmwLoVcyjd/HX3ngUONWic33+FltMAoZ9ip1l8yCgLnb7AAkzAojnAVLCMx3XsoHn qlo8XjYgNqFT+Jk//uDAC2IJ0/UG4AThThgs+b8ZNVlAyFsIoOaHN+0cSsM7baNBdnVG vK3r7fiXriHQmuXpAuBDwZtvqQZGRkfycXpcgvrIFWLkde1I1joTZV30XBSK+JNL+VTq t2mw== X-Gm-Message-State: AC+VfDw0yw9tPOrfcWxP9c2m/ewBYXxCJI4pEb18v12tYBnklSfrI5Bg eTCM9aCcL0RZQi6xaj72yNRAElT0SqbJGIwjCYMKmQ== X-Google-Smtp-Source: ACHHUZ5Ts9pr50CdhMlfgcfDjghn7y2nRrVNkPsEr5txt0GIz4HEGpeU3guno0MuEfBeG3PL5ZjsXkaNVu6SGfNNHtw= X-Received: by 2002:a17:907:3e97:b0:966:350f:f43b with SMTP id hs23-20020a1709073e9700b00966350ff43bmr17245187ejc.9.1684879203177; Tue, 23 May 2023 15:00:03 -0700 (PDT) MIME-Version: 1.0 References: <20230414185815.2994-1-tphan@ventanamicro.com> In-Reply-To: From: "Tuan Phan" Date: Tue, 23 May 2023 14:59:50 -0700 Message-ID: Subject: Re: [edk2-devel] [PATCH v2 0/6] RISC-V MMU support To: "Warkentin, Andrei" Cc: "devel@edk2.groups.io" , "Kinney, Michael D" , "Gao, Liming" , "Liu, Zhiguang" , "sunilvl@ventanamicro.com" , "git@danielschaefer.me" Content-Type: multipart/alternative; boundary="00000000000065289305fc6382df" --00000000000065289305fc6382df Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Thanks Andrei, Sunil, any comments or it is good to go. As this patchset spans across MdePkg, UefiCpuPkg and OvmfPkg, do I need to separate it so each package maintainer can merge independently? On Mon, May 8, 2023 at 10:19=E2=80=AFAM Warkentin, Andrei < andrei.warkentin@intel.com> wrote: > Apologies for the late review. I added my comments on GH. Aside from a > request for more context for > https://github.com/tianocore/edk2/commit/b7387dae40cc3a72562c6461d007d200= 87ab7414#comments, > I think this patch set from a functionality standpoint looks good enough = to > be submitted. > > > > Reviewed-by: Andrei Warkentin > > > > *From:* devel@edk2.groups.io *On Behalf Of *Tuan > Phan > *Sent:* Wednesday, April 19, 2023 5:37 PM > *To:* devel@edk2.groups.io; Warkentin, Andrei > *Cc:* Kinney, Michael D ; Gao, Liming < > gaoliming@byosoft.com.cn>; Liu, Zhiguang ; > sunilvl@ventanamicro.com; git@danielschaefer.me > *Subject:* Re: [edk2-devel] [PATCH v2 0/6] RISC-V MMU support > > > > Hi Andrei, > > Here you go: https://github.com/pttuan/edk2/tree/tphan/riscv_mmu > > Will put the link in the cover letter next round. > > > > *From: *devel@edk2.groups.io on behalf of Andrei > Warkentin > *Date: *Tuesday, April 18, 2023 at 9:04 AM > *To: *Tuan Phan , devel@edk2.groups.io < > devel@edk2.groups.io> > *Cc: *Kinney, Michael D , Gao, Liming < > gaoliming@byosoft.com.cn>, Liu, Zhiguang , > sunilvl@ventanamicro.com , git@danielschaefer.m= e > > *Subject: *Re: [edk2-devel] [PATCH v2 0/6] RISC-V MMU support > > Hi Tuan, > > Do you mind sharing the GitHub branch as well? It would help with the > review immensely. > > A > > > -----Original Message----- > > From: Tuan Phan > > Sent: Friday, April 14, 2023 1:58 PM > > To: devel@edk2.groups.io > > Cc: Kinney, Michael D ; Gao, Liming > > ; Liu, Zhiguang ; > > sunilvl@ventanamicro.com; git@danielschaefer.me; Warkentin, Andrei > > ; Tuan Phan > > Subject: [PATCH v2 0/6] RISC-V MMU support > > > > RISC-V: Add MMU support > > > > This series adds MMU support for RISC-V. Only SV39/48/57 modes are > > supported and tested. The MMU is required to support setting page > > attribute which is the first basic step to support security booting on > RISC-V. > > > > There are three parts: > > 1. Add MMU base library. MMU will be enabled during CpuDxe > initialization. > > 2. Fix OvmfPkg/VirtNorFlashDxe that failed to add flash base address to > GCD > > if already done. > > 3. Fix all resources should be populated in HOB or added to GCD by driv= er > > before accessing when MMU enabled. > > > > Changes in v2: > > - Move MMU core to a library. > > - Setup SATP mode as highest possible that HW supports. > > > > Tuan Phan (6): > > MdePkg/BaseLib: RISC-V: Support getting satp register value > > MdePkg/Register: RISC-V: Add satp mode bits shift definition > > UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode > > OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size > > OvmfPkg/VirtNorFlashDxe: Not add memory space if it exists > > OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform > > devices > > > > MdePkg/Include/Library/BaseLib.h | 5 + > > MdePkg/Include/Library/BaseRiscVMmuLib.h | 39 ++ > > .../Include/Register/RiscV64/RiscVEncoding.h | 7 +- > > MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8 + > > .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 569 > > ++++++++++++++++++ > > .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 25 + > > MdePkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S | 31 + > > .../VirtNorFlashStaticLib.c | 3 +- > > OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 + > > OvmfPkg/RiscVVirt/Sec/Memory.c | 18 +- > > OvmfPkg/RiscVVirt/Sec/Platform.c | 62 ++ > > OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 + > > OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c | 25 +- > > UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 9 +- > > UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 2 + > > UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf | 2 + > > 16 files changed, 776 insertions(+), 31 deletions(-) create mode 1006= 44 > > MdePkg/Include/Library/BaseRiscVMmuLib.h > > create mode 100644 > > MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c > > create mode 100644 > > MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf > > create mode 100644 MdePkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S > > > > -- > > 2.25.1 > > > > >=20 > --00000000000065289305fc6382df Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Thanks Andrei,
Sunil, any comments or it is good=C2=A0= to go. As this patchset spans across MdePkg, UefiCpuPkg and OvmfPkg, do I n= eed to separate=C2=A0it so each package maintainer can merge independently?=

On Mon, May 8, 2023 at 10:19=E2=80=AFAM Warkentin, Andrei <andrei.warkentin@intel.com> w= rote:

Apologies for the lat= e review. I added my comments on GH. Aside from a request for more context = for https://github.com/tianocore/edk2/commit/b7387dae40cc3a72562c6461d007d20087= ab7414#comments, I think this patch set from a functionality standpoint= looks good enough to be submitted.

=C2=A0<= /span>

Reviewed-by: Andrei W= arkentin <andrei.warkentin@intel.com>

=C2=A0<= /span>

From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Tuan Phan
Sent: Wednesday, April 19, 2023 5:37 PM
To: devel@= edk2.groups.io; Warkentin, Andrei <andrei.warkentin@intel.com>
Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming <<= a href=3D"mailto:gaoliming@byosoft.com.cn" target=3D"_blank">gaoliming@byos= oft.com.cn>; Liu, Zhiguang <zhiguang.liu@intel.com>; sunilvl@ventanamicro.com; git@danielschaefer.= me
Subject: Re: [edk2-devel] [PATCH v2 0/6] RISC-V MMU support

=C2=A0

Hi Andrei,<= /u>

Here you go: https://github.com/pttuan/edk2/tree/tphan/riscv_mmu

Will put the link in = the cover letter next round.

=C2=A0<= /span>

From: devel@edk2.groups.io <devel@edk2.groups.io= > on behalf of Andrei Warkentin <andrei.warkentin@intel.com>
Date: Tuesday, April 18, 2023 at 9:04 AM
To: Tuan Phan <tphan@ventanamicro.com>, devel@edk2.groups= .io <devel= @edk2.groups.io>
Cc: Kinney, Michael D <michael.d.kinney@intel.com>, Gao, Liming <<= a href=3D"mailto:gaoliming@byosoft.com.cn" target=3D"_blank">gaoliming@byos= oft.com.cn>, Liu, Zhiguang <zhiguang.liu@intel.com>, sunilvl@venta= namicro.com <sunilvl@ventanamicro.com>, git@danielschaef= er.me <gi= t@danielschaefer.me>
Subject: Re: [edk2-devel] [PATCH v2 0/6] RISC-V MMU support

Hi Tuan,

Do you mind sharing the GitHub branch as well? It would help with the revie= w immensely.

A

> -----Original Message-----
> From: Tuan Phan <tphan@ventanamicro.com>
> Sent: Friday, April 14, 2023 1:58 PM
> To: devel@ed= k2.groups.io
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming
> <gaol= iming@byosoft.com.cn>; Liu, Zhiguang <zhiguang.liu@intel.com>;
> sunilvl@= ventanamicro.com; git@danielschaefer.me; Warkentin, Andrei
> <an= drei.warkentin@intel.com>; Tuan Phan <tphan@ventanamicro.com>
> Subject: [PATCH v2 0/6] RISC-V MMU support
>
> RISC-V: Add MMU support
>
> This series adds MMU support for RISC-V. Only SV39/48/57 modes are
> supported and tested. The MMU is required to support setting page
> attribute which is the first basic step to support security booting on= RISC-V.
>
> There are three parts:
> 1. Add MMU base library. MMU will be enabled during CpuDxe initializat= ion.
> 2. Fix OvmfPkg/VirtNorFlashDxe that failed to add flash base address t= o GCD
> if already done.
> 3. Fix all resources should be populated in HOB or added to GCD by dri= ver
> before accessing when MMU enabled.
>
> Changes in v2:
>=C2=A0=C2=A0 - Move MMU core to a library.
>=C2=A0=C2=A0 - Setup SATP mode as highest possible that HW supports. >
> Tuan Phan (6):
>=C2=A0=C2=A0 MdePkg/BaseLib: RISC-V: Support getting satp register valu= e
>=C2=A0=C2=A0 MdePkg/Register: RISC-V: Add satp mode bits shift definiti= on
>=C2=A0=C2=A0 UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode
>=C2=A0=C2=A0 OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flas= h size
>=C2=A0=C2=A0 OvmfPkg/VirtNorFlashDxe: Not add memory space if it exists=
>=C2=A0=C2=A0 OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for pla= tform
>=C2=A0=C2=A0=C2=A0=C2=A0 devices
>
>=C2=A0 MdePkg/Include/Library/BaseLib.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 5 +
>=C2=A0 MdePkg/Include/Library/BaseRiscVMmuLib.h=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 |=C2=A0 39 ++
>=C2=A0 .../Include/Register/RiscV64/RiscVEncoding.h=C2=A0 |=C2=A0=C2=A0= 7 +-
>=C2=A0 MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S=C2=A0=C2=A0=C2=A0=C2= =A0 |=C2=A0=C2=A0 8 +
>=C2=A0 .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 569
> ++++++++++++++++++
>=C2=A0 .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 |=C2=A0 25 +
>=C2=A0 MdePkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S |=C2=A0 31 +
>=C2=A0 .../VirtNorFlashStaticLib.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |= =C2=A0=C2=A0 3 +-
>=C2=A0 OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 1 +
>=C2=A0 OvmfPkg/RiscVVirt/Sec/Memory.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 18 +-
>=C2=A0 OvmfPkg/RiscVVirt/Sec/Platform.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 62 ++
>=C2=A0 OvmfPkg/RiscVVirt/Sec/SecMain.inf=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 1 +
>=C2=A0 OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c=C2=A0=C2=A0=C2=A0=C2= =A0 |=C2=A0 25 +-
>=C2=A0 UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 9 +-
>=C2=A0 UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 2 +
>=C2=A0 UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf=C2=A0=C2=A0=C2=A0 |= =C2=A0=C2=A0 2 +
>=C2=A0 16 files changed, 776 insertions(+), 31 deletions(-)=C2=A0 creat= e mode 100644
> MdePkg/Include/Library/BaseRiscVMmuLib.h
>=C2=A0 create mode 100644
> MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
>=C2=A0 create mode 100644
> MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
>=C2=A0 create mode 100644 MdePkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S=
>
> --
> 2.25.1




--00000000000065289305fc6382df--