* [PATCH v4 0/7] RISC-V: Add MMU support
@ 2023-06-23 18:39 Tuan Phan
2023-06-23 18:39 ` [PATCH v4 1/7] MdePkg/BaseLib: RISC-V: Support getting satp register value Tuan Phan
` (8 more replies)
0 siblings, 9 replies; 20+ messages in thread
From: Tuan Phan @ 2023-06-23 18:39 UTC (permalink / raw)
To: devel
Cc: michael.d.kinney, gaoliming, zhiguang.liu, sunilvl, git,
andrei.warkentin, ardb+tianocore, Tuan Phan
This series adds MMU support for RISC-V. Only SV39/48/57 modes
are supported and tested. The MMU is required to support setting
page attribute which is the first basic step to support security
booting on RISC-V.
There are two parts:
1. Add MMU base library. MMU will be enabled during
CpuDxe initialization.
2. Fix all resources should be populated in HOB
or added to GCD by driver before accessing when MMU enabled.
All changes can be found in the branch tphan/riscv_mmu at:
https://github.com/pttuan/edk2.git
Changes in v4:
- Rebased master.
- Added VirtNorFlashDxe to APRIORI DXE list.
Changes in v3:
- Move MMU library to UefiCpuPkg.
- Add Andrei reviewed-by.
Changes in v2:
- Move MMU core to a library.
- Setup SATP mode as highest possible that HW supports.
Tuan Phan (7):
MdePkg/BaseLib: RISC-V: Support getting satp register value
MdePkg/Register: RISC-V: Add satp mode bits shift definition
OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size
OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform
devices
OvmfPkg/RiscVVirt: Add VirtNorFlashDxe to APRIORI list
OvmfPkg: RiscVVirt: Remove satp bare mode setting
UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode
MdePkg/Include/Library/BaseLib.h | 5 +
.../Include/Register/RiscV64/RiscVEncoding.h | 7 +-
MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8 +
.../VirtNorFlashStaticLib.c | 3 +-
OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 +
OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 10 +
OvmfPkg/RiscVVirt/Sec/Memory.c | 18 +-
OvmfPkg/RiscVVirt/Sec/Platform.c | 62 ++
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 9 +-
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 2 +
UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf | 2 +
UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h | 39 ++
.../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 569 ++++++++++++++++++
.../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 26 +
.../Library/BaseRiscVMmuLib/RiscVMmuCore.S | 31 +
15 files changed, 770 insertions(+), 22 deletions(-)
create mode 100644 UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h
create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S
--
2.25.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v4 1/7] MdePkg/BaseLib: RISC-V: Support getting satp register value
2023-06-23 18:39 [PATCH v4 0/7] RISC-V: Add MMU support Tuan Phan
@ 2023-06-23 18:39 ` Tuan Phan
2023-06-23 18:39 ` [PATCH v4 2/7] MdePkg/Register: RISC-V: Add satp mode bits shift definition Tuan Phan
` (7 subsequent siblings)
8 siblings, 0 replies; 20+ messages in thread
From: Tuan Phan @ 2023-06-23 18:39 UTC (permalink / raw)
To: devel
Cc: michael.d.kinney, gaoliming, zhiguang.liu, sunilvl, git,
andrei.warkentin, ardb+tianocore, Tuan Phan
Add an API to retrieve satp register value.
Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
---
MdePkg/Include/Library/BaseLib.h | 5 +++++
MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8 ++++++++
2 files changed, 13 insertions(+)
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 8f2df76c29a3..5d7067ee854e 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -181,6 +181,11 @@ RiscVSetSupervisorAddressTranslationRegister (
IN UINT64
);
+UINT64
+RiscVGetSupervisorAddressTranslationRegister (
+ VOID
+ );
+
UINT64
RiscVReadTimer (
VOID
diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S b/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S
index ac8f92f38aed..c9cf60c1664b 100644
--- a/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S
+++ b/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S
@@ -21,3 +21,11 @@
ASM_FUNC (RiscVSetSupervisorAddressTranslationRegister)
csrw CSR_SATP, a0
ret
+
+//
+// Get the value of Supervisor Address Translation and
+// Protection Register.
+//
+ASM_FUNC (RiscVGetSupervisorAddressTranslationRegister)
+ csrr a0, CSR_SATP
+ ret
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v4 2/7] MdePkg/Register: RISC-V: Add satp mode bits shift definition
2023-06-23 18:39 [PATCH v4 0/7] RISC-V: Add MMU support Tuan Phan
2023-06-23 18:39 ` [PATCH v4 1/7] MdePkg/BaseLib: RISC-V: Support getting satp register value Tuan Phan
@ 2023-06-23 18:39 ` Tuan Phan
2023-06-27 20:10 ` Michael D Kinney
2023-06-23 18:39 ` [PATCH v4 3/7] OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size Tuan Phan
` (6 subsequent siblings)
8 siblings, 1 reply; 20+ messages in thread
From: Tuan Phan @ 2023-06-23 18:39 UTC (permalink / raw)
To: devel
Cc: michael.d.kinney, gaoliming, zhiguang.liu, sunilvl, git,
andrei.warkentin, ardb+tianocore, Tuan Phan
The satp mode bits shift is used cross modules. It should be defined
in one place.
Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
---
MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
index 5c2989b797bf..2bde8db478ff 100644
--- a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
+++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
@@ -58,9 +58,10 @@
#define PRV_S 1UL
#define PRV_M 3UL
-#define SATP64_MODE 0xF000000000000000ULL
-#define SATP64_ASID 0x0FFFF00000000000ULL
-#define SATP64_PPN 0x00000FFFFFFFFFFFULL
+#define SATP64_MODE 0xF000000000000000ULL
+#define SATP64_MODE_SHIFT 60
+#define SATP64_ASID 0x0FFFF00000000000ULL
+#define SATP64_PPN 0x00000FFFFFFFFFFFULL
#define SATP_MODE_OFF 0UL
#define SATP_MODE_SV32 1UL
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v4 3/7] OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size
2023-06-23 18:39 [PATCH v4 0/7] RISC-V: Add MMU support Tuan Phan
2023-06-23 18:39 ` [PATCH v4 1/7] MdePkg/BaseLib: RISC-V: Support getting satp register value Tuan Phan
2023-06-23 18:39 ` [PATCH v4 2/7] MdePkg/Register: RISC-V: Add satp mode bits shift definition Tuan Phan
@ 2023-06-23 18:39 ` Tuan Phan
2023-06-23 18:39 ` [PATCH v4 4/7] OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform devices Tuan Phan
` (5 subsequent siblings)
8 siblings, 0 replies; 20+ messages in thread
From: Tuan Phan @ 2023-06-23 18:39 UTC (permalink / raw)
To: devel
Cc: michael.d.kinney, gaoliming, zhiguang.liu, sunilvl, git,
andrei.warkentin, ardb+tianocore, Tuan Phan
The size should be for single region, not the whole firmware FD.
Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
---
.../Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c b/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c
index fdc2ccb6294e..33f3a01b06f4 100644
--- a/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c
+++ b/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c
@@ -24,7 +24,8 @@ VIRT_NOR_FLASH_DESCRIPTION mNorFlashDevice =
{
FixedPcdGet32 (PcdOvmfFdBaseAddress),
FixedPcdGet64 (PcdFlashNvStorageVariableBase),
- FixedPcdGet32 (PcdOvmfFirmwareFdSize),
+ FixedPcdGet32 (PcdOvmfFirmwareFdSize) -
+ (FixedPcdGet64 (PcdFlashNvStorageVariableBase) - FixedPcdGet32 (PcdOvmfFdBaseAddress)),
QEMU_NOR_BLOCK_SIZE
};
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v4 4/7] OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform devices
2023-06-23 18:39 [PATCH v4 0/7] RISC-V: Add MMU support Tuan Phan
` (2 preceding siblings ...)
2023-06-23 18:39 ` [PATCH v4 3/7] OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size Tuan Phan
@ 2023-06-23 18:39 ` Tuan Phan
2023-06-23 18:39 ` [PATCH v4 5/7] OvmfPkg/RiscVVirt: Add VirtNorFlashDxe to APRIORI list Tuan Phan
` (4 subsequent siblings)
8 siblings, 0 replies; 20+ messages in thread
From: Tuan Phan @ 2023-06-23 18:39 UTC (permalink / raw)
To: devel
Cc: michael.d.kinney, gaoliming, zhiguang.liu, sunilvl, git,
andrei.warkentin, ardb+tianocore, Tuan Phan
Normally, DXE driver would add device resource to GCD before start using.
But some key resources such as uart used for printing info at very early
stage.
Those resources should be populated to HOB in SEC phase so they are
added to GCD before MMU enabled.
Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
---
OvmfPkg/RiscVVirt/Sec/Platform.c | 62 ++++++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/OvmfPkg/RiscVVirt/Sec/Platform.c b/OvmfPkg/RiscVVirt/Sec/Platform.c
index 3645c27b0b12..c66432473067 100644
--- a/OvmfPkg/RiscVVirt/Sec/Platform.c
+++ b/OvmfPkg/RiscVVirt/Sec/Platform.c
@@ -21,6 +21,64 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <libfdt.h>
#include <Guid/FdtHob.h>
+/**
+ Build memory map I/O range resource HOB using the
+ base address and size.
+
+ @param MemoryBase Memory map I/O base.
+ @param MemorySize Memory map I/O size.
+
+**/
+STATIC
+VOID
+AddIoMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ )
+{
+ /* Align to EFI_PAGE_SIZE */
+ MemorySize = ALIGN_VALUE (MemorySize, EFI_PAGE_SIZE);
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_MEMORY_MAPPED_IO,
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED,
+ MemoryBase,
+ MemorySize
+ );
+}
+
+/**
+ Populate IO resources from FDT that not added to GCD by its
+ driver in the DXE phase.
+
+ @param FdtBase Fdt base address
+ @param Compatible Compatible string
+
+**/
+STATIC
+VOID
+PopulateIoResources (
+ VOID *FdtBase,
+ CONST CHAR8 *Compatible
+ )
+{
+ UINT64 *Reg;
+ INT32 Node, LenP;
+
+ Node = fdt_node_offset_by_compatible (FdtBase, -1, Compatible);
+ while (Node != -FDT_ERR_NOTFOUND) {
+ Reg = (UINT64 *)fdt_getprop (FdtBase, Node, "reg", &LenP);
+ if (Reg) {
+ ASSERT (LenP == (2 * sizeof (UINT64)));
+ AddIoMemoryBaseSizeHob (SwapBytes64 (Reg[0]), SwapBytes64 (Reg[1]));
+ }
+
+ Node = fdt_node_offset_by_compatible (FdtBase, Node, Compatible);
+ }
+}
+
/**
@retval EFI_SUCCESS The address of FDT is passed in HOB.
EFI_UNSUPPORTED Can't locate FDT.
@@ -80,5 +138,9 @@ PlatformPeimInitialization (
BuildFvHob (PcdGet32 (PcdOvmfDxeMemFvBase), PcdGet32 (PcdOvmfDxeMemFvSize));
+ PopulateIoResources (Base, "ns16550a");
+ PopulateIoResources (Base, "qemu,fw-cfg-mmio");
+ PopulateIoResources (Base, "virtio,mmio");
+
return EFI_SUCCESS;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v4 5/7] OvmfPkg/RiscVVirt: Add VirtNorFlashDxe to APRIORI list
2023-06-23 18:39 [PATCH v4 0/7] RISC-V: Add MMU support Tuan Phan
` (3 preceding siblings ...)
2023-06-23 18:39 ` [PATCH v4 4/7] OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform devices Tuan Phan
@ 2023-06-23 18:39 ` Tuan Phan
2023-06-28 16:47 ` Sunil V L
2023-06-23 18:39 ` [PATCH v4 6/7] OvmfPkg: RiscVVirt: Remove satp bare mode setting Tuan Phan
` (3 subsequent siblings)
8 siblings, 1 reply; 20+ messages in thread
From: Tuan Phan @ 2023-06-23 18:39 UTC (permalink / raw)
To: devel
Cc: michael.d.kinney, gaoliming, zhiguang.liu, sunilvl, git,
andrei.warkentin, ardb+tianocore, Tuan Phan
Make sure VirtNorFlashDxe loaded before VariableRuntimeDxe as it
is the backend flash driver.
Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
---
OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
index 21e4ba67379f..9ab8eb3ba7d8 100644
--- a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
+++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
@@ -53,6 +53,16 @@ READ_STATUS = TRUE
READ_LOCK_CAP = TRUE
READ_LOCK_STATUS = TRUE
+APRIORI DXE {
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+ INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
+ INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
+ INF EmbeddedPkg/Drivers/FdtClientDxe/FdtClientDxe.inf
+ INF UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
+ INF OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.inf
+}
+
#
# DXE Phase modules
#
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v4 6/7] OvmfPkg: RiscVVirt: Remove satp bare mode setting
2023-06-23 18:39 [PATCH v4 0/7] RISC-V: Add MMU support Tuan Phan
` (4 preceding siblings ...)
2023-06-23 18:39 ` [PATCH v4 5/7] OvmfPkg/RiscVVirt: Add VirtNorFlashDxe to APRIORI list Tuan Phan
@ 2023-06-23 18:39 ` Tuan Phan
2023-06-23 18:39 ` [PATCH v4 7/7] UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode Tuan Phan
` (2 subsequent siblings)
8 siblings, 0 replies; 20+ messages in thread
From: Tuan Phan @ 2023-06-23 18:39 UTC (permalink / raw)
To: devel
Cc: michael.d.kinney, gaoliming, zhiguang.liu, sunilvl, git,
andrei.warkentin, ardb+tianocore, Tuan Phan
There is no point to set satp to bare mode as that should be the
default mode when booting edk2.
Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
---
OvmfPkg/RiscVVirt/Sec/Memory.c | 18 ++----------------
1 file changed, 2 insertions(+), 16 deletions(-)
diff --git a/OvmfPkg/RiscVVirt/Sec/Memory.c b/OvmfPkg/RiscVVirt/Sec/Memory.c
index 0e2690c73687..aad71ee5dcbb 100644
--- a/OvmfPkg/RiscVVirt/Sec/Memory.c
+++ b/OvmfPkg/RiscVVirt/Sec/Memory.c
@@ -85,21 +85,6 @@ AddMemoryRangeHob (
AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
}
-/**
- Configure MMU
-**/
-STATIC
-VOID
-InitMmu (
- )
-{
- //
- // Set supervisor translation mode to Bare mode
- //
- RiscVSetSupervisorAddressTranslationRegister ((UINT64)SATP_MODE_OFF << 60);
- DEBUG ((DEBUG_INFO, "%a: Set Supervisor address mode to bare-metal mode.\n", __func__));
-}
-
/**
Publish system RAM and reserve memory regions.
@@ -327,7 +312,8 @@ MemoryPeimInitialization (
AddReservedMemoryMap (FdtPointer);
- InitMmu ();
+ /* Make sure SEC is booting with bare mode */
+ ASSERT ((RiscVGetSupervisorAddressTranslationRegister () & SATP64_MODE) == (SATP_MODE_OFF << SATP64_MODE_SHIFT));
BuildMemoryTypeInformationHob ();
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v4 7/7] UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode
2023-06-23 18:39 [PATCH v4 0/7] RISC-V: Add MMU support Tuan Phan
` (5 preceding siblings ...)
2023-06-23 18:39 ` [PATCH v4 6/7] OvmfPkg: RiscVVirt: Remove satp bare mode setting Tuan Phan
@ 2023-06-23 18:39 ` Tuan Phan
2023-07-14 10:24 ` Sunil V L
2023-06-25 8:45 ` [edk2-devel] UsbNetworkPkg not find in UDK 202305 stable version Yoshinoya
2023-07-15 5:21 ` [PATCH v4 0/7] RISC-V: Add MMU support Sunil V L
8 siblings, 1 reply; 20+ messages in thread
From: Tuan Phan @ 2023-06-23 18:39 UTC (permalink / raw)
To: devel
Cc: michael.d.kinney, gaoliming, zhiguang.liu, sunilvl, git,
andrei.warkentin, ardb+tianocore, Tuan Phan
During CpuDxe initialization, MMU will be setup with the highest
mode that HW supports.
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
---
OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 +
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 9 +-
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 2 +
UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf | 2 +
UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h | 39 ++
.../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 569 ++++++++++++++++++
.../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 26 +
.../Library/BaseRiscVMmuLib/RiscVMmuCore.S | 31 +
8 files changed, 677 insertions(+), 2 deletions(-)
create mode 100644 UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h
create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S
diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
index 731f54f73f81..bc204ba5fe52 100644
--- a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
+++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
@@ -83,6 +83,7 @@
# RISC-V Architectural Libraries
CpuExceptionHandlerLib|UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf
RiscVSbiLib|MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf
+ RiscVMmuLib|UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
PlatformBootManagerLib|OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
ResetSystemLib|OvmfPkg/RiscVVirt/Library/ResetSystemLib/BaseResetSystemLib.inf
diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
index 25fe3f54c325..2af3b6223450 100644
--- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
+++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
@@ -296,8 +296,7 @@ CpuSetMemoryAttributes (
IN UINT64 Attributes
)
{
- DEBUG ((DEBUG_INFO, "%a: Set memory attributes not supported yet\n", __func__));
- return EFI_SUCCESS;
+ return RiscVSetMemoryAttributes (BaseAddress, Length, Attributes);
}
/**
@@ -340,6 +339,12 @@ InitializeCpu (
//
DisableInterrupts ();
+ //
+ // Enable MMU
+ //
+ Status = RiscVConfigureMmu ();
+ ASSERT_EFI_ERROR (Status);
+
//
// Install Boot protocol
//
diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
index 49f4e119665a..68e6d038b66e 100644
--- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
+++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
@@ -15,11 +15,13 @@
#include <Protocol/Cpu.h>
#include <Protocol/RiscVBootProtocol.h>
#include <Library/BaseRiscVSbiLib.h>
+#include <Library/BaseRiscVMmuLib.h>
#include <Library/BaseLib.h>
#include <Library/CpuExceptionHandlerLib.h>
#include <Library/DebugLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiDriverEntryPoint.h>
+#include <Register/RiscV64/RiscVEncoding.h>
/**
Flush CPU data cache. If the instruction cache is fully coherent
diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf b/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
index e8fa25446aef..6d52085df0d5 100644
--- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
+++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
@@ -37,6 +37,8 @@
TimerLib
PeCoffGetEntryPointLib
RiscVSbiLib
+ RiscVMmuLib
+ CacheMaintenanceLib
[Sources]
CpuDxe.c
diff --git a/UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h b/UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h
new file mode 100644
index 000000000000..f71d6a4a1e7b
--- /dev/null
+++ b/UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h
@@ -0,0 +1,39 @@
+/** @file
+
+ Copyright (c) 2015 - 2016, Linaro Ltd. All rights reserved.<BR>
+ Copyright (c) 2023, Ventana Micro Systems Inc. All Rights Reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef BASE_RISCV_MMU_LIB_H_
+#define BASE_RISCV_MMU_LIB_H_
+
+VOID
+EFIAPI
+RiscVLocalTlbFlushAll (
+ VOID
+ );
+
+VOID
+EFIAPI
+RiscVLocalTlbFlush (
+ UINTN VirtAddr
+ );
+
+EFI_STATUS
+EFIAPI
+RiscVSetMemoryAttributes (
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
+ );
+
+EFI_STATUS
+EFIAPI
+RiscVConfigureMmu (
+ VOID
+ );
+
+#endif /* BASE_RISCV_MMU_LIB_H_ */
diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
new file mode 100644
index 000000000000..e6841b793bfc
--- /dev/null
+++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
@@ -0,0 +1,569 @@
+/** @file
+* MMU implementation for RISC-V
+*
+* Copyright (c) 2011-2020, ARM Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+* Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+* Copyright (c) 2023, Ventana Micro Systems Inc. All Rights Reserved.<BR>
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <PiDxe.h>
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/BaseRiscVMmuLib.h>
+#include <Library/CacheMaintenanceLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Register/RiscV64/RiscVEncoding.h>
+
+#define RISCV_PG_V BIT0
+#define RISCV_PG_R BIT1
+#define RISCV_PG_W BIT2
+#define RISCV_PG_X BIT3
+#define RISCV_PG_G BIT5
+#define RISCV_PG_A BIT6
+#define RISCV_PG_D BIT7
+#define PTE_ATTRIBUTES_MASK 0xE
+
+#define PTE_PPN_MASK 0x3FFFFFFFFFFC00ULL
+#define PTE_PPN_SHIFT 10
+#define RISCV_MMU_PAGE_SHIFT 12
+
+STATIC UINTN mMaxRootTableLevel;
+STATIC UINTN mBitPerLevel;
+STATIC UINTN mTableEntryCount;
+
+STATIC
+BOOLEAN
+RiscVMmuEnabled (
+ VOID
+ )
+{
+ return ((RiscVGetSupervisorAddressTranslationRegister () &
+ SATP64_MODE) != (SATP_MODE_OFF << SATP64_MODE_SHIFT));
+}
+
+STATIC
+UINTN
+RiscVGetRootTranslateTable (
+ VOID
+ )
+{
+ return (RiscVGetSupervisorAddressTranslationRegister () & SATP64_PPN) <<
+ RISCV_MMU_PAGE_SHIFT;
+}
+
+STATIC
+BOOLEAN
+IsValidPte (
+ IN UINTN Entry
+ )
+{
+ if (!(Entry & RISCV_PG_V) ||
+ (((Entry & (RISCV_PG_R | RISCV_PG_W)) == RISCV_PG_W)))
+ {
+ return FALSE;
+ }
+
+ return TRUE;
+}
+
+STATIC
+UINTN
+SetValidPte (
+ IN UINTN Entry
+ )
+{
+ /* Set Valid and Global mapping bits */
+ return Entry | RISCV_PG_G | RISCV_PG_V;
+}
+
+STATIC
+BOOLEAN
+IsBlockEntry (
+ IN UINTN Entry
+ )
+{
+ return IsValidPte (Entry) &&
+ (Entry & (RISCV_PG_X | RISCV_PG_R));
+}
+
+STATIC
+BOOLEAN
+IsTableEntry (
+ IN UINTN Entry
+ )
+{
+ return IsValidPte (Entry) &&
+ !IsBlockEntry (Entry);
+}
+
+STATIC
+UINTN
+SetTableEntry (
+ IN UINTN Entry
+ )
+{
+ Entry = SetValidPte (Entry);
+ Entry &= ~(RISCV_PG_X | RISCV_PG_W | RISCV_PG_R);
+
+ return Entry;
+}
+
+STATIC
+VOID
+ReplaceTableEntry (
+ IN UINTN *Entry,
+ IN UINTN Value,
+ IN UINTN RegionStart,
+ IN BOOLEAN IsLiveBlockMapping
+ )
+{
+ *Entry = Value;
+
+ if (IsLiveBlockMapping && RiscVMmuEnabled ()) {
+ RiscVLocalTlbFlush (RegionStart);
+ }
+}
+
+STATIC
+UINTN
+GetPpnfromPte (
+ UINTN Entry,
+ UINTN Level
+ )
+{
+ return ((Entry & PTE_PPN_MASK) >> PTE_PPN_SHIFT);
+}
+
+STATIC
+UINTN
+SetPpnToPte (
+ UINTN Entry,
+ UINTN Address,
+ UINTN Level
+ )
+{
+ UINTN Ppn;
+
+ Ppn = ((Address >> RISCV_MMU_PAGE_SHIFT) << PTE_PPN_SHIFT);
+ ASSERT (~(Ppn & ~PTE_PPN_MASK));
+ Entry &= ~PTE_PPN_MASK;
+ return Entry | Ppn;
+}
+
+STATIC
+VOID
+FreePageTablesRecursive (
+ IN UINTN *TranslationTable,
+ IN UINTN Level
+ )
+{
+ UINTN Index;
+
+ if (Level < mMaxRootTableLevel - 1) {
+ for (Index = 0; Index < mTableEntryCount; Index++) {
+ if (IsTableEntry (TranslationTable[Index])) {
+ FreePageTablesRecursive (
+ (UINTN *)(GetPpnfromPte ((TranslationTable[Index]), Level) <<
+ RISCV_MMU_PAGE_SHIFT),
+ Level + 1
+ );
+ }
+ }
+ }
+
+ FreePages (TranslationTable, 1);
+}
+
+STATIC
+EFI_STATUS
+UpdateRegionMappingRecursive (
+ IN UINTN RegionStart,
+ IN UINTN RegionEnd,
+ IN UINTN AttributeSetMask,
+ IN UINTN AttributeClearMask,
+ IN UINTN *PageTable,
+ IN UINTN Level,
+ IN BOOLEAN TableIsLive
+ )
+{
+ EFI_STATUS Status;
+ UINTN BlockShift;
+ UINTN BlockMask;
+ UINTN BlockEnd;
+ UINTN *Entry;
+ UINTN EntryValue;
+ UINTN *TranslationTable;
+ BOOLEAN NextTableIsLive;
+
+ ASSERT (Level < mMaxRootTableLevel);
+ ASSERT (((RegionStart | RegionEnd) & EFI_PAGE_MASK) == 0);
+
+ BlockShift = (mMaxRootTableLevel - Level - 1) * mBitPerLevel + RISCV_MMU_PAGE_SHIFT;
+ BlockMask = MAX_ADDRESS >> (64 - BlockShift);
+
+ DEBUG (
+ (
+ DEBUG_VERBOSE,
+ "%a(%d): %llx - %llx set %lx clr %lx\n",
+ __func__,
+ Level,
+ RegionStart,
+ RegionEnd,
+ AttributeSetMask,
+ AttributeClearMask
+ )
+ );
+
+ for ( ; RegionStart < RegionEnd; RegionStart = BlockEnd) {
+ BlockEnd = MIN (RegionEnd, (RegionStart | BlockMask) + 1);
+ Entry = &PageTable[(RegionStart >> BlockShift) & (mTableEntryCount - 1)];
+
+ //
+ // If RegionStart or BlockEnd is not aligned to the block size at this
+ // level, we will have to create a table mapping in order to map less
+ // than a block, and recurse to create the block or page entries at
+ // the next level. No block mappings are allowed at all at level 0,
+ // so in that case, we have to recurse unconditionally.
+ //
+ if ((Level == 0) ||
+ (((RegionStart | BlockEnd) & BlockMask) != 0) || IsTableEntry (*Entry))
+ {
+ ASSERT (Level < mMaxRootTableLevel - 1);
+ if (!IsTableEntry (*Entry)) {
+ //
+ // No table entry exists yet, so we need to allocate a page table
+ // for the next level.
+ //
+ TranslationTable = AllocatePages (1);
+ if (TranslationTable == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ ZeroMem (TranslationTable, EFI_PAGE_SIZE);
+
+ if (IsBlockEntry (*Entry)) {
+ //
+ // We are splitting an existing block entry, so we have to populate
+ // the new table with the attributes of the block entry it replaces.
+ //
+ Status = UpdateRegionMappingRecursive (
+ RegionStart & ~BlockMask,
+ (RegionStart | BlockMask) + 1,
+ *Entry & PTE_ATTRIBUTES_MASK,
+ PTE_ATTRIBUTES_MASK,
+ TranslationTable,
+ Level + 1,
+ FALSE
+ );
+ if (EFI_ERROR (Status)) {
+ //
+ // The range we passed to UpdateRegionMappingRecursive () is block
+ // aligned, so it is guaranteed that no further pages were allocated
+ // by it, and so we only have to free the page we allocated here.
+ //
+ FreePages (TranslationTable, 1);
+ return Status;
+ }
+ }
+
+ NextTableIsLive = FALSE;
+ } else {
+ TranslationTable = (UINTN *)(GetPpnfromPte (*Entry, Level) << RISCV_MMU_PAGE_SHIFT);
+ NextTableIsLive = TableIsLive;
+ }
+
+ //
+ // Recurse to the next level
+ //
+ Status = UpdateRegionMappingRecursive (
+ RegionStart,
+ BlockEnd,
+ AttributeSetMask,
+ AttributeClearMask,
+ TranslationTable,
+ Level + 1,
+ NextTableIsLive
+ );
+ if (EFI_ERROR (Status)) {
+ if (!IsTableEntry (*Entry)) {
+ //
+ // We are creating a new table entry, so on failure, we can free all
+ // allocations we made recursively, given that the whole subhierarchy
+ // has not been wired into the live page tables yet. (This is not
+ // possible for existing table entries, since we cannot revert the
+ // modifications we made to the subhierarchy it represents.)
+ //
+ FreePageTablesRecursive (TranslationTable, Level + 1);
+ }
+
+ return Status;
+ }
+
+ if (!IsTableEntry (*Entry)) {
+ EntryValue = SetPpnToPte (0, (UINTN)TranslationTable, Level);
+ EntryValue = SetTableEntry (EntryValue);
+ ReplaceTableEntry (
+ Entry,
+ EntryValue,
+ RegionStart,
+ TableIsLive
+ );
+ }
+ } else {
+ EntryValue = (*Entry & ~AttributeClearMask) | AttributeSetMask;
+ //
+ // We don't have page fault exception handler when a virtual page is accessed and
+ // the A bit is clear, or is written and the D bit is clear.
+ // So just set A for read and D for write permission.
+ //
+ if (AttributeSetMask & RISCV_PG_R) {
+ EntryValue |= RISCV_PG_A;
+ }
+
+ if (AttributeSetMask & RISCV_PG_W) {
+ EntryValue |= RISCV_PG_D;
+ }
+
+ EntryValue = SetPpnToPte (EntryValue, RegionStart, Level);
+ EntryValue = SetValidPte (EntryValue);
+ ReplaceTableEntry (Entry, EntryValue, RegionStart, TableIsLive);
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+UpdateRegionMapping (
+ IN UINTN RegionStart,
+ IN UINTN RegionLength,
+ IN UINTN AttributeSetMask,
+ IN UINTN AttributeClearMask,
+ IN UINTN *RootTable,
+ IN BOOLEAN TableIsLive
+ )
+{
+ if (((RegionStart | RegionLength) & EFI_PAGE_MASK) != 0) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return UpdateRegionMappingRecursive (
+ RegionStart,
+ RegionStart + RegionLength,
+ AttributeSetMask,
+ AttributeClearMask,
+ RootTable,
+ 0,
+ TableIsLive
+ );
+}
+
+STATIC
+UINTN
+GcdAttributeToPageAttribute (
+ IN UINTN GcdAttributes
+ )
+{
+ UINTN RiscVAttributes = RISCV_PG_R | RISCV_PG_W | RISCV_PG_X;
+
+ // Determine protection attributes
+ if (GcdAttributes & EFI_MEMORY_RO) {
+ RiscVAttributes &= ~(RISCV_PG_W);
+ }
+
+ // Process eXecute Never attribute
+ if (GcdAttributes & EFI_MEMORY_XP) {
+ RiscVAttributes &= ~RISCV_PG_X;
+ }
+
+ return RiscVAttributes;
+}
+
+EFI_STATUS
+EFIAPI
+RiscVSetMemoryAttributes (
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINTN Length,
+ IN UINTN Attributes
+ )
+{
+ UINTN PageAttributesSet = GcdAttributeToPageAttribute (Attributes);
+
+ if (!RiscVMmuEnabled ()) {
+ return EFI_SUCCESS;
+ }
+
+ DEBUG (
+ (
+ DEBUG_VERBOSE,
+ "%a: Set %llX page attribute 0x%X\n",
+ __func__,
+ BaseAddress,
+ PageAttributesSet
+ )
+ );
+
+ return UpdateRegionMapping (
+ BaseAddress,
+ Length,
+ PageAttributesSet,
+ PTE_ATTRIBUTES_MASK,
+ (UINTN *)RiscVGetRootTranslateTable (),
+ TRUE
+ );
+}
+
+STATIC
+EFI_STATUS
+RiscVMmuSetSatpMode (
+ UINTN SatpMode
+ )
+{
+ VOID *TranslationTable;
+ UINTN SatpReg;
+ UINTN Ppn;
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemoryMap;
+ UINTN NumberOfDescriptors;
+ UINTN Index;
+ EFI_STATUS Status;
+
+ switch (SatpMode) {
+ case SATP_MODE_OFF:
+ return EFI_SUCCESS;
+ case SATP_MODE_SV39:
+ mMaxRootTableLevel = 3;
+ mBitPerLevel = 9;
+ mTableEntryCount = 512;
+ break;
+ case SATP_MODE_SV48:
+ mMaxRootTableLevel = 4;
+ mBitPerLevel = 9;
+ mTableEntryCount = 512;
+ break;
+ case SATP_MODE_SV57:
+ mMaxRootTableLevel = 5;
+ mBitPerLevel = 9;
+ mTableEntryCount = 512;
+ break;
+ default:
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Allocate pages for translation table
+ TranslationTable = AllocatePages (1);
+ if (TranslationTable == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ ZeroMem (TranslationTable, mTableEntryCount * sizeof (UINTN));
+
+ NumberOfDescriptors = 0;
+ MemoryMap = NULL;
+ Status = gDS->GetMemorySpaceMap (
+ &NumberOfDescriptors,
+ &MemoryMap
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ for (Index = 0; Index < NumberOfDescriptors; Index++) {
+ if (MemoryMap[Index].GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo) {
+ // Default Read/Write attribute for memory mapped IO
+ UpdateRegionMapping (
+ MemoryMap[Index].BaseAddress,
+ MemoryMap[Index].Length,
+ RISCV_PG_R | RISCV_PG_W,
+ PTE_ATTRIBUTES_MASK,
+ TranslationTable,
+ FALSE
+ );
+ } else if (MemoryMap[Index].GcdMemoryType == EfiGcdMemoryTypeSystemMemory) {
+ // Default Read/Write/Execute attribute for system memory
+ UpdateRegionMapping (
+ MemoryMap[Index].BaseAddress,
+ MemoryMap[Index].Length,
+ RISCV_PG_R | RISCV_PG_W | RISCV_PG_X,
+ PTE_ATTRIBUTES_MASK,
+ TranslationTable,
+ FALSE
+ );
+ }
+ }
+
+ FreePool ((VOID *)MemoryMap);
+
+ if (GetInterruptState ()) {
+ DisableInterrupts ();
+ }
+
+ Ppn = (UINTN)TranslationTable >> RISCV_MMU_PAGE_SHIFT;
+ ASSERT (!(Ppn & ~(SATP64_PPN)));
+
+ SatpReg = Ppn;
+ SatpReg |= (SatpMode <<
+ SATP64_MODE_SHIFT) & SATP64_MODE;
+ RiscVSetSupervisorAddressTranslationRegister (SatpReg);
+ /* Check if HW support the setup satp mode */
+ if (SatpReg != RiscVGetSupervisorAddressTranslationRegister ()) {
+ DEBUG (
+ (
+ DEBUG_VERBOSE,
+ "%a: HW does not support SATP mode:%d\n",
+ __func__,
+ SatpMode
+ )
+ );
+ FreePageTablesRecursive (TranslationTable, 0);
+ return EFI_DEVICE_ERROR;
+ }
+
+ RiscVLocalTlbFlushAll ();
+
+ if (GetInterruptState ()) {
+ EnableInterrupts ();
+ }
+
+ return Status;
+}
+
+EFI_STATUS
+EFIAPI
+RiscVConfigureMmu (
+ VOID
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ INTN ModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48, SATP_MODE_SV39 };
+ INTN Idx;
+
+ /* Try to setup MMU with highest mode as possible */
+ for (Idx = 0; Idx < ARRAY_SIZE (ModeSupport); Idx++) {
+ Status = RiscVMmuSetSatpMode (ModeSupport[Idx]);
+ if (Status == EFI_DEVICE_ERROR) {
+ continue;
+ } else if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ DEBUG (
+ (
+ DEBUG_INFO,
+ "%a: SATP mode %d successfully configured\n",
+ __func__,
+ ModeSupport[Idx]
+ )
+ );
+ break;
+ }
+
+ return Status;
+}
diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
new file mode 100644
index 000000000000..2819c871b2a2
--- /dev/null
+++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
@@ -0,0 +1,26 @@
+## @file
+#
+# Copyright (c) 2023, Ventana Micro Systems Inc. All Rights Reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = BaseRiscVMmuLib
+ FILE_GUID = d3bc42ee-c9eb-4339-ba11-06747083d3ae
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVMmuLib
+
+[Sources]
+ BaseRiscVMmuLib.c
+ RiscVMmuCore.S
+
+[Packages]
+ MdePkg/MdePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+ BaseLib
diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S b/UefiCpuPkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S
new file mode 100644
index 000000000000..42eec4cbdf83
--- /dev/null
+++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S
@@ -0,0 +1,31 @@
+/** @file
+*
+* Copyright (c) 2023, Ventana Micro Systems Inc. All Rights Reserved.<BR>
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Base.h>
+#include <Register/RiscV64/RiscVImpl.h>
+
+.text
+ .align 3
+
+//
+// Local tlb flush all.
+//
+//
+ASM_FUNC (RiscVLocalTlbFlushAll)
+sfence.vma
+ret
+
+//
+// Local tlb flush at a virtual address
+// @retval a0 : virtual address.
+//
+ASM_FUNC (
+ RiscVLocalTlbFlush
+ )
+sfence.vma a0
+ret
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [edk2-devel] UsbNetworkPkg not find in UDK 202305 stable version
2023-06-23 18:39 [PATCH v4 0/7] RISC-V: Add MMU support Tuan Phan
` (6 preceding siblings ...)
2023-06-23 18:39 ` [PATCH v4 7/7] UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode Tuan Phan
@ 2023-06-25 8:45 ` Yoshinoya
2023-07-15 5:21 ` [PATCH v4 0/7] RISC-V: Add MMU support Sunil V L
8 siblings, 0 replies; 20+ messages in thread
From: Yoshinoya @ 2023-06-25 8:45 UTC (permalink / raw)
To: devel
[-- Attachment #1: Type: text/plain, Size: 303 bytes --]
Hello,
I have a question about UsbNetworkPkg.
UsbNetworkPkg not find in UDK 202305 stable version, so where could download it?
Here is a sample paste about UsbNetworkPkg
https://edk2.groups.io/g/devel/message/102688?p=%2C%2C%2C20%2C0%2C0%2C0%3A%3Acreated%2C0%2Cusb+lan%2C20%2C2%2C0%2C98122714
Thanks
[-- Attachment #2: Type: text/html, Size: 892 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 2/7] MdePkg/Register: RISC-V: Add satp mode bits shift definition
2023-06-23 18:39 ` [PATCH v4 2/7] MdePkg/Register: RISC-V: Add satp mode bits shift definition Tuan Phan
@ 2023-06-27 20:10 ` Michael D Kinney
0 siblings, 0 replies; 20+ messages in thread
From: Michael D Kinney @ 2023-06-27 20:10 UTC (permalink / raw)
To: Tuan Phan, devel@edk2.groups.io
Cc: Gao, Liming, Liu, Zhiguang, sunilvl@ventanamicro.com,
git@danielschaefer.me, Warkentin, Andrei,
ardb+tianocore@kernel.org, Kinney, Michael D
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
> -----Original Message-----
> From: Tuan Phan <tphan@ventanamicro.com>
> Sent: Friday, June 23, 2023 11:39 AM
> To: devel@edk2.groups.io
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming
> <gaoliming@byosoft.com.cn>; Liu, Zhiguang <zhiguang.liu@intel.com>;
> sunilvl@ventanamicro.com; git@danielschaefer.me; Warkentin, Andrei
> <andrei.warkentin@intel.com>; ardb+tianocore@kernel.org; Tuan Phan
> <tphan@ventanamicro.com>
> Subject: [PATCH v4 2/7] MdePkg/Register: RISC-V: Add satp mode bits shift
> definition
>
> The satp mode bits shift is used cross modules. It should be defined
> in one place.
>
> Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
> ---
> MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
> b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
> index 5c2989b797bf..2bde8db478ff 100644
> --- a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
> +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
> @@ -58,9 +58,10 @@
> #define PRV_S 1UL
>
> #define PRV_M 3UL
>
>
>
> -#define SATP64_MODE 0xF000000000000000ULL
>
> -#define SATP64_ASID 0x0FFFF00000000000ULL
>
> -#define SATP64_PPN 0x00000FFFFFFFFFFFULL
>
> +#define SATP64_MODE 0xF000000000000000ULL
>
> +#define SATP64_MODE_SHIFT 60
>
> +#define SATP64_ASID 0x0FFFF00000000000ULL
>
> +#define SATP64_PPN 0x00000FFFFFFFFFFFULL
>
>
>
> #define SATP_MODE_OFF 0UL
>
> #define SATP_MODE_SV32 1UL
>
> --
> 2.25.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 5/7] OvmfPkg/RiscVVirt: Add VirtNorFlashDxe to APRIORI list
2023-06-23 18:39 ` [PATCH v4 5/7] OvmfPkg/RiscVVirt: Add VirtNorFlashDxe to APRIORI list Tuan Phan
@ 2023-06-28 16:47 ` Sunil V L
2023-06-28 21:27 ` Tuan Phan
0 siblings, 1 reply; 20+ messages in thread
From: Sunil V L @ 2023-06-28 16:47 UTC (permalink / raw)
To: Tuan Phan
Cc: devel, michael.d.kinney, gaoliming, zhiguang.liu, git,
andrei.warkentin, ardb+tianocore
On Fri, Jun 23, 2023 at 11:39:32AM -0700, Tuan Phan wrote:
> Make sure VirtNorFlashDxe loaded before VariableRuntimeDxe as it
> is the backend flash driver.
>
> Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
> ---
> OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
> index 21e4ba67379f..9ab8eb3ba7d8 100644
> --- a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
> +++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
> @@ -53,6 +53,16 @@ READ_STATUS = TRUE
> READ_LOCK_CAP = TRUE
> READ_LOCK_STATUS = TRUE
>
> +APRIORI DXE {
> + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> + INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
> + INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
> + INF EmbeddedPkg/Drivers/FdtClientDxe/FdtClientDxe.inf
> + INF UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
> + INF OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.inf
> +}
> +
Hi Tuan,
Actually, Ard had recommended not to use APRIORI and hence we avoided
it when we upstreamed RiscVVirt. So, I am wondering whether this can be
avoided by using depex in CpuDxe on gEfiVariableArchProtocolGuid?
Thanks,
Sunil
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 5/7] OvmfPkg/RiscVVirt: Add VirtNorFlashDxe to APRIORI list
2023-06-28 16:47 ` Sunil V L
@ 2023-06-28 21:27 ` Tuan Phan
2023-07-04 5:07 ` Sunil V L
0 siblings, 1 reply; 20+ messages in thread
From: Tuan Phan @ 2023-06-28 21:27 UTC (permalink / raw)
To: Sunil V L
Cc: devel, michael.d.kinney, gaoliming, zhiguang.liu, git,
andrei.warkentin, ardb+tianocore
[-- Attachment #1: Type: text/plain, Size: 1979 bytes --]
On Wed, Jun 28, 2023 at 9:47 AM Sunil V L <sunilvl@ventanamicro.com> wrote:
> On Fri, Jun 23, 2023 at 11:39:32AM -0700, Tuan Phan wrote:
> > Make sure VirtNorFlashDxe loaded before VariableRuntimeDxe as it
> > is the backend flash driver.
> >
> > Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
> > ---
> > OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 10 ++++++++++
> > 1 file changed, 10 insertions(+)
> >
> > diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
> b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
> > index 21e4ba67379f..9ab8eb3ba7d8 100644
> > --- a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
> > +++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
> > @@ -53,6 +53,16 @@ READ_STATUS = TRUE
> > READ_LOCK_CAP = TRUE
> > READ_LOCK_STATUS = TRUE
> >
> > +APRIORI DXE {
> > + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> > + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> > + INF
> MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
> > + INF
> MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
> > + INF EmbeddedPkg/Drivers/FdtClientDxe/FdtClientDxe.inf
> > + INF UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
> > + INF OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.inf
> > +}
> > +
> Hi Tuan,
>
> Actually, Ard had recommended not to use APRIORI and hence we avoided
> it when we upstreamed RiscVVirt. So, I am wondering whether this can be
> avoided by using depex in CpuDxe on gEfiVariableArchProtocolGuid?
>
> Hi Sunil,
Not sure what the reason behind avoiding APRIORI besides it is a workaround
for broken DEPEX. BTW, what we need is to put VirtNorFlashDxe loaded before
VariableRuntimeDxe which doesn't depend on any modules. I don't see any
other clearer way than modifying VirNorFlashDxe as shown in the first
version of this series.
The CpuDxeRiscV64 in the aprioriy list as VirNorFlashDxe depends on it.
Thanks,
> Sunil
>
[-- Attachment #2: Type: text/html, Size: 2804 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 5/7] OvmfPkg/RiscVVirt: Add VirtNorFlashDxe to APRIORI list
2023-06-28 21:27 ` Tuan Phan
@ 2023-07-04 5:07 ` Sunil V L
2023-07-04 6:45 ` Tuan Phan
0 siblings, 1 reply; 20+ messages in thread
From: Sunil V L @ 2023-07-04 5:07 UTC (permalink / raw)
To: Tuan Phan
Cc: devel, michael.d.kinney, gaoliming, zhiguang.liu, git,
andrei.warkentin, ardb+tianocore
On Wed, Jun 28, 2023 at 02:27:10PM -0700, Tuan Phan wrote:
> On Wed, Jun 28, 2023 at 9:47 AM Sunil V L <sunilvl@ventanamicro.com> wrote:
>
> > On Fri, Jun 23, 2023 at 11:39:32AM -0700, Tuan Phan wrote:
> > > Make sure VirtNorFlashDxe loaded before VariableRuntimeDxe as it
> > > is the backend flash driver.
> > >
> > > Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
> > > ---
> > > OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 10 ++++++++++
> > > 1 file changed, 10 insertions(+)
> > >
> > > diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
> > b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
> > > index 21e4ba67379f..9ab8eb3ba7d8 100644
> > > --- a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
> > > +++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
> > > @@ -53,6 +53,16 @@ READ_STATUS = TRUE
> > > READ_LOCK_CAP = TRUE
> > > READ_LOCK_STATUS = TRUE
> > >
> > > +APRIORI DXE {
> > > + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> > > + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> > > + INF
> > MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
> > > + INF
> > MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
> > > + INF EmbeddedPkg/Drivers/FdtClientDxe/FdtClientDxe.inf
> > > + INF UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
> > > + INF OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.inf
> > > +}
> > > +
> > Hi Tuan,
> >
> > Actually, Ard had recommended not to use APRIORI and hence we avoided
> > it when we upstreamed RiscVVirt. So, I am wondering whether this can be
> > avoided by using depex in CpuDxe on gEfiVariableArchProtocolGuid?
> >
> > Hi Sunil,
> Not sure what the reason behind avoiding APRIORI besides it is a workaround
> for broken DEPEX. BTW, what we need is to put VirtNorFlashDxe loaded before
> VariableRuntimeDxe which doesn't depend on any modules. I don't see any
> other clearer way than modifying VirNorFlashDxe as shown in the first
> version of this series.
>
> The CpuDxeRiscV64 in the aprioriy list as VirNorFlashDxe depends on it.
>
Hi Tuan,
I couldn't locate old mail from Ard recommending to remove APRIORI in
RISC-V. But here is the recent mail on different context but those
reasons are still valid in any case.
https://edk2.groups.io/g/devel/message/104543
IMO, there is no dependency between VirtNorFlashDxe and
VariableRuntimeDxe. I think what we need is CpuDxeRiscV64 loaded after
VariableRuntimeDxe and before VirtNorFlashDxe. A simple depex like I
suggested in previous mail should work. I still prefer this than
introducing APRIORI unless there are other issues I am now aware of.
What do you think?
Thanks!
Sunil
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 5/7] OvmfPkg/RiscVVirt: Add VirtNorFlashDxe to APRIORI list
2023-07-04 5:07 ` Sunil V L
@ 2023-07-04 6:45 ` Tuan Phan
2023-07-04 7:01 ` Sunil V L
0 siblings, 1 reply; 20+ messages in thread
From: Tuan Phan @ 2023-07-04 6:45 UTC (permalink / raw)
To: Sunil V L
Cc: andrei.warkentin, ardb+tianocore, devel, gaoliming, git,
michael.d.kinney, zhiguang.liu
[-- Attachment #1: Type: text/plain, Size: 3053 bytes --]
As i said, VirtNorFlashDxe needed to be loaded before VariableRuntimeDxe so
your suggestion will not work.
On Mon, Jul 3, 2023 at 10:07 PM Sunil V L <sunilvl@ventanamicro.com> wrote:
> On Wed, Jun 28, 2023 at 02:27:10PM -0700, Tuan Phan wrote:
> > On Wed, Jun 28, 2023 at 9:47 AM Sunil V L <sunilvl@ventanamicro.com>
> wrote:
> >
> > > On Fri, Jun 23, 2023 at 11:39:32AM -0700, Tuan Phan wrote:
> > > > Make sure VirtNorFlashDxe loaded before VariableRuntimeDxe as it
> > > > is the backend flash driver.
> > > >
> > > > Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
> > > > ---
> > > > OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 10 ++++++++++
> > > > 1 file changed, 10 insertions(+)
> > > >
> > > > diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
> > > b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
> > > > index 21e4ba67379f..9ab8eb3ba7d8 100644
> > > > --- a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
> > > > +++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
> > > > @@ -53,6 +53,16 @@ READ_STATUS = TRUE
> > > > READ_LOCK_CAP = TRUE
> > > > READ_LOCK_STATUS = TRUE
> > > >
> > > > +APRIORI DXE {
> > > > + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> > > > + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> > > > + INF
> > >
> MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
> > > > + INF
> > >
> MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
> > > > + INF EmbeddedPkg/Drivers/FdtClientDxe/FdtClientDxe.inf
> > > > + INF UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
> > > > + INF OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.inf
> > > > +}
> > > > +
> > > Hi Tuan,
> > >
> > > Actually, Ard had recommended not to use APRIORI and hence we avoided
> > > it when we upstreamed RiscVVirt. So, I am wondering whether this can be
> > > avoided by using depex in CpuDxe on gEfiVariableArchProtocolGuid?
> > >
> > > Hi Sunil,
> > Not sure what the reason behind avoiding APRIORI besides it is a
> workaround
> > for broken DEPEX. BTW, what we need is to put VirtNorFlashDxe loaded
> before
> > VariableRuntimeDxe which doesn't depend on any modules. I don't see any
> > other clearer way than modifying VirNorFlashDxe as shown in the first
> > version of this series.
> >
> > The CpuDxeRiscV64 in the aprioriy list as VirNorFlashDxe depends on it.
> >
> Hi Tuan,
>
> I couldn't locate old mail from Ard recommending to remove APRIORI in
> RISC-V. But here is the recent mail on different context but those
> reasons are still valid in any case.
> https://edk2.groups.io/g/devel/message/104543
>
> IMO, there is no dependency between VirtNorFlashDxe and
> VariableRuntimeDxe. I think what we need is CpuDxeRiscV64 loaded after
> VariableRuntimeDxe and before VirtNorFlashDxe. A simple depex like I
> suggested in previous mail should work. I still prefer this than
> introducing APRIORI unless there are other issues I am now aware of.
> What do you think?
>
> Thanks!
> Sunil
>
[-- Attachment #2: Type: text/html, Size: 4208 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 5/7] OvmfPkg/RiscVVirt: Add VirtNorFlashDxe to APRIORI list
2023-07-04 6:45 ` Tuan Phan
@ 2023-07-04 7:01 ` Sunil V L
2023-07-13 19:08 ` Tuan Phan
0 siblings, 1 reply; 20+ messages in thread
From: Sunil V L @ 2023-07-04 7:01 UTC (permalink / raw)
To: Tuan Phan
Cc: andrei.warkentin, ardb+tianocore, devel, gaoliming, git,
michael.d.kinney, zhiguang.liu
On Mon, Jul 03, 2023 at 11:45:45PM -0700, Tuan Phan wrote:
> As i said, VirtNorFlashDxe needed to be loaded before VariableRuntimeDxe so
> your suggestion will not work.
>
Okay, at least for me, by removing APRIORI patch and adding this depex,
edk2 boots fine with your series. I am not sure what won't work.
Hi Ard, any thoughts? If no better way, may be we have to use APRIORI.
Thanks,
Sunil
> On Mon, Jul 3, 2023 at 10:07 PM Sunil V L <sunilvl@ventanamicro.com> wrote:
>
> > On Wed, Jun 28, 2023 at 02:27:10PM -0700, Tuan Phan wrote:
> > > On Wed, Jun 28, 2023 at 9:47 AM Sunil V L <sunilvl@ventanamicro.com>
> > wrote:
> > >
> > > > On Fri, Jun 23, 2023 at 11:39:32AM -0700, Tuan Phan wrote:
> > > > > Make sure VirtNorFlashDxe loaded before VariableRuntimeDxe as it
> > > > > is the backend flash driver.
> > > > >
> > > > > Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
> > > > > ---
> > > > > OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 10 ++++++++++
> > > > > 1 file changed, 10 insertions(+)
> > > > >
> > > > > diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
> > > > b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
> > > > > index 21e4ba67379f..9ab8eb3ba7d8 100644
> > > > > --- a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
> > > > > +++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
> > > > > @@ -53,6 +53,16 @@ READ_STATUS = TRUE
> > > > > READ_LOCK_CAP = TRUE
> > > > > READ_LOCK_STATUS = TRUE
> > > > >
> > > > > +APRIORI DXE {
> > > > > + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> > > > > + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> > > > > + INF
> > > >
> > MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
> > > > > + INF
> > > >
> > MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
> > > > > + INF EmbeddedPkg/Drivers/FdtClientDxe/FdtClientDxe.inf
> > > > > + INF UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
> > > > > + INF OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.inf
> > > > > +}
> > > > > +
> > > > Hi Tuan,
> > > >
> > > > Actually, Ard had recommended not to use APRIORI and hence we avoided
> > > > it when we upstreamed RiscVVirt. So, I am wondering whether this can be
> > > > avoided by using depex in CpuDxe on gEfiVariableArchProtocolGuid?
> > > >
> > > > Hi Sunil,
> > > Not sure what the reason behind avoiding APRIORI besides it is a
> > workaround
> > > for broken DEPEX. BTW, what we need is to put VirtNorFlashDxe loaded
> > before
> > > VariableRuntimeDxe which doesn't depend on any modules. I don't see any
> > > other clearer way than modifying VirNorFlashDxe as shown in the first
> > > version of this series.
> > >
> > > The CpuDxeRiscV64 in the aprioriy list as VirNorFlashDxe depends on it.
> > >
> > Hi Tuan,
> >
> > I couldn't locate old mail from Ard recommending to remove APRIORI in
> > RISC-V. But here is the recent mail on different context but those
> > reasons are still valid in any case.
> > https://edk2.groups.io/g/devel/message/104543
> >
> > IMO, there is no dependency between VirtNorFlashDxe and
> > VariableRuntimeDxe. I think what we need is CpuDxeRiscV64 loaded after
> > VariableRuntimeDxe and before VirtNorFlashDxe. A simple depex like I
> > suggested in previous mail should work. I still prefer this than
> > introducing APRIORI unless there are other issues I am now aware of.
> > What do you think?
> >
> > Thanks!
> > Sunil
> >
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 5/7] OvmfPkg/RiscVVirt: Add VirtNorFlashDxe to APRIORI list
2023-07-04 7:01 ` Sunil V L
@ 2023-07-13 19:08 ` Tuan Phan
2023-07-14 4:19 ` Sunil V L
0 siblings, 1 reply; 20+ messages in thread
From: Tuan Phan @ 2023-07-13 19:08 UTC (permalink / raw)
To: Sunil V L
Cc: andrei.warkentin, ardb+tianocore, devel, gaoliming, git,
michael.d.kinney, zhiguang.liu
[-- Attachment #1: Type: text/plain, Size: 4102 bytes --]
On Tue, Jul 4, 2023 at 12:01 AM Sunil V L <sunilvl@ventanamicro.com> wrote:
> On Mon, Jul 03, 2023 at 11:45:45PM -0700, Tuan Phan wrote:
> > As i said, VirtNorFlashDxe needed to be loaded before VariableRuntimeDxe
> so
> > your suggestion will not work.
> >
> Okay, at least for me, by removing APRIORI patch and adding this depex,
> edk2 boots fine with your series. I am not sure what won't work.
>
> Hi Ard, any thoughts? If no better way, may be we have to use APRIORI.
>
It doesn't work as your workaround trying to make CpuDxe depends on
variable protocol which has nothing to do with it. Also, CpuDxe is an
essential module and should not depend on anything, what happens if the
variable driver before generating the protocol tries to use CPU protocol?
It is worse than having APRIORI workaround.
>
> Thanks,
> Sunil
> > On Mon, Jul 3, 2023 at 10:07 PM Sunil V L <sunilvl@ventanamicro.com>
> wrote:
> >
> > > On Wed, Jun 28, 2023 at 02:27:10PM -0700, Tuan Phan wrote:
> > > > On Wed, Jun 28, 2023 at 9:47 AM Sunil V L <sunilvl@ventanamicro.com>
> > > wrote:
> > > >
> > > > > On Fri, Jun 23, 2023 at 11:39:32AM -0700, Tuan Phan wrote:
> > > > > > Make sure VirtNorFlashDxe loaded before VariableRuntimeDxe as it
> > > > > > is the backend flash driver.
> > > > > >
> > > > > > Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
> > > > > > ---
> > > > > > OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 10 ++++++++++
> > > > > > 1 file changed, 10 insertions(+)
> > > > > >
> > > > > > diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
> > > > > b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
> > > > > > index 21e4ba67379f..9ab8eb3ba7d8 100644
> > > > > > --- a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
> > > > > > +++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
> > > > > > @@ -53,6 +53,16 @@ READ_STATUS = TRUE
> > > > > > READ_LOCK_CAP = TRUE
> > > > > > READ_LOCK_STATUS = TRUE
> > > > > >
> > > > > > +APRIORI DXE {
> > > > > > + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> > > > > > + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> > > > > > + INF
> > > > >
> > >
> MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
> > > > > > + INF
> > > > >
> > >
> MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
> > > > > > + INF EmbeddedPkg/Drivers/FdtClientDxe/FdtClientDxe.inf
> > > > > > + INF UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
> > > > > > + INF OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.inf
> > > > > > +}
> > > > > > +
> > > > > Hi Tuan,
> > > > >
> > > > > Actually, Ard had recommended not to use APRIORI and hence we
> avoided
> > > > > it when we upstreamed RiscVVirt. So, I am wondering whether this
> can be
> > > > > avoided by using depex in CpuDxe on gEfiVariableArchProtocolGuid?
> > > > >
> > > > > Hi Sunil,
> > > > Not sure what the reason behind avoiding APRIORI besides it is a
> > > workaround
> > > > for broken DEPEX. BTW, what we need is to put VirtNorFlashDxe loaded
> > > before
> > > > VariableRuntimeDxe which doesn't depend on any modules. I don't see
> any
> > > > other clearer way than modifying VirNorFlashDxe as shown in the first
> > > > version of this series.
> > > >
> > > > The CpuDxeRiscV64 in the aprioriy list as VirNorFlashDxe depends on
> it.
> > > >
> > > Hi Tuan,
> > >
> > > I couldn't locate old mail from Ard recommending to remove APRIORI in
> > > RISC-V. But here is the recent mail on different context but those
> > > reasons are still valid in any case.
> > > https://edk2.groups.io/g/devel/message/104543
> > >
> > > IMO, there is no dependency between VirtNorFlashDxe and
> > > VariableRuntimeDxe. I think what we need is CpuDxeRiscV64 loaded after
> > > VariableRuntimeDxe and before VirtNorFlashDxe. A simple depex like I
> > > suggested in previous mail should work. I still prefer this than
> > > introducing APRIORI unless there are other issues I am now aware of.
> > > What do you think?
> > >
> > > Thanks!
> > > Sunil
> > >
>
[-- Attachment #2: Type: text/html, Size: 5805 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 5/7] OvmfPkg/RiscVVirt: Add VirtNorFlashDxe to APRIORI list
2023-07-13 19:08 ` Tuan Phan
@ 2023-07-14 4:19 ` Sunil V L
0 siblings, 0 replies; 20+ messages in thread
From: Sunil V L @ 2023-07-14 4:19 UTC (permalink / raw)
To: Tuan Phan
Cc: andrei.warkentin, ardb+tianocore, devel, gaoliming, git,
michael.d.kinney, zhiguang.liu
On Thu, Jul 13, 2023 at 12:08:02PM -0700, Tuan Phan wrote:
> On Tue, Jul 4, 2023 at 12:01 AM Sunil V L <sunilvl@ventanamicro.com> wrote:
>
> > On Mon, Jul 03, 2023 at 11:45:45PM -0700, Tuan Phan wrote:
> > > As i said, VirtNorFlashDxe needed to be loaded before VariableRuntimeDxe
> > so
> > > your suggestion will not work.
> > >
> > Okay, at least for me, by removing APRIORI patch and adding this depex,
> > edk2 boots fine with your series. I am not sure what won't work.
> >
> > Hi Ard, any thoughts? If no better way, may be we have to use APRIORI.
> >
> It doesn't work as your workaround trying to make CpuDxe depends on
> variable protocol which has nothing to do with it. Also, CpuDxe is an
> essential module and should not depend on anything, what happens if the
> variable driver before generating the protocol tries to use CPU protocol?
> It is worse than having APRIORI workaround.
>
Okay. Thanks!. Let's go with this solution for now. But let me do some
tests to ensure this builds fine with CLANG and then merge.
Thanks,
Sunil
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 7/7] UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode
2023-06-23 18:39 ` [PATCH v4 7/7] UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode Tuan Phan
@ 2023-07-14 10:24 ` Sunil V L
2023-07-14 19:10 ` Tuan Phan
0 siblings, 1 reply; 20+ messages in thread
From: Sunil V L @ 2023-07-14 10:24 UTC (permalink / raw)
To: Tuan Phan
Cc: devel, michael.d.kinney, gaoliming, zhiguang.liu, git,
andrei.warkentin, ardb+tianocore
On Fri, Jun 23, 2023 at 11:39:34AM -0700, Tuan Phan wrote:
> During CpuDxe initialization, MMU will be setup with the highest
> mode that HW supports.
>
> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
> Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
> ---
Hi Tuan,
CI tests are failing for these changes primarily due to code formatting
errors. Can you please fix them and send the next version?
Thanks,
Sunil
> OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 +
> UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 9 +-
> UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 2 +
> UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf | 2 +
> UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h | 39 ++
> .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 569 ++++++++++++++++++
> .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 26 +
> .../Library/BaseRiscVMmuLib/RiscVMmuCore.S | 31 +
> 8 files changed, 677 insertions(+), 2 deletions(-)
> create mode 100644 UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h
> create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S
>
> diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
> index 731f54f73f81..bc204ba5fe52 100644
> --- a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
> +++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
> @@ -83,6 +83,7 @@
> # RISC-V Architectural Libraries
> CpuExceptionHandlerLib|UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf
> RiscVSbiLib|MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf
> + RiscVMmuLib|UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> PlatformBootManagerLib|OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
> ResetSystemLib|OvmfPkg/RiscVVirt/Library/ResetSystemLib/BaseResetSystemLib.inf
>
> diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
> index 25fe3f54c325..2af3b6223450 100644
> --- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
> +++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
> @@ -296,8 +296,7 @@ CpuSetMemoryAttributes (
> IN UINT64 Attributes
> )
> {
> - DEBUG ((DEBUG_INFO, "%a: Set memory attributes not supported yet\n", __func__));
> - return EFI_SUCCESS;
> + return RiscVSetMemoryAttributes (BaseAddress, Length, Attributes);
> }
>
> /**
> @@ -340,6 +339,12 @@ InitializeCpu (
> //
> DisableInterrupts ();
>
> + //
> + // Enable MMU
> + //
> + Status = RiscVConfigureMmu ();
> + ASSERT_EFI_ERROR (Status);
> +
> //
> // Install Boot protocol
> //
> diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
> index 49f4e119665a..68e6d038b66e 100644
> --- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
> +++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
> @@ -15,11 +15,13 @@
> #include <Protocol/Cpu.h>
> #include <Protocol/RiscVBootProtocol.h>
> #include <Library/BaseRiscVSbiLib.h>
> +#include <Library/BaseRiscVMmuLib.h>
> #include <Library/BaseLib.h>
> #include <Library/CpuExceptionHandlerLib.h>
> #include <Library/DebugLib.h>
> #include <Library/UefiBootServicesTableLib.h>
> #include <Library/UefiDriverEntryPoint.h>
> +#include <Register/RiscV64/RiscVEncoding.h>
>
> /**
> Flush CPU data cache. If the instruction cache is fully coherent
> diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf b/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
> index e8fa25446aef..6d52085df0d5 100644
> --- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
> +++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
> @@ -37,6 +37,8 @@
> TimerLib
> PeCoffGetEntryPointLib
> RiscVSbiLib
> + RiscVMmuLib
> + CacheMaintenanceLib
>
> [Sources]
> CpuDxe.c
> diff --git a/UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h b/UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h
> new file mode 100644
> index 000000000000..f71d6a4a1e7b
> --- /dev/null
> +++ b/UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h
> @@ -0,0 +1,39 @@
> +/** @file
> +
> + Copyright (c) 2015 - 2016, Linaro Ltd. All rights reserved.<BR>
> + Copyright (c) 2023, Ventana Micro Systems Inc. All Rights Reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef BASE_RISCV_MMU_LIB_H_
> +#define BASE_RISCV_MMU_LIB_H_
> +
> +VOID
> +EFIAPI
> +RiscVLocalTlbFlushAll (
> + VOID
> + );
> +
> +VOID
> +EFIAPI
> +RiscVLocalTlbFlush (
> + UINTN VirtAddr
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +RiscVSetMemoryAttributes (
> + IN EFI_PHYSICAL_ADDRESS BaseAddress,
> + IN UINT64 Length,
> + IN UINT64 Attributes
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +RiscVConfigureMmu (
> + VOID
> + );
> +
> +#endif /* BASE_RISCV_MMU_LIB_H_ */
> diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> new file mode 100644
> index 000000000000..e6841b793bfc
> --- /dev/null
> +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> @@ -0,0 +1,569 @@
> +/** @file
> +* MMU implementation for RISC-V
> +*
> +* Copyright (c) 2011-2020, ARM Limited. All rights reserved.
> +* Copyright (c) 2016, Linaro Limited. All rights reserved.
> +* Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +* Copyright (c) 2023, Ventana Micro Systems Inc. All Rights Reserved.<BR>
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +
> +#include <PiDxe.h>
> +#include <Uefi.h>
> +#include <Library/BaseLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/BaseRiscVMmuLib.h>
> +#include <Library/CacheMaintenanceLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/DxeServicesTableLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/PcdLib.h>
> +#include <Register/RiscV64/RiscVEncoding.h>
> +
> +#define RISCV_PG_V BIT0
> +#define RISCV_PG_R BIT1
> +#define RISCV_PG_W BIT2
> +#define RISCV_PG_X BIT3
> +#define RISCV_PG_G BIT5
> +#define RISCV_PG_A BIT6
> +#define RISCV_PG_D BIT7
> +#define PTE_ATTRIBUTES_MASK 0xE
> +
> +#define PTE_PPN_MASK 0x3FFFFFFFFFFC00ULL
> +#define PTE_PPN_SHIFT 10
> +#define RISCV_MMU_PAGE_SHIFT 12
> +
> +STATIC UINTN mMaxRootTableLevel;
> +STATIC UINTN mBitPerLevel;
> +STATIC UINTN mTableEntryCount;
> +
> +STATIC
> +BOOLEAN
> +RiscVMmuEnabled (
> + VOID
> + )
> +{
> + return ((RiscVGetSupervisorAddressTranslationRegister () &
> + SATP64_MODE) != (SATP_MODE_OFF << SATP64_MODE_SHIFT));
> +}
> +
> +STATIC
> +UINTN
> +RiscVGetRootTranslateTable (
> + VOID
> + )
> +{
> + return (RiscVGetSupervisorAddressTranslationRegister () & SATP64_PPN) <<
> + RISCV_MMU_PAGE_SHIFT;
> +}
> +
> +STATIC
> +BOOLEAN
> +IsValidPte (
> + IN UINTN Entry
> + )
> +{
> + if (!(Entry & RISCV_PG_V) ||
> + (((Entry & (RISCV_PG_R | RISCV_PG_W)) == RISCV_PG_W)))
> + {
> + return FALSE;
> + }
> +
> + return TRUE;
> +}
> +
> +STATIC
> +UINTN
> +SetValidPte (
> + IN UINTN Entry
> + )
> +{
> + /* Set Valid and Global mapping bits */
> + return Entry | RISCV_PG_G | RISCV_PG_V;
> +}
> +
> +STATIC
> +BOOLEAN
> +IsBlockEntry (
> + IN UINTN Entry
> + )
> +{
> + return IsValidPte (Entry) &&
> + (Entry & (RISCV_PG_X | RISCV_PG_R));
> +}
> +
> +STATIC
> +BOOLEAN
> +IsTableEntry (
> + IN UINTN Entry
> + )
> +{
> + return IsValidPte (Entry) &&
> + !IsBlockEntry (Entry);
> +}
> +
> +STATIC
> +UINTN
> +SetTableEntry (
> + IN UINTN Entry
> + )
> +{
> + Entry = SetValidPte (Entry);
> + Entry &= ~(RISCV_PG_X | RISCV_PG_W | RISCV_PG_R);
> +
> + return Entry;
> +}
> +
> +STATIC
> +VOID
> +ReplaceTableEntry (
> + IN UINTN *Entry,
> + IN UINTN Value,
> + IN UINTN RegionStart,
> + IN BOOLEAN IsLiveBlockMapping
> + )
> +{
> + *Entry = Value;
> +
> + if (IsLiveBlockMapping && RiscVMmuEnabled ()) {
> + RiscVLocalTlbFlush (RegionStart);
> + }
> +}
> +
> +STATIC
> +UINTN
> +GetPpnfromPte (
> + UINTN Entry,
> + UINTN Level
> + )
> +{
> + return ((Entry & PTE_PPN_MASK) >> PTE_PPN_SHIFT);
> +}
> +
> +STATIC
> +UINTN
> +SetPpnToPte (
> + UINTN Entry,
> + UINTN Address,
> + UINTN Level
> + )
> +{
> + UINTN Ppn;
> +
> + Ppn = ((Address >> RISCV_MMU_PAGE_SHIFT) << PTE_PPN_SHIFT);
> + ASSERT (~(Ppn & ~PTE_PPN_MASK));
> + Entry &= ~PTE_PPN_MASK;
> + return Entry | Ppn;
> +}
> +
> +STATIC
> +VOID
> +FreePageTablesRecursive (
> + IN UINTN *TranslationTable,
> + IN UINTN Level
> + )
> +{
> + UINTN Index;
> +
> + if (Level < mMaxRootTableLevel - 1) {
> + for (Index = 0; Index < mTableEntryCount; Index++) {
> + if (IsTableEntry (TranslationTable[Index])) {
> + FreePageTablesRecursive (
> + (UINTN *)(GetPpnfromPte ((TranslationTable[Index]), Level) <<
> + RISCV_MMU_PAGE_SHIFT),
> + Level + 1
> + );
> + }
> + }
> + }
> +
> + FreePages (TranslationTable, 1);
> +}
> +
> +STATIC
> +EFI_STATUS
> +UpdateRegionMappingRecursive (
> + IN UINTN RegionStart,
> + IN UINTN RegionEnd,
> + IN UINTN AttributeSetMask,
> + IN UINTN AttributeClearMask,
> + IN UINTN *PageTable,
> + IN UINTN Level,
> + IN BOOLEAN TableIsLive
> + )
> +{
> + EFI_STATUS Status;
> + UINTN BlockShift;
> + UINTN BlockMask;
> + UINTN BlockEnd;
> + UINTN *Entry;
> + UINTN EntryValue;
> + UINTN *TranslationTable;
> + BOOLEAN NextTableIsLive;
> +
> + ASSERT (Level < mMaxRootTableLevel);
> + ASSERT (((RegionStart | RegionEnd) & EFI_PAGE_MASK) == 0);
> +
> + BlockShift = (mMaxRootTableLevel - Level - 1) * mBitPerLevel + RISCV_MMU_PAGE_SHIFT;
> + BlockMask = MAX_ADDRESS >> (64 - BlockShift);
> +
> + DEBUG (
> + (
> + DEBUG_VERBOSE,
> + "%a(%d): %llx - %llx set %lx clr %lx\n",
> + __func__,
> + Level,
> + RegionStart,
> + RegionEnd,
> + AttributeSetMask,
> + AttributeClearMask
> + )
> + );
> +
> + for ( ; RegionStart < RegionEnd; RegionStart = BlockEnd) {
> + BlockEnd = MIN (RegionEnd, (RegionStart | BlockMask) + 1);
> + Entry = &PageTable[(RegionStart >> BlockShift) & (mTableEntryCount - 1)];
> +
> + //
> + // If RegionStart or BlockEnd is not aligned to the block size at this
> + // level, we will have to create a table mapping in order to map less
> + // than a block, and recurse to create the block or page entries at
> + // the next level. No block mappings are allowed at all at level 0,
> + // so in that case, we have to recurse unconditionally.
> + //
> + if ((Level == 0) ||
> + (((RegionStart | BlockEnd) & BlockMask) != 0) || IsTableEntry (*Entry))
> + {
> + ASSERT (Level < mMaxRootTableLevel - 1);
> + if (!IsTableEntry (*Entry)) {
> + //
> + // No table entry exists yet, so we need to allocate a page table
> + // for the next level.
> + //
> + TranslationTable = AllocatePages (1);
> + if (TranslationTable == NULL) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + ZeroMem (TranslationTable, EFI_PAGE_SIZE);
> +
> + if (IsBlockEntry (*Entry)) {
> + //
> + // We are splitting an existing block entry, so we have to populate
> + // the new table with the attributes of the block entry it replaces.
> + //
> + Status = UpdateRegionMappingRecursive (
> + RegionStart & ~BlockMask,
> + (RegionStart | BlockMask) + 1,
> + *Entry & PTE_ATTRIBUTES_MASK,
> + PTE_ATTRIBUTES_MASK,
> + TranslationTable,
> + Level + 1,
> + FALSE
> + );
> + if (EFI_ERROR (Status)) {
> + //
> + // The range we passed to UpdateRegionMappingRecursive () is block
> + // aligned, so it is guaranteed that no further pages were allocated
> + // by it, and so we only have to free the page we allocated here.
> + //
> + FreePages (TranslationTable, 1);
> + return Status;
> + }
> + }
> +
> + NextTableIsLive = FALSE;
> + } else {
> + TranslationTable = (UINTN *)(GetPpnfromPte (*Entry, Level) << RISCV_MMU_PAGE_SHIFT);
> + NextTableIsLive = TableIsLive;
> + }
> +
> + //
> + // Recurse to the next level
> + //
> + Status = UpdateRegionMappingRecursive (
> + RegionStart,
> + BlockEnd,
> + AttributeSetMask,
> + AttributeClearMask,
> + TranslationTable,
> + Level + 1,
> + NextTableIsLive
> + );
> + if (EFI_ERROR (Status)) {
> + if (!IsTableEntry (*Entry)) {
> + //
> + // We are creating a new table entry, so on failure, we can free all
> + // allocations we made recursively, given that the whole subhierarchy
> + // has not been wired into the live page tables yet. (This is not
> + // possible for existing table entries, since we cannot revert the
> + // modifications we made to the subhierarchy it represents.)
> + //
> + FreePageTablesRecursive (TranslationTable, Level + 1);
> + }
> +
> + return Status;
> + }
> +
> + if (!IsTableEntry (*Entry)) {
> + EntryValue = SetPpnToPte (0, (UINTN)TranslationTable, Level);
> + EntryValue = SetTableEntry (EntryValue);
> + ReplaceTableEntry (
> + Entry,
> + EntryValue,
> + RegionStart,
> + TableIsLive
> + );
> + }
> + } else {
> + EntryValue = (*Entry & ~AttributeClearMask) | AttributeSetMask;
> + //
> + // We don't have page fault exception handler when a virtual page is accessed and
> + // the A bit is clear, or is written and the D bit is clear.
> + // So just set A for read and D for write permission.
> + //
> + if (AttributeSetMask & RISCV_PG_R) {
> + EntryValue |= RISCV_PG_A;
> + }
> +
> + if (AttributeSetMask & RISCV_PG_W) {
> + EntryValue |= RISCV_PG_D;
> + }
> +
> + EntryValue = SetPpnToPte (EntryValue, RegionStart, Level);
> + EntryValue = SetValidPte (EntryValue);
> + ReplaceTableEntry (Entry, EntryValue, RegionStart, TableIsLive);
> + }
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +STATIC
> +EFI_STATUS
> +UpdateRegionMapping (
> + IN UINTN RegionStart,
> + IN UINTN RegionLength,
> + IN UINTN AttributeSetMask,
> + IN UINTN AttributeClearMask,
> + IN UINTN *RootTable,
> + IN BOOLEAN TableIsLive
> + )
> +{
> + if (((RegionStart | RegionLength) & EFI_PAGE_MASK) != 0) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + return UpdateRegionMappingRecursive (
> + RegionStart,
> + RegionStart + RegionLength,
> + AttributeSetMask,
> + AttributeClearMask,
> + RootTable,
> + 0,
> + TableIsLive
> + );
> +}
> +
> +STATIC
> +UINTN
> +GcdAttributeToPageAttribute (
> + IN UINTN GcdAttributes
> + )
> +{
> + UINTN RiscVAttributes = RISCV_PG_R | RISCV_PG_W | RISCV_PG_X;
> +
> + // Determine protection attributes
> + if (GcdAttributes & EFI_MEMORY_RO) {
> + RiscVAttributes &= ~(RISCV_PG_W);
> + }
> +
> + // Process eXecute Never attribute
> + if (GcdAttributes & EFI_MEMORY_XP) {
> + RiscVAttributes &= ~RISCV_PG_X;
> + }
> +
> + return RiscVAttributes;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +RiscVSetMemoryAttributes (
> + IN EFI_PHYSICAL_ADDRESS BaseAddress,
> + IN UINTN Length,
> + IN UINTN Attributes
> + )
> +{
> + UINTN PageAttributesSet = GcdAttributeToPageAttribute (Attributes);
> +
> + if (!RiscVMmuEnabled ()) {
> + return EFI_SUCCESS;
> + }
> +
> + DEBUG (
> + (
> + DEBUG_VERBOSE,
> + "%a: Set %llX page attribute 0x%X\n",
> + __func__,
> + BaseAddress,
> + PageAttributesSet
> + )
> + );
> +
> + return UpdateRegionMapping (
> + BaseAddress,
> + Length,
> + PageAttributesSet,
> + PTE_ATTRIBUTES_MASK,
> + (UINTN *)RiscVGetRootTranslateTable (),
> + TRUE
> + );
> +}
> +
> +STATIC
> +EFI_STATUS
> +RiscVMmuSetSatpMode (
> + UINTN SatpMode
> + )
> +{
> + VOID *TranslationTable;
> + UINTN SatpReg;
> + UINTN Ppn;
> + EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemoryMap;
> + UINTN NumberOfDescriptors;
> + UINTN Index;
> + EFI_STATUS Status;
> +
> + switch (SatpMode) {
> + case SATP_MODE_OFF:
> + return EFI_SUCCESS;
> + case SATP_MODE_SV39:
> + mMaxRootTableLevel = 3;
> + mBitPerLevel = 9;
> + mTableEntryCount = 512;
> + break;
> + case SATP_MODE_SV48:
> + mMaxRootTableLevel = 4;
> + mBitPerLevel = 9;
> + mTableEntryCount = 512;
> + break;
> + case SATP_MODE_SV57:
> + mMaxRootTableLevel = 5;
> + mBitPerLevel = 9;
> + mTableEntryCount = 512;
> + break;
> + default:
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + // Allocate pages for translation table
> + TranslationTable = AllocatePages (1);
> + if (TranslationTable == NULL) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + ZeroMem (TranslationTable, mTableEntryCount * sizeof (UINTN));
> +
> + NumberOfDescriptors = 0;
> + MemoryMap = NULL;
> + Status = gDS->GetMemorySpaceMap (
> + &NumberOfDescriptors,
> + &MemoryMap
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + for (Index = 0; Index < NumberOfDescriptors; Index++) {
> + if (MemoryMap[Index].GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo) {
> + // Default Read/Write attribute for memory mapped IO
> + UpdateRegionMapping (
> + MemoryMap[Index].BaseAddress,
> + MemoryMap[Index].Length,
> + RISCV_PG_R | RISCV_PG_W,
> + PTE_ATTRIBUTES_MASK,
> + TranslationTable,
> + FALSE
> + );
> + } else if (MemoryMap[Index].GcdMemoryType == EfiGcdMemoryTypeSystemMemory) {
> + // Default Read/Write/Execute attribute for system memory
> + UpdateRegionMapping (
> + MemoryMap[Index].BaseAddress,
> + MemoryMap[Index].Length,
> + RISCV_PG_R | RISCV_PG_W | RISCV_PG_X,
> + PTE_ATTRIBUTES_MASK,
> + TranslationTable,
> + FALSE
> + );
> + }
> + }
> +
> + FreePool ((VOID *)MemoryMap);
> +
> + if (GetInterruptState ()) {
> + DisableInterrupts ();
> + }
> +
> + Ppn = (UINTN)TranslationTable >> RISCV_MMU_PAGE_SHIFT;
> + ASSERT (!(Ppn & ~(SATP64_PPN)));
> +
> + SatpReg = Ppn;
> + SatpReg |= (SatpMode <<
> + SATP64_MODE_SHIFT) & SATP64_MODE;
> + RiscVSetSupervisorAddressTranslationRegister (SatpReg);
> + /* Check if HW support the setup satp mode */
> + if (SatpReg != RiscVGetSupervisorAddressTranslationRegister ()) {
> + DEBUG (
> + (
> + DEBUG_VERBOSE,
> + "%a: HW does not support SATP mode:%d\n",
> + __func__,
> + SatpMode
> + )
> + );
> + FreePageTablesRecursive (TranslationTable, 0);
> + return EFI_DEVICE_ERROR;
> + }
> +
> + RiscVLocalTlbFlushAll ();
> +
> + if (GetInterruptState ()) {
> + EnableInterrupts ();
> + }
> +
> + return Status;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +RiscVConfigureMmu (
> + VOID
> + )
> +{
> + EFI_STATUS Status = EFI_SUCCESS;
> + INTN ModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48, SATP_MODE_SV39 };
> + INTN Idx;
> +
> + /* Try to setup MMU with highest mode as possible */
> + for (Idx = 0; Idx < ARRAY_SIZE (ModeSupport); Idx++) {
> + Status = RiscVMmuSetSatpMode (ModeSupport[Idx]);
> + if (Status == EFI_DEVICE_ERROR) {
> + continue;
> + } else if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + DEBUG (
> + (
> + DEBUG_INFO,
> + "%a: SATP mode %d successfully configured\n",
> + __func__,
> + ModeSupport[Idx]
> + )
> + );
> + break;
> + }
> +
> + return Status;
> +}
> diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> new file mode 100644
> index 000000000000..2819c871b2a2
> --- /dev/null
> +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> @@ -0,0 +1,26 @@
> +## @file
> +#
> +# Copyright (c) 2023, Ventana Micro Systems Inc. All Rights Reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001b
> + BASE_NAME = BaseRiscVMmuLib
> + FILE_GUID = d3bc42ee-c9eb-4339-ba11-06747083d3ae
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = RiscVMmuLib
> +
> +[Sources]
> + BaseRiscVMmuLib.c
> + RiscVMmuCore.S
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + UefiCpuPkg/UefiCpuPkg.dec
> +
> +[LibraryClasses]
> + BaseLib
> diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S b/UefiCpuPkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S
> new file mode 100644
> index 000000000000..42eec4cbdf83
> --- /dev/null
> +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S
> @@ -0,0 +1,31 @@
> +/** @file
> +*
> +* Copyright (c) 2023, Ventana Micro Systems Inc. All Rights Reserved.<BR>
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +
> +#include <Base.h>
> +#include <Register/RiscV64/RiscVImpl.h>
> +
> +.text
> + .align 3
> +
> +//
> +// Local tlb flush all.
> +//
> +//
> +ASM_FUNC (RiscVLocalTlbFlushAll)
> +sfence.vma
> +ret
> +
> +//
> +// Local tlb flush at a virtual address
> +// @retval a0 : virtual address.
> +//
> +ASM_FUNC (
> + RiscVLocalTlbFlush
> + )
> +sfence.vma a0
> +ret
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 7/7] UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode
2023-07-14 10:24 ` Sunil V L
@ 2023-07-14 19:10 ` Tuan Phan
0 siblings, 0 replies; 20+ messages in thread
From: Tuan Phan @ 2023-07-14 19:10 UTC (permalink / raw)
To: Sunil V L
Cc: devel, michael.d.kinney, gaoliming, zhiguang.liu, git,
andrei.warkentin, ardb+tianocore
[-- Attachment #1: Type: text/plain, Size: 24995 bytes --]
On Fri, Jul 14, 2023 at 3:24 AM Sunil V L <sunilvl@ventanamicro.com> wrote:
> On Fri, Jun 23, 2023 at 11:39:34AM -0700, Tuan Phan wrote:
> > During CpuDxe initialization, MMU will be setup with the highest
> > mode that HW supports.
> >
> > Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
> > Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
> > ---
> Hi Tuan,
>
> CI tests are failing for these changes primarily due to code formatting
> errors. Can you please fix them and send the next version?
>
Hi Sunil,
I sent the next version. It passed CI at this pull request:
https://github.com/tianocore/edk2/pull/4569
>
> Thanks,
> Sunil
> > OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 +
> > UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 9 +-
> > UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 2 +
> > UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf | 2 +
> > UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h | 39 ++
> > .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 569 ++++++++++++++++++
> > .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 26 +
> > .../Library/BaseRiscVMmuLib/RiscVMmuCore.S | 31 +
> > 8 files changed, 677 insertions(+), 2 deletions(-)
> > create mode 100644 UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h
> > create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> > create mode 100644
> UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> > create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S
> >
> > diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
> b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
> > index 731f54f73f81..bc204ba5fe52 100644
> > --- a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
> > +++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
> > @@ -83,6 +83,7 @@
> > # RISC-V Architectural Libraries
> >
> CpuExceptionHandlerLib|UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf
> > RiscVSbiLib|MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf
> > + RiscVMmuLib|UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> >
> PlatformBootManagerLib|OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
> >
> ResetSystemLib|OvmfPkg/RiscVVirt/Library/ResetSystemLib/BaseResetSystemLib.inf
> >
> > diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
> b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
> > index 25fe3f54c325..2af3b6223450 100644
> > --- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
> > +++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
> > @@ -296,8 +296,7 @@ CpuSetMemoryAttributes (
> > IN UINT64 Attributes
> > )
> > {
> > - DEBUG ((DEBUG_INFO, "%a: Set memory attributes not supported yet\n",
> __func__));
> > - return EFI_SUCCESS;
> > + return RiscVSetMemoryAttributes (BaseAddress, Length, Attributes);
> > }
> >
> > /**
> > @@ -340,6 +339,12 @@ InitializeCpu (
> > //
> > DisableInterrupts ();
> >
> > + //
> > + // Enable MMU
> > + //
> > + Status = RiscVConfigureMmu ();
> > + ASSERT_EFI_ERROR (Status);
> > +
> > //
> > // Install Boot protocol
> > //
> > diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
> b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
> > index 49f4e119665a..68e6d038b66e 100644
> > --- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
> > +++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
> > @@ -15,11 +15,13 @@
> > #include <Protocol/Cpu.h>
> > #include <Protocol/RiscVBootProtocol.h>
> > #include <Library/BaseRiscVSbiLib.h>
> > +#include <Library/BaseRiscVMmuLib.h>
> > #include <Library/BaseLib.h>
> > #include <Library/CpuExceptionHandlerLib.h>
> > #include <Library/DebugLib.h>
> > #include <Library/UefiBootServicesTableLib.h>
> > #include <Library/UefiDriverEntryPoint.h>
> > +#include <Register/RiscV64/RiscVEncoding.h>
> >
> > /**
> > Flush CPU data cache. If the instruction cache is fully coherent
> > diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
> b/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
> > index e8fa25446aef..6d52085df0d5 100644
> > --- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
> > +++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
> > @@ -37,6 +37,8 @@
> > TimerLib
> > PeCoffGetEntryPointLib
> > RiscVSbiLib
> > + RiscVMmuLib
> > + CacheMaintenanceLib
> >
> > [Sources]
> > CpuDxe.c
> > diff --git a/UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h
> b/UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h
> > new file mode 100644
> > index 000000000000..f71d6a4a1e7b
> > --- /dev/null
> > +++ b/UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h
> > @@ -0,0 +1,39 @@
> > +/** @file
> > +
> > + Copyright (c) 2015 - 2016, Linaro Ltd. All rights reserved.<BR>
> > + Copyright (c) 2023, Ventana Micro Systems Inc. All Rights
> Reserved.<BR>
> > +
> > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > +
> > +**/
> > +
> > +#ifndef BASE_RISCV_MMU_LIB_H_
> > +#define BASE_RISCV_MMU_LIB_H_
> > +
> > +VOID
> > +EFIAPI
> > +RiscVLocalTlbFlushAll (
> > + VOID
> > + );
> > +
> > +VOID
> > +EFIAPI
> > +RiscVLocalTlbFlush (
> > + UINTN VirtAddr
> > + );
> > +
> > +EFI_STATUS
> > +EFIAPI
> > +RiscVSetMemoryAttributes (
> > + IN EFI_PHYSICAL_ADDRESS BaseAddress,
> > + IN UINT64 Length,
> > + IN UINT64 Attributes
> > + );
> > +
> > +EFI_STATUS
> > +EFIAPI
> > +RiscVConfigureMmu (
> > + VOID
> > + );
> > +
> > +#endif /* BASE_RISCV_MMU_LIB_H_ */
> > diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> > new file mode 100644
> > index 000000000000..e6841b793bfc
> > --- /dev/null
> > +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> > @@ -0,0 +1,569 @@
> > +/** @file
> > +* MMU implementation for RISC-V
> > +*
> > +* Copyright (c) 2011-2020, ARM Limited. All rights reserved.
> > +* Copyright (c) 2016, Linaro Limited. All rights reserved.
> > +* Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> > +* Copyright (c) 2023, Ventana Micro Systems Inc. All Rights
> Reserved.<BR>
> > +*
> > +* SPDX-License-Identifier: BSD-2-Clause-Patent
> > +*
> > +**/
> > +
> > +#include <PiDxe.h>
> > +#include <Uefi.h>
> > +#include <Library/BaseLib.h>
> > +#include <Library/BaseMemoryLib.h>
> > +#include <Library/BaseRiscVMmuLib.h>
> > +#include <Library/CacheMaintenanceLib.h>
> > +#include <Library/DebugLib.h>
> > +#include <Library/DxeServicesTableLib.h>
> > +#include <Library/UefiBootServicesTableLib.h>
> > +#include <Library/MemoryAllocationLib.h>
> > +#include <Library/PcdLib.h>
> > +#include <Register/RiscV64/RiscVEncoding.h>
> > +
> > +#define RISCV_PG_V BIT0
> > +#define RISCV_PG_R BIT1
> > +#define RISCV_PG_W BIT2
> > +#define RISCV_PG_X BIT3
> > +#define RISCV_PG_G BIT5
> > +#define RISCV_PG_A BIT6
> > +#define RISCV_PG_D BIT7
> > +#define PTE_ATTRIBUTES_MASK 0xE
> > +
> > +#define PTE_PPN_MASK 0x3FFFFFFFFFFC00ULL
> > +#define PTE_PPN_SHIFT 10
> > +#define RISCV_MMU_PAGE_SHIFT 12
> > +
> > +STATIC UINTN mMaxRootTableLevel;
> > +STATIC UINTN mBitPerLevel;
> > +STATIC UINTN mTableEntryCount;
> > +
> > +STATIC
> > +BOOLEAN
> > +RiscVMmuEnabled (
> > + VOID
> > + )
> > +{
> > + return ((RiscVGetSupervisorAddressTranslationRegister () &
> > + SATP64_MODE) != (SATP_MODE_OFF << SATP64_MODE_SHIFT));
> > +}
> > +
> > +STATIC
> > +UINTN
> > +RiscVGetRootTranslateTable (
> > + VOID
> > + )
> > +{
> > + return (RiscVGetSupervisorAddressTranslationRegister () & SATP64_PPN)
> <<
> > + RISCV_MMU_PAGE_SHIFT;
> > +}
> > +
> > +STATIC
> > +BOOLEAN
> > +IsValidPte (
> > + IN UINTN Entry
> > + )
> > +{
> > + if (!(Entry & RISCV_PG_V) ||
> > + (((Entry & (RISCV_PG_R | RISCV_PG_W)) == RISCV_PG_W)))
> > + {
> > + return FALSE;
> > + }
> > +
> > + return TRUE;
> > +}
> > +
> > +STATIC
> > +UINTN
> > +SetValidPte (
> > + IN UINTN Entry
> > + )
> > +{
> > + /* Set Valid and Global mapping bits */
> > + return Entry | RISCV_PG_G | RISCV_PG_V;
> > +}
> > +
> > +STATIC
> > +BOOLEAN
> > +IsBlockEntry (
> > + IN UINTN Entry
> > + )
> > +{
> > + return IsValidPte (Entry) &&
> > + (Entry & (RISCV_PG_X | RISCV_PG_R));
> > +}
> > +
> > +STATIC
> > +BOOLEAN
> > +IsTableEntry (
> > + IN UINTN Entry
> > + )
> > +{
> > + return IsValidPte (Entry) &&
> > + !IsBlockEntry (Entry);
> > +}
> > +
> > +STATIC
> > +UINTN
> > +SetTableEntry (
> > + IN UINTN Entry
> > + )
> > +{
> > + Entry = SetValidPte (Entry);
> > + Entry &= ~(RISCV_PG_X | RISCV_PG_W | RISCV_PG_R);
> > +
> > + return Entry;
> > +}
> > +
> > +STATIC
> > +VOID
> > +ReplaceTableEntry (
> > + IN UINTN *Entry,
> > + IN UINTN Value,
> > + IN UINTN RegionStart,
> > + IN BOOLEAN IsLiveBlockMapping
> > + )
> > +{
> > + *Entry = Value;
> > +
> > + if (IsLiveBlockMapping && RiscVMmuEnabled ()) {
> > + RiscVLocalTlbFlush (RegionStart);
> > + }
> > +}
> > +
> > +STATIC
> > +UINTN
> > +GetPpnfromPte (
> > + UINTN Entry,
> > + UINTN Level
> > + )
> > +{
> > + return ((Entry & PTE_PPN_MASK) >> PTE_PPN_SHIFT);
> > +}
> > +
> > +STATIC
> > +UINTN
> > +SetPpnToPte (
> > + UINTN Entry,
> > + UINTN Address,
> > + UINTN Level
> > + )
> > +{
> > + UINTN Ppn;
> > +
> > + Ppn = ((Address >> RISCV_MMU_PAGE_SHIFT) << PTE_PPN_SHIFT);
> > + ASSERT (~(Ppn & ~PTE_PPN_MASK));
> > + Entry &= ~PTE_PPN_MASK;
> > + return Entry | Ppn;
> > +}
> > +
> > +STATIC
> > +VOID
> > +FreePageTablesRecursive (
> > + IN UINTN *TranslationTable,
> > + IN UINTN Level
> > + )
> > +{
> > + UINTN Index;
> > +
> > + if (Level < mMaxRootTableLevel - 1) {
> > + for (Index = 0; Index < mTableEntryCount; Index++) {
> > + if (IsTableEntry (TranslationTable[Index])) {
> > + FreePageTablesRecursive (
> > + (UINTN *)(GetPpnfromPte ((TranslationTable[Index]), Level) <<
> > + RISCV_MMU_PAGE_SHIFT),
> > + Level + 1
> > + );
> > + }
> > + }
> > + }
> > +
> > + FreePages (TranslationTable, 1);
> > +}
> > +
> > +STATIC
> > +EFI_STATUS
> > +UpdateRegionMappingRecursive (
> > + IN UINTN RegionStart,
> > + IN UINTN RegionEnd,
> > + IN UINTN AttributeSetMask,
> > + IN UINTN AttributeClearMask,
> > + IN UINTN *PageTable,
> > + IN UINTN Level,
> > + IN BOOLEAN TableIsLive
> > + )
> > +{
> > + EFI_STATUS Status;
> > + UINTN BlockShift;
> > + UINTN BlockMask;
> > + UINTN BlockEnd;
> > + UINTN *Entry;
> > + UINTN EntryValue;
> > + UINTN *TranslationTable;
> > + BOOLEAN NextTableIsLive;
> > +
> > + ASSERT (Level < mMaxRootTableLevel);
> > + ASSERT (((RegionStart | RegionEnd) & EFI_PAGE_MASK) == 0);
> > +
> > + BlockShift = (mMaxRootTableLevel - Level - 1) * mBitPerLevel +
> RISCV_MMU_PAGE_SHIFT;
> > + BlockMask = MAX_ADDRESS >> (64 - BlockShift);
> > +
> > + DEBUG (
> > + (
> > + DEBUG_VERBOSE,
> > + "%a(%d): %llx - %llx set %lx clr %lx\n",
> > + __func__,
> > + Level,
> > + RegionStart,
> > + RegionEnd,
> > + AttributeSetMask,
> > + AttributeClearMask
> > + )
> > + );
> > +
> > + for ( ; RegionStart < RegionEnd; RegionStart = BlockEnd) {
> > + BlockEnd = MIN (RegionEnd, (RegionStart | BlockMask) + 1);
> > + Entry = &PageTable[(RegionStart >> BlockShift) &
> (mTableEntryCount - 1)];
> > +
> > + //
> > + // If RegionStart or BlockEnd is not aligned to the block size at
> this
> > + // level, we will have to create a table mapping in order to map
> less
> > + // than a block, and recurse to create the block or page entries at
> > + // the next level. No block mappings are allowed at all at level 0,
> > + // so in that case, we have to recurse unconditionally.
> > + //
> > + if ((Level == 0) ||
> > + (((RegionStart | BlockEnd) & BlockMask) != 0) || IsTableEntry
> (*Entry))
> > + {
> > + ASSERT (Level < mMaxRootTableLevel - 1);
> > + if (!IsTableEntry (*Entry)) {
> > + //
> > + // No table entry exists yet, so we need to allocate a page
> table
> > + // for the next level.
> > + //
> > + TranslationTable = AllocatePages (1);
> > + if (TranslationTable == NULL) {
> > + return EFI_OUT_OF_RESOURCES;
> > + }
> > +
> > + ZeroMem (TranslationTable, EFI_PAGE_SIZE);
> > +
> > + if (IsBlockEntry (*Entry)) {
> > + //
> > + // We are splitting an existing block entry, so we have to
> populate
> > + // the new table with the attributes of the block entry it
> replaces.
> > + //
> > + Status = UpdateRegionMappingRecursive (
> > + RegionStart & ~BlockMask,
> > + (RegionStart | BlockMask) + 1,
> > + *Entry & PTE_ATTRIBUTES_MASK,
> > + PTE_ATTRIBUTES_MASK,
> > + TranslationTable,
> > + Level + 1,
> > + FALSE
> > + );
> > + if (EFI_ERROR (Status)) {
> > + //
> > + // The range we passed to UpdateRegionMappingRecursive ()
> is block
> > + // aligned, so it is guaranteed that no further pages were
> allocated
> > + // by it, and so we only have to free the page we allocated
> here.
> > + //
> > + FreePages (TranslationTable, 1);
> > + return Status;
> > + }
> > + }
> > +
> > + NextTableIsLive = FALSE;
> > + } else {
> > + TranslationTable = (UINTN *)(GetPpnfromPte (*Entry, Level) <<
> RISCV_MMU_PAGE_SHIFT);
> > + NextTableIsLive = TableIsLive;
> > + }
> > +
> > + //
> > + // Recurse to the next level
> > + //
> > + Status = UpdateRegionMappingRecursive (
> > + RegionStart,
> > + BlockEnd,
> > + AttributeSetMask,
> > + AttributeClearMask,
> > + TranslationTable,
> > + Level + 1,
> > + NextTableIsLive
> > + );
> > + if (EFI_ERROR (Status)) {
> > + if (!IsTableEntry (*Entry)) {
> > + //
> > + // We are creating a new table entry, so on failure, we can
> free all
> > + // allocations we made recursively, given that the whole
> subhierarchy
> > + // has not been wired into the live page tables yet. (This is
> not
> > + // possible for existing table entries, since we cannot
> revert the
> > + // modifications we made to the subhierarchy it represents.)
> > + //
> > + FreePageTablesRecursive (TranslationTable, Level + 1);
> > + }
> > +
> > + return Status;
> > + }
> > +
> > + if (!IsTableEntry (*Entry)) {
> > + EntryValue = SetPpnToPte (0, (UINTN)TranslationTable, Level);
> > + EntryValue = SetTableEntry (EntryValue);
> > + ReplaceTableEntry (
> > + Entry,
> > + EntryValue,
> > + RegionStart,
> > + TableIsLive
> > + );
> > + }
> > + } else {
> > + EntryValue = (*Entry & ~AttributeClearMask) | AttributeSetMask;
> > + //
> > + // We don't have page fault exception handler when a virtual page
> is accessed and
> > + // the A bit is clear, or is written and the D bit is clear.
> > + // So just set A for read and D for write permission.
> > + //
> > + if (AttributeSetMask & RISCV_PG_R) {
> > + EntryValue |= RISCV_PG_A;
> > + }
> > +
> > + if (AttributeSetMask & RISCV_PG_W) {
> > + EntryValue |= RISCV_PG_D;
> > + }
> > +
> > + EntryValue = SetPpnToPte (EntryValue, RegionStart, Level);
> > + EntryValue = SetValidPte (EntryValue);
> > + ReplaceTableEntry (Entry, EntryValue, RegionStart, TableIsLive);
> > + }
> > + }
> > +
> > + return EFI_SUCCESS;
> > +}
> > +
> > +STATIC
> > +EFI_STATUS
> > +UpdateRegionMapping (
> > + IN UINTN RegionStart,
> > + IN UINTN RegionLength,
> > + IN UINTN AttributeSetMask,
> > + IN UINTN AttributeClearMask,
> > + IN UINTN *RootTable,
> > + IN BOOLEAN TableIsLive
> > + )
> > +{
> > + if (((RegionStart | RegionLength) & EFI_PAGE_MASK) != 0) {
> > + return EFI_INVALID_PARAMETER;
> > + }
> > +
> > + return UpdateRegionMappingRecursive (
> > + RegionStart,
> > + RegionStart + RegionLength,
> > + AttributeSetMask,
> > + AttributeClearMask,
> > + RootTable,
> > + 0,
> > + TableIsLive
> > + );
> > +}
> > +
> > +STATIC
> > +UINTN
> > +GcdAttributeToPageAttribute (
> > + IN UINTN GcdAttributes
> > + )
> > +{
> > + UINTN RiscVAttributes = RISCV_PG_R | RISCV_PG_W | RISCV_PG_X;
> > +
> > + // Determine protection attributes
> > + if (GcdAttributes & EFI_MEMORY_RO) {
> > + RiscVAttributes &= ~(RISCV_PG_W);
> > + }
> > +
> > + // Process eXecute Never attribute
> > + if (GcdAttributes & EFI_MEMORY_XP) {
> > + RiscVAttributes &= ~RISCV_PG_X;
> > + }
> > +
> > + return RiscVAttributes;
> > +}
> > +
> > +EFI_STATUS
> > +EFIAPI
> > +RiscVSetMemoryAttributes (
> > + IN EFI_PHYSICAL_ADDRESS BaseAddress,
> > + IN UINTN Length,
> > + IN UINTN Attributes
> > + )
> > +{
> > + UINTN PageAttributesSet = GcdAttributeToPageAttribute (Attributes);
> > +
> > + if (!RiscVMmuEnabled ()) {
> > + return EFI_SUCCESS;
> > + }
> > +
> > + DEBUG (
> > + (
> > + DEBUG_VERBOSE,
> > + "%a: Set %llX page attribute 0x%X\n",
> > + __func__,
> > + BaseAddress,
> > + PageAttributesSet
> > + )
> > + );
> > +
> > + return UpdateRegionMapping (
> > + BaseAddress,
> > + Length,
> > + PageAttributesSet,
> > + PTE_ATTRIBUTES_MASK,
> > + (UINTN *)RiscVGetRootTranslateTable (),
> > + TRUE
> > + );
> > +}
> > +
> > +STATIC
> > +EFI_STATUS
> > +RiscVMmuSetSatpMode (
> > + UINTN SatpMode
> > + )
> > +{
> > + VOID *TranslationTable;
> > + UINTN SatpReg;
> > + UINTN Ppn;
> > + EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemoryMap;
> > + UINTN NumberOfDescriptors;
> > + UINTN Index;
> > + EFI_STATUS Status;
> > +
> > + switch (SatpMode) {
> > + case SATP_MODE_OFF:
> > + return EFI_SUCCESS;
> > + case SATP_MODE_SV39:
> > + mMaxRootTableLevel = 3;
> > + mBitPerLevel = 9;
> > + mTableEntryCount = 512;
> > + break;
> > + case SATP_MODE_SV48:
> > + mMaxRootTableLevel = 4;
> > + mBitPerLevel = 9;
> > + mTableEntryCount = 512;
> > + break;
> > + case SATP_MODE_SV57:
> > + mMaxRootTableLevel = 5;
> > + mBitPerLevel = 9;
> > + mTableEntryCount = 512;
> > + break;
> > + default:
> > + return EFI_INVALID_PARAMETER;
> > + }
> > +
> > + // Allocate pages for translation table
> > + TranslationTable = AllocatePages (1);
> > + if (TranslationTable == NULL) {
> > + return EFI_OUT_OF_RESOURCES;
> > + }
> > +
> > + ZeroMem (TranslationTable, mTableEntryCount * sizeof (UINTN));
> > +
> > + NumberOfDescriptors = 0;
> > + MemoryMap = NULL;
> > + Status = gDS->GetMemorySpaceMap (
> > + &NumberOfDescriptors,
> > + &MemoryMap
> > + );
> > + ASSERT_EFI_ERROR (Status);
> > +
> > + for (Index = 0; Index < NumberOfDescriptors; Index++) {
> > + if (MemoryMap[Index].GcdMemoryType ==
> EfiGcdMemoryTypeMemoryMappedIo) {
> > + // Default Read/Write attribute for memory mapped IO
> > + UpdateRegionMapping (
> > + MemoryMap[Index].BaseAddress,
> > + MemoryMap[Index].Length,
> > + RISCV_PG_R | RISCV_PG_W,
> > + PTE_ATTRIBUTES_MASK,
> > + TranslationTable,
> > + FALSE
> > + );
> > + } else if (MemoryMap[Index].GcdMemoryType ==
> EfiGcdMemoryTypeSystemMemory) {
> > + // Default Read/Write/Execute attribute for system memory
> > + UpdateRegionMapping (
> > + MemoryMap[Index].BaseAddress,
> > + MemoryMap[Index].Length,
> > + RISCV_PG_R | RISCV_PG_W | RISCV_PG_X,
> > + PTE_ATTRIBUTES_MASK,
> > + TranslationTable,
> > + FALSE
> > + );
> > + }
> > + }
> > +
> > + FreePool ((VOID *)MemoryMap);
> > +
> > + if (GetInterruptState ()) {
> > + DisableInterrupts ();
> > + }
> > +
> > + Ppn = (UINTN)TranslationTable >> RISCV_MMU_PAGE_SHIFT;
> > + ASSERT (!(Ppn & ~(SATP64_PPN)));
> > +
> > + SatpReg = Ppn;
> > + SatpReg |= (SatpMode <<
> > + SATP64_MODE_SHIFT) & SATP64_MODE;
> > + RiscVSetSupervisorAddressTranslationRegister (SatpReg);
> > + /* Check if HW support the setup satp mode */
> > + if (SatpReg != RiscVGetSupervisorAddressTranslationRegister ()) {
> > + DEBUG (
> > + (
> > + DEBUG_VERBOSE,
> > + "%a: HW does not support SATP mode:%d\n",
> > + __func__,
> > + SatpMode
> > + )
> > + );
> > + FreePageTablesRecursive (TranslationTable, 0);
> > + return EFI_DEVICE_ERROR;
> > + }
> > +
> > + RiscVLocalTlbFlushAll ();
> > +
> > + if (GetInterruptState ()) {
> > + EnableInterrupts ();
> > + }
> > +
> > + return Status;
> > +}
> > +
> > +EFI_STATUS
> > +EFIAPI
> > +RiscVConfigureMmu (
> > + VOID
> > + )
> > +{
> > + EFI_STATUS Status = EFI_SUCCESS;
> > + INTN ModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48,
> SATP_MODE_SV39 };
> > + INTN Idx;
> > +
> > + /* Try to setup MMU with highest mode as possible */
> > + for (Idx = 0; Idx < ARRAY_SIZE (ModeSupport); Idx++) {
> > + Status = RiscVMmuSetSatpMode (ModeSupport[Idx]);
> > + if (Status == EFI_DEVICE_ERROR) {
> > + continue;
> > + } else if (EFI_ERROR (Status)) {
> > + return Status;
> > + }
> > +
> > + DEBUG (
> > + (
> > + DEBUG_INFO,
> > + "%a: SATP mode %d successfully configured\n",
> > + __func__,
> > + ModeSupport[Idx]
> > + )
> > + );
> > + break;
> > + }
> > +
> > + return Status;
> > +}
> > diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> > new file mode 100644
> > index 000000000000..2819c871b2a2
> > --- /dev/null
> > +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> > @@ -0,0 +1,26 @@
> > +## @file
> > +#
> > +# Copyright (c) 2023, Ventana Micro Systems Inc. All Rights
> Reserved.<BR>
> > +#
> > +# SPDX-License-Identifier: BSD-2-Clause-Patent
> > +#
> > +##
> > +
> > +[Defines]
> > + INF_VERSION = 0x0001001b
> > + BASE_NAME = BaseRiscVMmuLib
> > + FILE_GUID = d3bc42ee-c9eb-4339-ba11-06747083d3ae
> > + MODULE_TYPE = BASE
> > + VERSION_STRING = 1.0
> > + LIBRARY_CLASS = RiscVMmuLib
> > +
> > +[Sources]
> > + BaseRiscVMmuLib.c
> > + RiscVMmuCore.S
> > +
> > +[Packages]
> > + MdePkg/MdePkg.dec
> > + UefiCpuPkg/UefiCpuPkg.dec
> > +
> > +[LibraryClasses]
> > + BaseLib
> > diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S
> b/UefiCpuPkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S
> > new file mode 100644
> > index 000000000000..42eec4cbdf83
> > --- /dev/null
> > +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S
> > @@ -0,0 +1,31 @@
> > +/** @file
> > +*
> > +* Copyright (c) 2023, Ventana Micro Systems Inc. All Rights
> Reserved.<BR>
> > +*
> > +* SPDX-License-Identifier: BSD-2-Clause-Patent
> > +*
> > +**/
> > +
> > +#include <Base.h>
> > +#include <Register/RiscV64/RiscVImpl.h>
> > +
> > +.text
> > + .align 3
> > +
> > +//
> > +// Local tlb flush all.
> > +//
> > +//
> > +ASM_FUNC (RiscVLocalTlbFlushAll)
> > +sfence.vma
> > +ret
> > +
> > +//
> > +// Local tlb flush at a virtual address
> > +// @retval a0 : virtual address.
> > +//
> > +ASM_FUNC (
> > + RiscVLocalTlbFlush
> > + )
> > +sfence.vma a0
> > +ret
> > --
> > 2.25.1
> >
>
[-- Attachment #2: Type: text/html, Size: 31691 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 0/7] RISC-V: Add MMU support
2023-06-23 18:39 [PATCH v4 0/7] RISC-V: Add MMU support Tuan Phan
` (7 preceding siblings ...)
2023-06-25 8:45 ` [edk2-devel] UsbNetworkPkg not find in UDK 202305 stable version Yoshinoya
@ 2023-07-15 5:21 ` Sunil V L
8 siblings, 0 replies; 20+ messages in thread
From: Sunil V L @ 2023-07-15 5:21 UTC (permalink / raw)
To: Tuan Phan
Cc: devel, michael.d.kinney, gaoliming, zhiguang.liu, git,
andrei.warkentin, ardb+tianocore
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
On Fri, Jun 23, 2023 at 11:39:27AM -0700, Tuan Phan wrote:
> This series adds MMU support for RISC-V. Only SV39/48/57 modes
> are supported and tested. The MMU is required to support setting
> page attribute which is the first basic step to support security
> booting on RISC-V.
>
> There are two parts:
> 1. Add MMU base library. MMU will be enabled during
> CpuDxe initialization.
> 2. Fix all resources should be populated in HOB
> or added to GCD by driver before accessing when MMU enabled.
>
> All changes can be found in the branch tphan/riscv_mmu at:
> https://github.com/pttuan/edk2.git
>
> Changes in v4:
> - Rebased master.
> - Added VirtNorFlashDxe to APRIORI DXE list.
>
> Changes in v3:
> - Move MMU library to UefiCpuPkg.
> - Add Andrei reviewed-by.
>
> Changes in v2:
> - Move MMU core to a library.
> - Setup SATP mode as highest possible that HW supports.
>
> Tuan Phan (7):
> MdePkg/BaseLib: RISC-V: Support getting satp register value
> MdePkg/Register: RISC-V: Add satp mode bits shift definition
> OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size
> OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform
> devices
> OvmfPkg/RiscVVirt: Add VirtNorFlashDxe to APRIORI list
> OvmfPkg: RiscVVirt: Remove satp bare mode setting
> UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode
>
> MdePkg/Include/Library/BaseLib.h | 5 +
> .../Include/Register/RiscV64/RiscVEncoding.h | 7 +-
> MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8 +
> .../VirtNorFlashStaticLib.c | 3 +-
> OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 +
> OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 10 +
> OvmfPkg/RiscVVirt/Sec/Memory.c | 18 +-
> OvmfPkg/RiscVVirt/Sec/Platform.c | 62 ++
> UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 9 +-
> UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 2 +
> UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf | 2 +
> UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h | 39 ++
> .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 569 ++++++++++++++++++
> .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 26 +
> .../Library/BaseRiscVMmuLib/RiscVMmuCore.S | 31 +
> 15 files changed, 770 insertions(+), 22 deletions(-)
> create mode 100644 UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h
> create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S
>
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2023-07-15 5:21 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-06-23 18:39 [PATCH v4 0/7] RISC-V: Add MMU support Tuan Phan
2023-06-23 18:39 ` [PATCH v4 1/7] MdePkg/BaseLib: RISC-V: Support getting satp register value Tuan Phan
2023-06-23 18:39 ` [PATCH v4 2/7] MdePkg/Register: RISC-V: Add satp mode bits shift definition Tuan Phan
2023-06-27 20:10 ` Michael D Kinney
2023-06-23 18:39 ` [PATCH v4 3/7] OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size Tuan Phan
2023-06-23 18:39 ` [PATCH v4 4/7] OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform devices Tuan Phan
2023-06-23 18:39 ` [PATCH v4 5/7] OvmfPkg/RiscVVirt: Add VirtNorFlashDxe to APRIORI list Tuan Phan
2023-06-28 16:47 ` Sunil V L
2023-06-28 21:27 ` Tuan Phan
2023-07-04 5:07 ` Sunil V L
2023-07-04 6:45 ` Tuan Phan
2023-07-04 7:01 ` Sunil V L
2023-07-13 19:08 ` Tuan Phan
2023-07-14 4:19 ` Sunil V L
2023-06-23 18:39 ` [PATCH v4 6/7] OvmfPkg: RiscVVirt: Remove satp bare mode setting Tuan Phan
2023-06-23 18:39 ` [PATCH v4 7/7] UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode Tuan Phan
2023-07-14 10:24 ` Sunil V L
2023-07-14 19:10 ` Tuan Phan
2023-06-25 8:45 ` [edk2-devel] UsbNetworkPkg not find in UDK 202305 stable version Yoshinoya
2023-07-15 5:21 ` [PATCH v4 0/7] RISC-V: Add MMU support Sunil V L
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