From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-ed1-f47.google.com (mail-ed1-f47.google.com [209.85.208.47]) by mx.groups.io with SMTP id smtpd.web10.33177.1678486838031541312 for ; Fri, 10 Mar 2023 14:20:38 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=N3L1kDkV; spf=pass (domain: ventanamicro.com, ip: 209.85.208.47, mailfrom: tphan@ventanamicro.com) Received: by mail-ed1-f47.google.com with SMTP id cw28so26429949edb.5 for ; Fri, 10 Mar 2023 14:20:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678486836; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=9ttmLg1ogkVgirizFm0X9j5f2bH4gKzocfrXSroFSzA=; b=N3L1kDkVluFHHwOYrOprarWxNgEQ8TQ56qjA7bvRP8uDU0HgYtgnSIrOp5TuRn8iEQ thdSNEc/ReG14b1J0LAzxRRAI0IbiCyQdOiCH9xFrjIX2AbvDOsA5QwqyYcOpJZ7VBPA gwtN4BLfRzzL5SzyXCAsCGJUcKXLj6fSOC1i1gA9PTTTWhMTsVM3kwA1bfoGcyynB7J4 fCo5erGJAh511poHF0HlZeeukrzW5iSPoj/RAJ8bGxVlOvEaUfmAJcTbLj+3tCTyQOnu ZHArmwNWHrXyfZT4VXm2Kgr7vOUbyJDLP7nVZwN/0sHtPUQTE4XQAPdYUyDFPx7YD3XG jvTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678486836; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=9ttmLg1ogkVgirizFm0X9j5f2bH4gKzocfrXSroFSzA=; b=rHTMEpEa79ejEvt/h5uFxEQWYDJdE3fFZwIPpHE/2dJnUY5D7mF9PWYlM85MDEhUYb jByQd4/rlW1w9SXUx3jYB2EfN+HIPp9pQEFnx7de0cYJL7NjqZvAkb3SD0t+3xJBnocg nS7mKVoPS1bxMGrK4ukekWV5VYdFmb7QARqrwTDP03ipeNSFdkU/ug47F0M/mxK6sxtz LF6aQl22/MBcp24KHkHGUCyrydCcKsYBWtXyXIiUpAi4jpYWUOmMCbxcJuuNeO9vyace dlImh35WYUZ8iSwAAwvBco/NwqsuXxRUtN3pt6xNDa7hrPJJakLe4Zon270+KpYbUuOc L7YQ== X-Gm-Message-State: AO0yUKVVyCi/OeyFa1t7339gYFRUM3FKYgqUenWPMtEfxs5WBWe/nmdg OTqSpZCjTqv4qbGWXIUiKIrnRVpFywhwybdM7FLYrA== X-Google-Smtp-Source: AK7set9pae79PSGVuzjmE/tX16QsL+zFd/ZK1nIZBgel1BizTEqXqf1GqttiAXjxOWeWWCzfo5aoZKE6O/tpF6x3Gqc= X-Received: by 2002:a50:d08d:0:b0:4bf:5fd5:da3f with SMTP id v13-20020a50d08d000000b004bf5fd5da3fmr15022393edd.3.1678486836461; Fri, 10 Mar 2023 14:20:36 -0800 (PST) MIME-Version: 1.0 References: <20230306173316.10319-1-tphan@ventanamicro.com> <444581EE-FCBD-48F0-A75E-BDDE4D9BE57A@hxcore.ol> In-Reply-To: From: "Tuan Phan" Date: Fri, 10 Mar 2023 14:20:25 -0800 Message-ID: Subject: Re: [PATCH 0/7] RISC-V: Add MMU support To: "Warkentin, Andrei" Cc: "devel@edk2.groups.io" , "Kinney, Michael D" , "Gao, Liming" , "Liu, Zhiguang" , "sunilvl@ventanamicro.com" , "git@danielschaefer.me" Content-Type: multipart/alternative; boundary="000000000000a5d47a05f6932b48" --000000000000a5d47a05f6932b48 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Andrei, Here it is: https://github.com/pttuan/edk2/tree/tphan/riscv_mmu On Thu, Mar 9, 2023 at 1:34=E2=80=AFPM Warkentin, Andrei wrote: > Hi Tuan, > > > > Could you share a GitHub link to a branch with the patch set? Somehow my > email client is mangling one of your patches where it=E2=80=99s all one g= iant line > of code. > > > > A > > > > *From:* Tuan Phan > *Sent:* Thursday, March 9, 2023 1:20 PM > *To:* devel@edk2.groups.io > *Cc:* Kinney, Michael D ; Gao, Liming < > gaoliming@byosoft.com.cn>; Liu, Zhiguang ; > sunilvl@ventanamicro.com; git@danielschaefer.me; Warkentin, Andrei < > andrei.warkentin@intel.com> > *Subject:* RE: [PATCH 0/7] RISC-V: Add MMU support > > > > Hi All, > > Any updates on this series? > > > > Thanks, > > > > *From: *Tuan Phan > *Sent: *Monday, March 6, 2023 9:33 AM > *To: *devel@edk2.groups.io > *Cc: *michael.d.kinney@intel.com; gaoliming@byosoft.com.cn; > zhiguang.liu@intel.com; sunilvl@ventanamicro.com; git@danielschaefer.me; > andrei.warkentin@intel.com; Tuan Phan > *Subject: *[PATCH 0/7] RISC-V: Add MMU support > > > > This series adds MMU support for RISC-V. Only SV39/48/57 modes > > are supported and tested. The MMU is required to support setting > > page attribute which is the first basic step to support security > > booting on RISC-V. > > > > There are three parts: > > 1. Add MMU core to UefiCpuPkg. MMU will be enabled during > > CpuDxe initialization. > > 2. Fix OvmfPkg/VirtNorFlashDxe that failed to add flash base > > address to GCD if already done. > > 3. Enable MMU for RiscVVirt platform and populating its device > > resources in SEC phase. All resources should be populated in HOB > > or added to GCD by driver before accessing them when MMU enabled. > > > > Tuan Phan (7): > > MdePkg/BaseLib: RISC-V: Support getting satp register value > > MdePkg/Register: RISC-V: Add satp mode bits shift definition > > UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode > > OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size > > OvmfPkg/VirtNorFlashDxe: Not add memory space if it exists > > OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform > > devices > > OvmfPkg/RiscVVirt: Enable MMU with SV39 mode > > > > MdePkg/Include/Library/BaseLib.h | 5 + > > .../Include/Register/RiscV64/RiscVEncoding.h | 7 +- > > MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8 + > > .../VirtNorFlashStaticLib.c | 3 +- > > OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 + > > OvmfPkg/RiscVVirt/Sec/Memory.c | 17 - > > OvmfPkg/RiscVVirt/Sec/Platform.c | 62 +++ > > OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 + > > OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c | 25 +- > > UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 10 +- > > UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 1 + > > UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf | 5 + > > UefiCpuPkg/CpuDxeRiscV64/Mmu.c | 493 ++++++++++++++++++ > > UefiCpuPkg/CpuDxeRiscV64/Mmu.h | 33 ++ > > UefiCpuPkg/CpuDxeRiscV64/MmuCore.S | 29 ++ > > UefiCpuPkg/UefiCpuPkg.dec | 8 + > > 16 files changed, 676 insertions(+), 32 deletions(-) > > create mode 100644 UefiCpuPkg/CpuDxeRiscV64/Mmu.c > > create mode 100644 UefiCpuPkg/CpuDxeRiscV64/Mmu.h > > create mode 100644 UefiCpuPkg/CpuDxeRiscV64/MmuCore.S > > > > -- > > 2.25.1 > > > > > --000000000000a5d47a05f6932b48 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
On Thu, Mar 9, 2023 at 1:34=E2=80=AFPM Warken= tin, Andrei <andrei.warken= tin@intel.com> wrote:

Hi Tuan,

=C2=A0

Could you share a GitHub link to a branch with the p= atch set? Somehow my email client is mangling one of your patches where it= =E2=80=99s all one giant line of code.

=C2=A0

A

=C2=A0

From: Tuan Phan <tphan@ventanamicro.com>
Sent: Thursday, March 9, 2023 1:20 PM
To: devel@= edk2.groups.io
Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming <<= a href=3D"mailto:gaoliming@byosoft.com.cn" target=3D"_blank">gaoliming@byos= oft.com.cn>; Liu, Zhiguang <zhiguang.liu@intel.com>; sunilvl@ventanamicro.com; git@danielschaefer.= me; Warkentin, Andrei <andrei.warkentin@intel.com>
Subject: RE: [PATCH 0/7] RISC-V: Add MMU support

=C2=A0

Hi All,

Any updates on this series?

=C2=A0

Thanks,

=C2=A0

=C2=A0

This series adds MMU support for RISC-V. Only SV39/4= 8/57 modes

are supported and tested. The MMU is required to sup= port setting

page attribute which is the first basic step to supp= ort security

booting on RISC-V.

=C2=A0

There are three parts:

1. Add MMU core to UefiCpuPkg. MMU will be enabled d= uring

CpuDxe initialization.

2. Fix OvmfPkg/VirtNorFlashDxe that failed to add fl= ash base

address to GCD if already done.

3. Enable MMU for RiscVVirt platform and populating = its device

resources in SEC phase. All resources should be popu= lated in HOB

or added to GCD by driver before accessing them when= MMU enabled.

=C2=A0

Tuan Phan (7):

=C2=A0 MdePkg/BaseLib: RISC-V: Support getting satp = register value

=C2=A0 MdePkg/Register: RISC-V: Add satp mode bits s= hift definition

=C2=A0 UefiCpuPkg: RISC-V: Support MMU with SV39/48/= 57 mode

=C2=A0 OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: F= ix wrong flash size

=C2=A0 OvmfPkg/VirtNorFlashDxe: Not add memory space= if it exists

=C2=A0 OvmfPkg/RiscVVirt: SEC: Add IO memory resourc= e hob for platform

=C2=A0=C2=A0=C2=A0 devices

=C2=A0 OvmfPkg/RiscVVirt: Enable MMU with SV39 mode<= u>

=C2=A0

MdePkg/Include/Library/BaseLib.h=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 = 5 +

.../Include/Register/RiscV64/RiscVEncoding.h=C2=A0 |= =C2=A0=C2=A0 7 +-

MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S=C2=A0=C2= =A0=C2=A0=C2=A0 |=C2=A0=C2=A0 8 +

.../VirtNorFlashStaticLib.c=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 |=C2=A0=C2=A0 3 +-

OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 1 +

OvmfPkg/RiscVVirt/Sec/Memory.c=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2= =A0 17 -

OvmfPkg/RiscVVirt/Sec/Platform.c=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 62 +++=

OvmfPkg/RiscVVirt/Sec/SecMain.inf=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 1 +=

OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c=C2=A0=C2= =A0=C2=A0=C2=A0 |=C2=A0 25 +-

UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 10 +-=

UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 1 +=

UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf=C2=A0=C2= =A0=C2=A0 |=C2=A0=C2=A0 5 +

UefiCpuPkg/CpuDxeRiscV64/Mmu.c=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | 493= ++++++++++++++++++

UefiCpuPkg/CpuDxeRiscV64/Mmu.h=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2= =A0 33 ++

UefiCpuPkg/CpuDxeRiscV64/MmuCore.S=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 29 ++

UefiCpuPkg/UefiCpuPkg.dec=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 8 +

16 files changed, 676 insertions(+), 32 deletions(-)=

create mode 100644 UefiCpuPkg/CpuDxeRiscV64/Mmu.c=

create mode 100644 UefiCpuPkg/CpuDxeRiscV64/Mmu.h=

create mode 100644 UefiCpuPkg/CpuDxeRiscV64/MmuCore.= S

=C2=A0

--

2.25.1

=C2=A0

=C2=A0

--000000000000a5d47a05f6932b48--