From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id A06AC740034 for ; Wed, 28 Feb 2024 17:23:06 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=Kj8pUh5k6wfAk4jW8UnZYTMAq6w62v81V64SzYjO7Mo=; c=relaxed/simple; d=groups.io; h=MIME-Version:References:In-Reply-To:From:Date:Message-ID:Subject:To:Cc:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type; s=20140610; t=1709140985; v=1; b=tBZOXuQZQ4JUyElqTBxjPyWhJOCv83hNZmJnDmtwbo+nqeHgfZBmUPw73uRGracvsjGwWBXn NB9Vgsp69abKVsj3XHxiULr45hbEt7kuUDNJxRkui63EcorPUm0Q5Q05TISkboWwQrO3+SJK9eY 5nKe3Qmjbyj+v9n9SjnV1cUQ= X-Received: by 127.0.0.2 with SMTP id MNoXYY7687511xDzLvRavYTh; Wed, 28 Feb 2024 09:23:05 -0800 X-Received: from mail-vs1-f41.google.com (mail-vs1-f41.google.com [209.85.217.41]) by mx.groups.io with SMTP id smtpd.web10.2733.1709140984317822871 for ; Wed, 28 Feb 2024 09:23:04 -0800 X-Received: by mail-vs1-f41.google.com with SMTP id ada2fe7eead31-47260f17741so633033137.0 for ; Wed, 28 Feb 2024 09:23:04 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCUB/oJhjrHBpRyZPZP1yX51fPiFfpPmxZZ3y5zaUGAhc2SCi9pLldGrF4OtxWJCz85SO8LN9kt85WW0IZj6+nTdhz6veA== X-Gm-Message-State: u4z9Aiu5wjsDXR6QsxPxxv4rx7686176AA= X-Google-Smtp-Source: AGHT+IH2TX6SNoweSZu2LTRyKP2+wFnpBEJez0uv58ICySjAEeM7B8sTkceUkgfPkMCma5k1My4NEeZ8+i8RjACXuB8= X-Received: by 2002:a05:6102:38cf:b0:470:62cc:6306 with SMTP id k15-20020a05610238cf00b0047062cc6306mr53910vst.6.1709140983278; Wed, 28 Feb 2024 09:23:03 -0800 (PST) MIME-Version: 1.0 References: <20240207012910.2133-1-tphan@ventanamicro.com> <17B3F4C51A165C5A.28807@groups.io> In-Reply-To: From: "Tuan Phan" Date: Wed, 28 Feb 2024 09:22:52 -0800 Message-ID: Subject: Re: [edk2-devel] [PATCH v2 0/3] RISC-V: Support Svpbmt extension To: Sunil V L Cc: "Warkentin, Andrei" , "devel@edk2.groups.io" , "Kinney, Michael D" , "gaoliming@byosoft.com.cn" , "Liu, Zhiguang" , "kraxel@redhat.com" , "lersek@redhat.com" , "Kumar, Rahul R" , "Ni, Ray" , "Yao, Jiewen" , "ardb+tianocore@kernel.org" Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,tphan@ventanamicro.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Type: multipart/alternative; boundary="0000000000002e0a350612746543" X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=tBZOXuQZ; dmarc=none; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io --0000000000002e0a350612746543 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, Feb 27, 2024 at 8:42=E2=80=AFPM Sunil V L wrote: > Hi Tuan, > > On Mon, Feb 26, 2024 at 08:34:22PM -0800, Tuan Phan wrote: > > Hi Sunil/ Andrei, > > Any comments on this series? > > > Did I miss your response to Laszlo's feedback on PATCH 2 - [1]? Apart > from that, don't we need to handle EFI_MEMORY_WT similar to > EFI_MEMORY_WC? > > Somehow I missed that feedback. Thanks. About EFI_MEMORY_WT, ARM treats it as EFI_MEMORY_WC under hood but I don't see RISC-V specs mentions it explicitly so don't feel confident to add that. > [1] - https://edk2.groups.io/g/devel/message/115243 > > Thanks, > Sunil > > Regards, > > > > On Wed, Feb 14, 2024 at 10:16=E2=80=AFPM Tuan Phan via groups.io > ventanamicro.com@groups.io> wrote: > > > > > > > > > > > On Wed, Feb 14, 2024 at 9:43=E2=80=AFPM Warkentin, Andrei < > > > andrei.warkentin@intel.com> wrote: > > > > > >> Do you mind sharing a GH branch with the patch set? > > >> > > > https://github.com/pttuan/edk2/tree/tphan/riscv_mmu_svpbmt > > > Tuan > > > > > >> > > >> A > > >> > > >> > -----Original Message----- > > >> > From: Tuan Phan > > >> > Sent: Tuesday, February 6, 2024 7:29 PM > > >> > To: devel@edk2.groups.io > > >> > Cc: Kinney, Michael D ; > > >> > gaoliming@byosoft.com.cn; Liu, Zhiguang ; > > >> > kraxel@redhat.com; lersek@redhat.com; Kumar, Rahul R > > >> > ; Ni, Ray ; > > >> > sunilvl@ventanamicro.com; Yao, Jiewen ; > > >> Warkentin, > > >> > Andrei ; ardb+tianocore@kernel.org; > Tuan > > >> Phan > > >> > > > >> > Subject: [PATCH v2 0/3] RISC-V: Support Svpbmt extension > > >> > > > >> > This patchset adds support for RISC-V Svpbmt extension. > > >> > > > >> > The GCD EFI_MEMORY_UC and EFI_MEMORY_WC attributes will be mapped = to > > >> > IO and NC mode defined in PBMT field. > > >> > > > >> > v2: > > >> > - Generated patch for each package. > > >> > > > >> > Tuan Phan (3): > > >> > MdePkg.dec: RISC-V: Define override bit for Svpbmt extension > > >> > UefiCpuPkg: RISC-V: MMU: Support Svpbmt extension > > >> > OvmfPkg/RiscVVirt: Override Svpbmt extension > > >> > > > >> > MdePkg/MdePkg.dec | 2 ++ > > >> > OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 2 +- > > >> > .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 25 > ++++++++++++++++++- > > >> > .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 1 + > > >> > 4 files changed, 28 insertions(+), 2 deletions(-) > > >> > > > >> > -- > > >> > 2.25.1 > > >> > > >>=20 > > > > > > > -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#116125): https://edk2.groups.io/g/devel/message/116125 Mute This Topic: https://groups.io/mt/104211191/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- --0000000000002e0a350612746543 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Tue, Feb 27, 2024 at 8:42=E2=80=AF= PM Sunil V L <sunilvl@ventan= amicro.com> wrote:
Hi Tuan,

On Mon, Feb 26, 2024 at 08:34:22PM -0800, Tuan Phan wrote:
> Hi Sunil/ Andrei,
> Any comments on this series?
>
Did I miss your response to Laszlo's feedback on PATCH 2 - [1]? Apart from that, don't we need to handle EFI_MEMORY_WT similar to
EFI_MEMORY_WC?

Somehow I missed that feedback. Thanks.
Abo= ut EFI_MEMORY_WT, ARM treats it as EFI_MEMORY_WC under hood but I don't= see RISC-V specs mentions it explicitly so don't feel confident to add= that.=C2=A0
[1] - https://edk2.groups.io/g/devel/message/115243=

Thanks,
Sunil
> Regards,
>
> On Wed, Feb 14, 2024 at 10:16=E2=80=AFPM Tuan Phan via groups.io <tphan= =3D
> ventan= amicro.com@groups.io> wrote:
>
> >
> >
> > On Wed, Feb 14, 2024 at 9:43=E2=80=AFPM Warkentin, Andrei < > > a= ndrei.warkentin@intel.com> wrote:
> >
> >> Do you mind sharing a GH branch with the patch set?
> >>
> > https://github.com/pttuan/edk2/t= ree/tphan/riscv_mmu_svpbmt
> > Tuan
> >
> >>
> >> A
> >>
> >> > -----Original Message-----
> >> > From: Tuan Phan <tphan@ventanamicro.com>
> >> > Sent: Tuesday, February 6, 2024 7:29 PM
> >> > To: devel@edk2.groups.io
> >> > Cc: Kinney, Michael D <michael.d.kinney@intel.com>;
> >> > gaoliming@byosoft.com.cn; Liu, Zhiguang <zhiguang.liu@intel.com>;
> >> > k= raxel@redhat.com; lersek@redhat.com; Kumar, Rahul R
> >> > <rahul.r.kumar@intel.com>; Ni, Ray <ray.ni@intel.com>;
> >> > sunilvl@ventanamicro.com; Yao, Jiewen <jiewen.yao@intel.com>;
> >> Warkentin,
> >> > Andrei <andrei.warkentin@intel.com>; ardb+tianocore@kernel.org;= Tuan
> >> Phan
> >> > <tphan@ventanamicro.com>
> >> > Subject: [PATCH v2 0/3] RISC-V: Support Svpbmt extension=
> >> >
> >> > This patchset adds support for RISC-V Svpbmt extension.<= br> > >> >
> >> > The GCD EFI_MEMORY_UC and EFI_MEMORY_WC attributes will = be mapped to
> >> > IO and NC mode defined in PBMT field.
> >> >
> >> > v2:
> >> >=C2=A0 =C2=A0- Generated patch for each package.
> >> >
> >> > Tuan Phan (3):
> >> >=C2=A0 =C2=A0MdePkg.dec: RISC-V: Define override bit for = Svpbmt extension
> >> >=C2=A0 =C2=A0UefiCpuPkg: RISC-V: MMU: Support Svpbmt exte= nsion
> >> >=C2=A0 =C2=A0OvmfPkg/RiscVVirt: Override Svpbmt extension=
> >> >
> >> >=C2=A0 MdePkg/MdePkg.dec=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|= =C2=A0 2 ++
> >> >=C2=A0 OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 2 +-
> >> >=C2=A0 .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 25= ++++++++++++++++++-
> >> >=C2=A0 .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf=C2=A0 =C2= =A0 =C2=A0 =C2=A0|=C2=A0 1 +
> >> >=C2=A0 4 files changed, 28 insertions(+), 2 deletions(-)<= br> > >> >
> >> > --
> >> > 2.25.1
> >> > >
> >
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