From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 7C63B740032 for ; Tue, 31 Oct 2023 11:51:56 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=xTCs7CYt56vzD7bmJoacGNED2wKX1aym+UKUo4Oky8o=; c=relaxed/simple; d=groups.io; h=MIME-Version:References:In-Reply-To:From:Date:Message-ID:Subject:To:Cc:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Transfer-Encoding; s=20140610; t=1698753115; v=1; b=ny5wyjEEi/+rDWk5YwowuNH8Be+VVMAeXxX1AaxNV2zZHpebapniXP5M3dKNyZ2+lopbxG// fpWONAwor/9v+MljJlfQ6ombP9Eevk0olcg/FjZ4lKUehwkbvOtwDXYD/HQ91Pvgdv0peyaS1sk lzAoCrOQGXlK8eqerk1PYtQI= X-Received: by 127.0.0.2 with SMTP id njH2YY7687511xEwVIe3J7WZ; Tue, 31 Oct 2023 04:51:55 -0700 X-Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by mx.groups.io with SMTP id smtpd.web11.184348.1698753114580600344 for ; Tue, 31 Oct 2023 04:51:54 -0700 X-Received: from mail-ua1-f71.google.com (mail-ua1-f71.google.com [209.85.222.71]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-564-bGtr2Gl1ORGXYnJvQyMyaQ-1; Tue, 31 Oct 2023 07:51:52 -0400 X-MC-Unique: bGtr2Gl1ORGXYnJvQyMyaQ-1 X-Received: by mail-ua1-f71.google.com with SMTP id a1e0cc1a2514c-7b5fafe064fso2026980241.0 for ; Tue, 31 Oct 2023 04:51:52 -0700 (PDT) X-Gm-Message-State: 5a7YhVldarh7AQVYZ9G3zdcIx7686176AA= X-Received: by 2002:a67:c083:0:b0:457:6602:497b with SMTP id x3-20020a67c083000000b004576602497bmr11493045vsi.0.1698753112153; Tue, 31 Oct 2023 04:51:52 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFAiT1B2XVo2sSDzb5U7PQz5sLLLSbdEhKXIGMbKGHkonhgUGPmUReKTCX/1QM7OtMZJWrmF4CuAazKlaF1I+o= X-Received: by 2002:a67:c083:0:b0:457:6602:497b with SMTP id x3-20020a67c083000000b004576602497bmr11493034vsi.0.1698753111881; Tue, 31 Oct 2023 04:51:51 -0700 (PDT) MIME-Version: 1.0 References: <20231031053711.1416-1-hsienchieh.lin@amd.com> In-Reply-To: From: "Paolo Bonzini" Date: Tue, 31 Oct 2023 12:51:38 +0100 Message-ID: Subject: Re: [edk2-devel] [PATCH v2] UefiCpuPkg/MmSaveStateLib: Remove checking Smm Rev ID in AMD MmSaveStateLib To: "Attar, AbdulLateef (Abdul Lateef)" Cc: "Lin, Jacque" , "devel@edk2.groups.io" , Laszlo Ersek , Gerd Hoffmann , "Chang, Abner" X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pbonzini@redhat.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=ny5wyjEE; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=redhat.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io On Tue, Oct 31, 2023 at 10:16=E2=80=AFAM Attar, AbdulLateef (Abdul Lateef) wrote: > > [Public] > > +Laszlo, +Gerd, +Paolo > PR: https://github.com/tianocore/edk2/pull/4982 I left a comment in the PR. The patch is only correct if this code is only ever used on 64-bit processors. Note that KVM uses the legacy 32-bit format of the SMRAM state save area, if the virtual machine is configured to clear the LM bit of CPUID. Second, the commit message does not explain why you are doing this. Without such an explanation, it is impossible to provide more constructive feedback. Paolo > -----Original Message----- > From: Lin, Jacque > Sent: Tuesday, October 31, 2023 11:07 AM > To: devel@edk2.groups.io > Cc: Lin, Jacque ; Attar, AbdulLateef (Abdul Latee= f) ; Chang, Abner > Subject: [PATCH v2] UefiCpuPkg/MmSaveStateLib: Remove checking Smm Rev ID= in AMD MmSaveStateLib > > Remove checking SMM Rev ID in AMD Save State lib when reading Save State = Register EFI_MM_SAVE_STATE_REGISTER_IO. > For AMD, it is not necessary to check SmmRevId when reading Save State Re= gister EFI_MM_SAVE_STATE_REGISTER_IO. > > Cc: Abdul Lateef Attar > Cc: Abner Chang > Signed-off-by: Jacque Lin > --- > UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveState.c | 13 ------------- > 1 file changed, 13 deletions(-) > > diff --git a/UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveState.c b/UefiCpu= Pkg/Library/MmSaveStateLib/AmdMmSaveState.c > index 3315a6cc44..c4bf6ad4bb 100644 > --- a/UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveState.c > +++ b/UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveState.c > @@ -102,7 +102,6 @@ MmSaveStateReadRegister ( > OUT VOID *Buffer ) {- UINT32 = SmmRevId; EFI_MM_SAVE_STATE_IO_INFO *IoInfo; AMD_SMRAM_SAVE_STATE= _MAP *CpuSaveState; UINT8 DataWidth;@@ -124,18 +12= 3,6 @@ MmSaveStateReadRegister ( > // Check for special EFI_MM_SAVE_STATE_REGISTER_IO if (Register =3D= =3D EFI_MM_SAVE_STATE_REGISTER_IO) {- //- // Get SMM Revision ID- = //- MmSaveStateReadRegisterByIndex (CpuIndex, AMD_MM_SAVE_STATE_REGISTER= _SMMREVID_INDEX, sizeof (SmmRevId), &SmmRevId);-- //- // See if the C= PU supports the IOMisc register in the save state- //- if (SmmRevId <= AMD_SMM_MIN_REV_ID_X64) {- return EFI_NOT_FOUND;- }- // Check = if IO Restart Dword [IO Trap] is valid or not using bit 1. if (!(CpuSav= eState->x64.IO_DWord & 0x02u)) { return EFI_NOT_FOUND;-- > 2.36.1.windows.1 > -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#110402): https://edk2.groups.io/g/devel/message/110402 Mute This Topic: https://groups.io/mt/102292190/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-